KR20030047571A - Method of Forming Silicon Thin Film - Google Patents

Abstract

PURPOSE: A method for forming a silicon thin film is provided, to form a silicon thin film with high orientation and high crystallinity by employing a seed layer having a lattice constant similar to that of silicon. CONSTITUTION: The method comprises the steps of forming an intermediate crystal layer(12) as a seed layer on a substrate(12), which is made of a material having a lattice constant similar to that of silicon; forming a silicon layer(14) on the intermediate crystal layer; and heating the silicon layer(14). Preferably the crystal layer(12) is made of CeO2, CaF2 or ZnS, and is evaporation deposited at a temperature of 500 deg.C or less. Preferably the substrate is made of glass, plastic, a metal or a metal alloy, and it comprises further a buffer layer on the surface. The silicon layer is formed at a temperature of 25-500 deg.C and is an amorphous layer.

Description

Method of Forming Silicon Thin Film {Method of Forming Silicon Thin Film}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicon thin film for use in a thin film device, and more particularly, to a method for forming a silicon layer having high orientation and high crystallinity.

The method of forming a silicon thin film on a large area substrate is very important for obtaining high performance TFT and optoelectronic devices. Substrates for such devices have significantly larger sizes than those used in the manufacture of conventional semiconductor devices, for example, the size of the substrate for TFTs used in the most recent display devices is 1 m 2. In order to manufacture a thin film device on such a substrate, a high-quality semiconductor layer must be formed. Typically, a silicon film is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

When a silicon film such as an amorphous silicon film or a single crystal silicon film is deposited at a low temperature suitable for a glass substrate as the semiconductor layer, the deposited silicon thin film has poor crystalline quality. Therefore, heat treatment processes such as furnace annealing, rapid thermal annealing (RTA) and laser annealing should be performed to crystallize the deposited thin film or to improve crystallinity. .

However, furnace annealing is usually carried out at a temperature of more than 600 ℃, there was a problem that is not suitable for application to a glass substrate. Laser annealing can produce a high quality polycrystalline silicon film without significantly increasing the temperature of the substrate, but the process window of laser annealing to obtain uniform crystalline throughout the substrate is very small, and run to run uniformity This was poor and there was a problem of constantly monitoring the process. In addition, the RTA process may cause deformation of a substrate such as glass or worsen the crystalline of the RTA-treated thin film.

Therefore, in order to manufacture a crystalline silicon thin film having good crystallinity on a glass substrate, a low temperature heat treatment process is required. The low temperature heat treatment process should be applicable to the manufacture of thin films on large area amorphous substrates, the crystalline of which must be uniform and reproducible over the entire surface of the substrate. Preferably the thin film should have a preferred orientation with less grain boundary defects for good electrical transfer.

In general, a method of forming a silicon thin film can be largely divided into a case of depositing on an amorphous surface and a crystalline surface. When silicon is deposited on an amorphous substrate at low temperatures, the silicon atoms adsorbed on the substrate do not have enough thermal energy to diffuse sufficiently on the substrate surface before they are covered by the next arriving atoms. Once the silicon atoms are covered, the random arrangement of silicon atoms is fixed, so that the deposited film becomes an amorphous silicon film.

On the other hand, in the case of depositing a silicon film on an amorphous substrate at a higher substrate temperature, the adsorbed silicon atoms have sufficient thermal energy, so that they move and meet other diffused atoms to form clusters. Some clusters reach a critical size out of a stable state to form a nucleus, the density of which increases with time and the distance between the nucleus decreases. At critical nuclear densities, silicon atoms are more likely to diffuse and bond to existing nuclei than to form new ones, so the nucleus begins to grow.

On the other hand, when silicon is deposited on a crystalline substrate, the silicon film grows in a somewhat different manner. That is, the surface of the crystalline substrate has a low energy site (nucleation site) where the incoming atoms are preferably fixed to themselves, and the temperature at which crystalline silicon grows when the nucleation site already exists is lowered.

At this time, when the distance between the low energy sites on the substrate surface is equal to the inter-atomic distance of the silicon lattice, the silicon thin film is epitaxially grown. During epitaxial growth, the silicon thin film has the same orientation as the substrate surface layer on which the silicon thin film is deposited. Therefore, when the substrate surface layer is polycrystalline, the grown silicon thin film is also polycrystalline, and when the substrate surface layer is monocrystalline, the silicon layer thin film grows into single crystal.

Therefore, it is easy to form a crystalline silicon thin film on a crystalline substrate having a good lattice match with silicon rather than an amorphous substrate. Thus, in order to obtain a crystalline surface on a large area substrate, such as glass, an intermediate crystalline layer must be deposited as the seed layer.

This intermediate crystal layer should have a good lattice match with silicon and be formed at a temperature suitable for the silicon substrate. The intermediate crystal layer should have a relatively high resistivity compared to silicon so as not to adversely affect the device formed using the silicon thin film, and should be uniformly formed in the large area used for the display device and the optoelectronic device.

CeO ₂ , CaF ₂ , ZnS, etc. are used as intermediate crystal layers satisfying the above conditions, and these materials all have a cubic system similar to that of silicon, and the lattice constant of silicon And other lattice constants less than or equal to 1%.

As such, a method of manufacturing a thin film transistor using CaF ₂ or CeO ₂ as an intermediate crystal layer has been proposed in Korean Patent Laid-Open Publication No. 2001-2273. The prior art relates to a method of manufacturing a thin film transistor having a microcrystalline silicon thin film having high mobility evenly without contamination at 400 ° C or less.

To this end, in the related art, a CaF ₂ or CeO ₂ layer is deposited on a substrate as a seed layer, and microcrystalline silicon is grown directly at low temperature by PECVD (Plasma Enhanced Chemical Vapor Deposition) method on the seed layer. A silicon (μc-Si) thin film could be deposited.

However, since the prior art forms CeO ₂ or CaF ₂ having a lattice constant similar to that of silicon as a seed layer and then directly deposits a microcrystalline silicon thin film without an annealing process, the grain size is formed to be quite small. In this manner, a silicon film having a small grain size has considerably more grain boundaries than a polycrystalline silicon film. Since the microcrystalline silicon film having many grain boundaries has lower crystallinity than the polycrystalline silicon film or the single crystal silicon film, the microcrystalline silicon film has properties similar to those of the amorphous silicon film, so that the carrier moves much slower than the polycrystalline or single crystal silicon film.

For example, when the n-channel thin film transistor is made of a microcrystalline silicon film, a low electron mobility of 5 V / cm 2 or less is obtained, while the electron mobility of the polycrystalline silicon film is 50 V / cm 2 or more, in particular, the crystallinity of the silicon film In a very good case it will be higher than 300V / cm2. On the other hand, when the p-channel TFT is made of a polycrystalline silicon film, the hole mobility becomes 30 V / cm 2 or more, but in the case of the microcrystalline silicon film, there is a problem in that the transport of the hole is very difficult.

In addition, there is a problem that a high annealing temperature is required to make the microcrystalline silicon film into a polycrystalline silicon film.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to provide a method for producing a highly oriented and highly crystalline silicon thin film on a large area substrate at low deposition temperature and crystallization temperature. have.

Another object of the present invention is to provide a method for forming a silicon thin film having high orientation and crystallinity by using an intermediate crystal layer made of a material having a good lattice match with silicon on a substrate.

1 is a cross-sectional view illustrating a method of forming a silicon thin film according to an embodiment of the present invention;

2 is a cross-sectional view of a thin film transistor having a coplanar structure to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied;

3 is a cross-sectional structure diagram of a thin film transistor having an inter-staggered structure to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied;

4 is a cross-sectional structure diagram of a thin film transistor having a staggered structure to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied;

5a and 5b is a view showing the crystalline characteristics of the silicon layer produced by the silicon thin film forming method of the present invention,

<Description of the symbols for the main parts of the drawings>

10, 20, 30, 40: substrate 21, 31, 41: buffer layer

12, 22, 32, 42: seed layer 14, 24, 34, 44: silicon layer

25, 35, 45: gate insulating film 26, 36, 46: gate

27: interlayer insulating film 28: contact hole

29, 39, 49: source / drain electrodes

In order to achieve the above object of the present invention, the present invention comprises the steps of forming an intermediate crystal layer of a material substantially the same as silicon and lattice constant on the substrate; Forming a silicon layer on the intermediate crystal layer; It provides a silicon thin film forming method comprising the step of heat-treating the silicon layer.

The intermediate crystal layer is characterized in that CeO ₂ , CaF ₂ , or ZnS is deposited at a substrate temperature of 500 ° C. or lower and then heat-treated by furnace annealing, RTA, or laser annealing at a temperature of 600 ° C. or lower.

The substrate material is made of one of glass, plastic, metal or metal alloy film, wherein the substrate is a substrate having a buffer layer formed thereon.

The silicon layer is deposited as an amorphous film by CVD deposition or PVD deposition in a temperature range of 25 to 500 ℃ and then heat-treated by furnace annealing, RTA, or laser annealing at a temperature of less than 600 ℃.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining a method of forming a silicon thin film according to an embodiment of the present invention.

First, an intermediate crystal layer 12 is formed on the substrate 10, which serves as a seed layer that provides nucleation sites during subsequent silicon growth. A CeO ₂ , CaF ₂ , or ZnS film is deposited on the intermediate crystal layer 12 at a temperature of 500 ° C. or less.

In this case, the crystalline CeO ₂ film is deposited using a sputtering method, an electron beam deposition method, atomic layer deposition (atomic layer deposition), metal organic deposition (metal organic deposition), laser ablation method (laser ablation) and the like, crystalline CaF ₂ , The ZnS film is deposited by sputtering, atomic layer deposition, or the like. The substrate material may be a plastic, metal, metal alloy film or the like in addition to the glass substrate.

After the intermediate crystal layer 12 is deposited, an annealing process is performed to further improve the crystallinity of the intermediate crystal layer 12. The annealing process includes furnace annealing, rapid thermal annealing, or laser annealing at a temperature of 600 ° C. or lower. Through.

The intermediate crystalline layer 12 may be deposited polycrystalline or highly oriented polycrystalline depending on the deposition conditions or subsequent annealing conditions. It is preferable that the intermediate crystal layer 12 has a predetermined orientation than a random polycrystalline orientation, and the CeO ₂ film can be easily grown in a (111) orientation.

As described above, an intermediate crystal layer 12 having a desired crystallinity and orientation is formed as a seed layer, and then a silicon layer 14 is deposited on the intermediate crystal layer 12.

At this time, when the nucleus site (low energy site) is present on the surface of the crystalline substrate, if the deposition temperature is lowered or the deposition rate is increased, the silicon atoms diffuse to the low energy site before they are covered by the next reaching silicon atoms. Since there is not enough time to be deposited, the deposited silicon layer grows into an amorphous silicon film. Such an amorphous silicon film is converted into a crystalline state by a subsequent heat treatment, when the lower substrate surface is crystalline with a good lattice match with silicon than when the lower substrate surface is amorphous without the need for nucleation. The time / temperature budget for the heat treatment is lowered.

Therefore, since the crystallinity of the silicon layer 14 is affected by the deposition parameter, in the embodiment of the present invention, the silicon layer 14 deposited on the intermediate crystal layer 12 may have a lower deposition temperature or a higher increase. It is grown to an amorphous film by depositing at a deposition rate.

The silicon layer 14 is deposited at a deposition temperature suitable for the substrate 10 by, for example, a CVD method such as LPCVD or PECVD, or a PVD technique such as stuffing or vacuum deposition, for example, 25 ° C to 500 ° C. For example, when the silicon layer 14 is deposited using the sputtering method, since the deposition is possible at room temperature, the silicon layer 14 may be deposited at a deposition temperature of 25 ° C.

In order to improve the crystallinity of the silicon layer 14, as described above, a process of depositing an amorphous silicon layer 14 on the crystalline intermediate crystal layer 12 and then performing a heat treatment is performed on the amorphous substrate surface. Since the annealing temperature is reduced compared to the process of depositing and then heat-treating the silicon layer 14, furnace annealing, RTA, or laser annealing can be performed at a lower annealing temperature, for example, a temperature of 600 ° C. or less. .

As described above, the silicon thin film forming method of the present invention controls the deposition temperature and the deposition rate, and for example, deposits the silicon layer 14 at a relatively lower deposition temperature or higher deposition rate than when depositing a more crystalline silicon film. By growing the silicon layer 14 to an amorphous film, the crystallization process is performed at a relatively low annealing temperature. Accordingly, it is possible to form the crystalline silicon layer 14 having a grain size larger than the microcrystalline, thereby improving mobility characteristics.

5A and 5B illustrate the characteristics of a silicon thin film formed according to an embodiment of the present invention, in which samples # 1, # 2, and # 3 are all annealed in an N 2 atmosphere at an annealing temperature of 500 ° C. for 2 hours. . It can be seen that crystallinity and orientation are increased when the annealing process is performed after deposition.

The method of forming a polycrystalline or highly oriented silicon layer as described above can be applied to fabricate thin film transistors or optoelectronic devices.

A method of manufacturing a thin film transistor by applying a polycrystalline or highly oriented silicon layer forming method according to an embodiment of the present invention will be described with reference to FIGS. 2 to 4 as follows.

2 illustrates a cross-sectional structure of a thin film transistor having a coplanar structure to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied.

Referring to FIG. 2, a buffer layer 21 such as SiO ₂ or SiNx is formed on a substrate 20, and an intermediate crystal layer 22 of CeO ₂ , CaF ₂ , or ZnS is deposited thereon as a seed layer. In addition, an annealing process is performed to improve the crystallinity of the intermediate crystal layer 22.

Glass, plastic, metal or metal alloy film is used as the substrate 20, and the intermediate crystal layer 22 is deposited by sputtering, electron beam deposition, atomic layer deposition, metal organic deposition or laser ablation. The process is carried out by a furnace annealing, RTA, or laser annealing process.

The silicon layer 24 is deposited, annealed and patterned on the intermediate crystal layer 22 in the same manner as described in the embodiment to form a semiconductor layer for a thin film transistor. The silicon layer is deposited by a CVD method such as PECVD or LPCVD or a PVD method such as sputtering or vacuum deposition, and the annealing process is performed by a furnace annealing, RTA, or laser annealing process.

A gate insulating film 25 is formed on the entire surface of the substrate, and a gate electrode 26 is formed on the gate insulating film 25 corresponding to the semiconductor layer 24. Source / drain regions 24a are formed by ion implanting n-type or p-type impurities into the semiconductor layer 24 using the gate electrode 26 as a mask.

An interlayer insulating layer 27 is formed on the gate insulating layer 25 including the gate electrode 26, and a contact hole 28 exposing a portion of the source / drain region 24a is formed. Finally, a source / drain electrode 29 in contact with the source / drain region 24a is formed through the contact hole 28 to manufacture a thin film transistor having a coplanar structure according to the present invention.

3 illustrates a cross-sectional structure of an inverter staggered thin film transistor to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied.

Referring to FIG. 3, a buffer layer 31, such as SiO ₂ or SiNx, is formed on a substrate 30, a gate electrode 36 is formed on the buffer layer 31, and a gate insulating layer 35 is formed over the entire surface of the substrate. To form. An intermediate crystal layer 32 of CeO ₂ , CaF ₂ , or ZnS is deposited on the gate insulating layer 35 as a seed layer, and an annealing process is performed to improve crystallinity of the intermediate crystal layer 32. .

Glass, plastic, metal or metal alloy film is used as the substrate 30, the intermediate crystal layer 32 is deposited by sputtering, electron beam deposition, atomic layer deposition, metal organic deposition or laser ablation method, annealing The process is carried out by a furnace annealing, RTA, or laser annealing process.

The silicon layer 34 is deposited, annealed and patterned on the intermediate crystal layer 32 in the same manner as described above to form a thin film transistor semiconductor layer at a portion corresponding to the gate electrode 36. The silicon layer 34 is deposited by a CVD method such as PECVD or LPCVD or a PVD method such as sputtering or vacuum deposition, and the annealing process is performed by a furnace annealing, RTA, or laser annealing process.

N-type or p-type impurities are ion-implanted into the semiconductor layer 34 to form a source / drain region 34a. A source / drain electrode material is deposited on the entire surface of the substrate and then patterned to form a source / drain electrode 39 in contact with the source / drain region 34a.

In this case, the intermediate crystal layer 32 may be used as a gate insulating layer, and as shown in FIG. 3, the gate insulating layer 35 may be deposited on the intermediate crystal layer 32 to form a two-layer structure. The deposition process of the insulating layer 35 may be omitted to form a single structure of the seed layer 32 alone.

4 illustrates a cross-sectional structure of a staggered thin film transistor to which a silicon thin film forming method according to an exemplary embodiment of the present invention is applied.

Referring to FIG. 4, a buffer layer 41 such as SiO ₂ or SiNx is formed on a substrate 40, and an intermediate crystal layer 42 of CeO ₂ , CaF ₂ , or ZnS is formed on the buffer layer 41. Deposited as a seed layer, an annealing process is performed to improve the crystallinity of the intermediate crystal layer 42.

Glass, plastic, metal or metal alloy film is used as the substrate 40, the intermediate crystal layer 42 is deposited by sputtering, electron beam deposition, atomic layer deposition, metal organic deposition or laser ablation method, annealing The process is carried out by a furnace annealing, RTA, or laser annealing process.

A source / drain electrode material is deposited on the intermediate crystal layer 42 and then patterned to form a source / drain electrode 49. The source / drain electrode 49 is formed on the intermediate crystal layer 42 including the source / drain electrode 49. As described above, the silicon layer 44 is deposited, annealed, and patterned to form a semiconductor layer for a thin film transistor. The silicon layer 44 is deposited by a CVD method such as PECVD or LPCVD or a PVD method such as sputtering or vacuum deposition, and the annealing process is performed by a furnace annealing, RTA, or laser annealing process.

If the gate insulating film 45 is formed on the entire surface of the substrate, the gate electrode 46 is formed thereon, and then the source / drain regions 44a are formed by ion implanting n-type or p-type impurities into the semiconductor layer 44. The thin film transistor of the stagger structure of this invention is obtained.

Instead of forming a silicon layer on the seed layer, the present invention may apply a method of inducing crystallization of the silicon layer by depositing and heat treating the seed layer on the silicon layer. In addition, the present invention can be applied not only to the above-described thin film transistor, but also to a method for manufacturing a solar cell, for example, a pn junction solar cell, a Schottky barrier solar cell, a MIS solar cell, and a pin device.

As described above, the silicon thin film forming method of the present invention has the advantage of forming a highly crystalline silicon layer having a high orientation and a high crystallinity by depositing and annealing the silicon layer at a low temperature using a seed layer having almost the same lattice constant as silicon. There is this.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

Forming an intermediate crystal layer of a material of substantially the same lattice constant as silicon on the substrate; Forming a silicon layer on the intermediate crystal layer; And heat-treating the silicon layer. The method of claim 1, wherein the intermediate crystal layer is formed of one of CeO ₂ , CaF ₂ , and ZnS. The method of claim 1, wherein the intermediate crystal layer is deposited at a substrate temperature of 500 ° C. or less. The method of claim 1, further comprising depositing and then annealing the intermediate crystal layer. The method of claim 4, wherein the intermediate crystal layer is performed by a furnace annealing, RTA, or laser annealing process at a temperature of 600 ° C. or less. The method of claim 1, wherein the substrate material is one of glass, plastic, metal, or metal alloy film. The method of claim 1, wherein the substrate is a substrate on which a buffer layer is formed. The method of claim 1, wherein the silicon layer is deposited as an amorphous film in a temperature range of 25 to 500 ℃. The method of claim 8, wherein the silicon layer is deposited using one of a CVD deposition method and a PVD deposition method. The method of claim 1, wherein the annealing of the silicon layer is performed by furnace annealing, RTA, or laser annealing at a temperature of 600 ° C. or less.