JPS61100967A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS61100967A JPS61100967A JP22155784A JP22155784A JPS61100967A JP S61100967 A JPS61100967 A JP S61100967A JP 22155784 A JP22155784 A JP 22155784A JP 22155784 A JP22155784 A JP 22155784A JP S61100967 A JPS61100967 A JP S61100967A
- Authority
- JP
- Japan
- Prior art keywords
- region
- silicon layer
- layer
- crystal silicon
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 43
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- VXUYXOFXAQZZMF-UHFFFAOYSA-N titanium(IV) isopropoxide Chemical group CC(C)O[Ti](OC(C)C)(OC(C)C)OC(C)C VXUYXOFXAQZZMF-UHFFFAOYSA-N 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜トランジス、りの構造に関するものであ
る＠
〔従来の技術〕
従来の薄膜トランジスタの構造は、特開昭５９−２２３
６５・特開昭５９−９６７６９の様に、動作層であるシ
リコン層の膜厚は、コンタクトホール形成時に問題がな
く、かつトランジスタ特性に、コンタクト抵抗等の寄生
抵抗が影響しない膜厚以上の均一膜厚であった。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the structure of a thin film transistor.
65. As in JP-A-59-96769, the thickness of the silicon layer that is the active layer is uniform enough to be at least as thick as there is no problem when forming contact holes, and that parasitic resistance such as contact resistance does not affect the transistor characteristics. The film thickness was
〔発明が解決しようとしている問題点〕しかし、前述の
従来技術では、薄膜トランジスタ（以下ＴＸＰＴと記す
。）特性において、動作層が非単結晶シリコンであるこ
とからオン電流値が小さくオフ状態でのリーク電流が大
きいためオン／オフ比が小さくおさえられる、またしき
い値電圧が高く、応答速度が鈍いという問題点を有する
。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the characteristics of a thin film transistor (hereinafter referred to as TXPT) are that the on-current value is small and leakage occurs in the off-state because the active layer is made of non-monocrystalline silicon. Since the current is large, the on/off ratio is kept small, the threshold voltage is high, and the response speed is slow.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、動作半導体層である非単結晶シ
リコン層の少なくともチャネル領域の非単結晶シリコン
層膜厚は薄くし、ソース領域およびドレイン領域の少な
くともコンタクト形成領域は・コンタクトホール形成時
に、歩留り良く形成が可能で、フンタクト抵抗等の寄生
抵抗がトランジスタ特性に影響を与えない膜厚でＴＩＦ
Ｔを構成し、オフ電流値を下げ、オン電流値を上げオン
／オフ比を大きくシ、シきい値電圧を下げ、高速応答を
可能にするなど、良好なトランジスタ特性を有するＴＩ
Ｆ’ｌ’構造を提供するところにある。The present invention is intended to solve these problems, and its purpose is to reduce the thickness of the non-single-crystal silicon layer at least in the channel region of the non-single-crystal silicon layer, which is an active semiconductor layer, and to reduce the thickness of the non-single-crystal silicon layer in the source region. At least the contact formation region of the drain region and the drain region should be formed using TIF with a film thickness that can be formed with good yield when forming contact holes, and that parasitic resistance such as direct resistance does not affect transistor characteristics.
TI has good transistor characteristics, such as lowering the off-current value, increasing the on-current value, increasing the on/off ratio, lowering the threshold voltage, and enabling high-speed response.
It provides an F'l' structure.
本発明のＴＩＦＴは、動作半導体層である非単結晶シリ
コン層中の少なくともチャネル領域に、イオン打込みに
より形成した絶縁層を有し、チャネル領域の非単結晶シ
リコン層膜厚は薄ぐ、外部配線とコンタクトを形成する
ソース領域およびドレイン領域の少なくともコンタクト
形成領域は、良好なフンタクトが可能であるように厚く
した構造を特徴とする。The TIFT of the present invention has an insulating layer formed by ion implantation at least in the channel region of the non-single crystal silicon layer that is the active semiconductor layer, the non-single crystal silicon layer in the channel region is thin, and the external wiring At least the contact forming regions of the source region and the drain region that form a contact with the semiconductor device are characterized by a thick structure so as to enable good contact.
本発明の上記構成によれば、チャネル領域の膜厚を薄く
シ、少なくともフンタクトを形成するソース領域および
ドレイン領域の膜厚は、フンタクトホール形成時に歩留
り低下に影響することなくかつ良好なコンタクト特性が
得られるような膜厚となるような構造としたので、しき
い値電圧の低下、オフ状態のリーク電流の減少、オン電
流の増加さらには、高速応答が実現できるものである口
〔実施例〕
第１図は、本発明の実施例におけるＴＩＦＴの構造図で
あって、第２図の従来のＴ？Ｔ構造と比較して、イオン
打込みにより形成される絶縁層２の厚さだけ、チャネル
領域４の非単結晶シリコン層の膜厚が薄くなっている。According to the above structure of the present invention, the film thickness of the channel region can be made thin, and at least the film thickness of the source region and the drain region forming the contact hole can be made thin enough to have good contact characteristics without affecting the yield reduction when forming the contact hole. The structure has a film thickness that allows for a reduction in threshold voltage, a reduction in off-state leakage current, an increase in on-state current, and a high-speed response. ] FIG. 1 is a structural diagram of a TIFT according to an embodiment of the present invention, and is a structural diagram of a TIFT according to an embodiment of the present invention. Compared to the T structure, the thickness of the non-single crystal silicon layer in the channel region 4 is thinner by the thickness of the insulating layer 2 formed by ion implantation.
第３図には、本発明による？ＩＦＴ構造を実現する為の
製造工程を示す。第３図を用いて、製造工程を説明する
。FIG. 3 shows the results according to the present invention? The manufacturing process for realizing the IFT structure is shown. The manufacturing process will be explained using FIG. 3.
最初に、絶縁基板１上に、非単結晶シリコン層を、化学
気相成長法（以下ＯＶＤと記す・）等により形成し、必
要な形状にエツチングを行ない、イオン打込み用のマス
クを、レジスト１０により少なくともチャネル領域４上
にはレジスト１０が残らないように形成しイオン打込み
を行なう０このようにして第３図（α）の如くなる。イ
オン打込みには・酸素イオンあるいは窒素イオンの使用
が可能である。First, a non-single-crystal silicon layer is formed on an insulating substrate 1 by chemical vapor deposition (hereinafter referred to as OVD), etched into a required shape, and a resist 10 is used as a mask for ion implantation. Therefore, the resist 10 is formed so that no resist 10 remains at least on the channel region 4, and ion implantation is performed.In this way, the result is as shown in FIG. 3(α). For ion implantation, oxygen ions or nitrogen ions can be used.
続いて、レジストマスクをハクリした後、非単結晶シリ
コン層９の熱酸化により、ゲート絶縁膜５を形成する＠
この際、イオン打込みした層２のアニールも同時に行な
うことができる。Subsequently, after peeling off the resist mask, the gate insulating film 5 is formed by thermal oxidation of the non-single crystal silicon layer 9.
At this time, the ion-implanted layer 2 can also be annealed at the same time.
続いて、不純物元素の熱拡散等で低抵抗化した非単結晶
シリコン層あるいは、ゲート配線抵抗が問題となる場合
には高融点金属またはそのシリサイド等を使用して、ゲ
ート電極６を形成し、不純物イオンの打ち込みにより、
ソース領域およびドレイン領域３を形成する。この際ゲ
ート電極６をマスクに打ち込むので、自己整合が可能と
なる。Next, a gate electrode 6 is formed using a non-single crystal silicon layer whose resistance has been lowered by thermal diffusion of impurity elements, or a high melting point metal or its silicide if gate wiring resistance is a problem, By implanting impurity ions,
A source region and a drain region 3 are formed. At this time, since the gate electrode 6 is implanted into the mask, self-alignment becomes possible.
このようにして、第［（Ｃ）の如くなる。In this way, the result becomes as shown in No. (C).
次に、相関絶縁膜７を形成し、コンタクトホールを形成
した後、Ａ Ｉ！、 −Ｓ ｉ 、 Ａ ｆｔ −Ｓ
ｉ −Ｏｕ等電極材料によりソース電極およびドレイン
電極８を形成することにより、第３図（ｄ）の如く構造
となるＯ
以上のようにして、本発明によるＴＰＴ構造の実現が可
能となる。Next, after forming a correlation insulating film 7 and forming contact holes, A I! , -S i , A ft -S
By forming the source electrode and drain electrode 8 using an electrode material such as i-Ou, a structure as shown in FIG. 3(d) is obtained.As described above, it becomes possible to realize the TPT structure according to the present invention.
さらに、第３図（ａ）においては、イオン打込みのマス
ク１０をレジストにより形成したが、このマスクをｃｖ
ｎ等で形成した酸化膜１形成した構造を第４図に示す。Furthermore, in FIG. 3(a), the mask 10 for ion implantation was formed of resist, but this mask was
FIG. 4 shows a structure in which an oxide film 1 made of n or the like is formed.
マスクとして形成した酸化膜は層間絶縁膜の一部として
使用できる。さらに、界面状態がＴＰＴ特性に敏感に影
響する非単結晶シリコン層９０表面が、レジスト１０で
汚染されることなく構成できるので、トランジスタ特性
のバラツキが小さくなる。The oxide film formed as a mask can be used as part of an interlayer insulating film. Furthermore, since the surface of the non-single crystal silicon layer 90, whose interface state sensitively affects the TPT characteristics, can be constructed without being contaminated by the resist 10, variations in transistor characteristics are reduced.
続いて、本発明による作用を詳しく説明すると、本発明
の上記構成によれば、チャネル領域の膜厚を薄くしたＴ
ＰＴ構造であるので、動作半導体層である非単結晶シリ
コン層中のチャネル領域において、ゲート電圧の増加に
より広がる空乏層は、低ゲート電圧で、チャネル領域を
満たすことになる。また、空乏層がチャネル領域を満た
すゲート電圧（以後ＶＴと記す）以上のゲート電圧（以
後’ＶＧと記す）を印加すれば、（７ｏ−７Ｔ）なる電
圧は、非単結晶シリコンの７エルミレベルを曲げること
に使用され、反転層形成に使用される０一般にＭＯＳ）
ランジスタにおけるしきい値電圧（以後ｖｔｈと記す。Next, the effects of the present invention will be explained in detail. According to the above structure of the present invention, T
Because of the PT structure, the depletion layer that expands as the gate voltage increases in the channel region in the non-single crystal silicon layer that is the active semiconductor layer fills the channel region with a low gate voltage. In addition, if a gate voltage (hereinafter referred to as 'VG) higher than the gate voltage (hereinafter referred to as VT) at which the depletion layer fills the channel region is applied, the voltage (7o-7T) will be at the 7 Hermi level of non-single crystal silicon. used for bending and forming an inversion layer (generally MOS)
Threshold voltage (hereinafter referred to as vth) in a transistor.
）は次式で表わされる０Ｖｔｈ＝Ｖｙｎ−）−２−１φ
７１−１−８・Ｎａ＊Ｗａ／ＣｏｘここでＶ ＰＢはフ
ラットバンド電圧、φνは７工ルミ準位、ｑは電荷量、
Ｎｓは不純物濃度、Ｗａは空乏層厚、Ｏｏｘはゲート容
量である。) is expressed by the following formula: 0Vth=Vyn-)-2-1φ
71-1-8・Na*Wa/Cox where V PB is the flat band voltage, φν is the 7-Eluminum level, q is the amount of charge,
Ns is the impurity concentration, Wa is the depletion layer thickness, and Oox is the gate capacitance.
上式のＷ８以外の変数の値が一定であるならば、’ｖｔ
ｈは、Ｗｓを小さくすることで、減少することになる。If the values of variables other than W8 in the above equation are constant, 'vt
h will decrease by decreasing Ws.
故に・本発明のＴＰＴ構造のように、Ｗｓすなわち空乏
層厚を有限な非単結晶シリコン層を用いて、制御するこ
とにより、しきい値電圧を下げることが可能となる。Therefore, as in the TPT structure of the present invention, by controlling Ws, that is, the thickness of the depletion layer using a finite non-single crystal silicon layer, it is possible to lower the threshold voltage.
また、オフ状態でのリーク電流を決定するのは蔦チャネ
ル領域の抵抗値である。オフ状態でのチャネル領域の非
単結晶シリコン層の比抵抗率をρＢとし、チャネル幅を
Ｗ１チャネル長をＬ１チャネル領域の非単結晶シリコン
層の膜厚をＷｓとすれば・オフ状態でのチャネル抵抗Ｒ
Ｏｆｆは、Ｒｏｆｆ ＝ρ８・Ｉ＋ ／ Ｗ−Ｗ ｓと
なる。したがって、オフ状態でのチャネル抵抗は、チャ
ネル領補の非単結晶シリコン層の膜厚を薄くすることで
、増加する。すなわち・本発明の如く構造にすることで
、オフ状態でのチャネル抵抗が増加し、オフ状態でのリ
ーク電流は減少する０
また、ＭＯＳ）ランジスタの理論式より理解できるよう
にオン状態での電流すなわちオン電流は１（ＶＧ−７ｔ
ｈ）の関数であり、（ｖｏ−ｖｔｈ）の値の増加で・オ
ン電流は増加する。本発明のＴＩＰＴ構造を実現するこ
とで、ｖｔｈが下がるので、オン電流が増加することに
なる。したがって、オン電流が増加し、前述のごとくオ
フ電流は減少するので、トランジスタ応答特性に必要な
オン／オフ比が増加することになる。Furthermore, it is the resistance value of the vine channel region that determines the leakage current in the off state. If the resistivity of the non-single crystal silicon layer in the channel region in the off state is ρB, the channel width is W1, the channel length is L1, the thickness of the non-single crystal silicon layer in the channel region is Ws, then the channel in the off state is Resistance R
Off is Roff=ρ8·I+/W−Ws. Therefore, the channel resistance in the off state increases by reducing the thickness of the non-single crystal silicon layer in the channel region. That is, by structuring as in the present invention, the channel resistance in the OFF state increases and the leakage current in the OFF state decreases.Also, as can be understood from the theoretical formula for a MOS transistor, the current in the ON state increases. In other words, the on-current is 1 (VG-7t
h), and as the value of (vo-vth) increases, the on-state current increases. By realizing the TIPT structure of the present invention, vth decreases, so on-current increases. Therefore, since the on-current increases and the off-current decreases as described above, the on/off ratio required for transistor response characteristics increases.
以上のことは、第５図に示す’１’ＦＴ特性の１例より
理解できる。さらに第５図より、本発明の構造にするこ
とで、特性の立ち上がりが急峻となり、より高速応答が
可能なＴＩＰＴ特性となることが理解できる。第５図に
は例としてＮチャネルＴＩＦ’ｌ’の特性が示しである
が、ＰチャネルＴＩＦＴにおいても同様な特性が得られ
る。The above can be understood from an example of the '1' FT characteristic shown in FIG. Further, from FIG. 5, it can be seen that by adopting the structure of the present invention, the rise of the characteristic becomes steeper, resulting in a TIPT characteristic that enables faster response. Although FIG. 5 shows the characteristics of an N-channel TIF'l' as an example, similar characteristics can be obtained in a P-channel TIFT.
加えて、本発明では、外部配線とのコンタクトにおいて
、動作半導体層のソース領域およびドレイン領域の少な
くともコンタクト形成領域は、量産工程においても、フ
ンタクトホールが歩留り良く形成でき、しかもコンタク
ト抵抗等寄生抵抗が、ＴＩＰＴ特性に影響しない膜厚と
しているので、それら要因に影響されることなく、前述
したような、高性能なＴ、Ｆ Ｔ特性が得られる。In addition, in the present invention, in contact with external wiring, at least the contact formation regions of the source region and drain region of the active semiconductor layer can be formed with a high yield even in the mass production process, and parasitic resistance such as contact resistance can be formed. However, since the film thickness is set such that it does not affect the TIPT characteristics, the high performance T and FT characteristics described above can be obtained without being affected by these factors.
以上述べたように本発明によれば、酸素あるいは窒素の
イオン打込みにより形成される絶縁層により動作半導体
層である非単結晶シリコン層の少なくともチャネル領域
の膜厚を薄くシ、フンタクトを形成するソース領域およ
びドレイン領域の膜厚は、チャネル領域より厚くすると
いうＴＰＴ構造にすることにより、しきい値電流値がＯ
〜３ｖと低くなり、オフ電流が１ピコアンペア以下、オ
ン電流も１０マイクロアンペア以上となり、オン／オフ
比でも７桁以上という、高性能なＴ’ＦＴ特性が得られ
る◎またＮチャネルＴＩＦＴだけでなくＰチャネルＴＮ
Ｔについても同様に高性能な特性が、バランス良く得ら
れるので、片チャネルのデバイスだけでなく、各種０Ｍ
Ｏ８構造のデバイスへの応用が可能となる。As described above, according to the present invention, the film thickness of at least the channel region of the non-single-crystal silicon layer, which is the active semiconductor layer, can be thinned by the insulating layer formed by ion implantation of oxygen or nitrogen, and the film thickness of the non-single crystal silicon layer, which is the active semiconductor layer, can be reduced. By adopting a TPT structure in which the film thickness of the region and drain region is thicker than that of the channel region, the threshold current value can be reduced to O.
~3V, the off current is less than 1 picoampere, the on current is more than 10 microamperes, and the on/off ratio is more than 7 digits, providing high-performance T'FT characteristics.In addition to N-channel TIFT, P channel TN
Similarly, high-performance characteristics can be obtained in a well-balanced manner for T, so it can be used not only for single channel devices but also for various 0M
Application to devices with O8 structure becomes possible.
加えて構造上、少なくともフンタクトを形成するソース
領域およびドレイン領域の膜厚を厚くしているので、量
産工程を考慮した場合にも、歩留り良くフンタクトホー
ル形成が可能となり、良好なコンタクト特性を実現する
という効果を有する。In addition, due to the structure, the thickness of at least the source and drain regions that form the contact hole is thicker, so even when considering the mass production process, it is possible to form the contact hole with a high yield and achieve good contact characteristics. It has the effect of
第１図は本発明の薄膜トランジスタの構造の一実施例を
示す主要断面図。
第２図は従来の薄膜トランジスタの構造を示す主要断面
図。
第５図（α）〜（ｄ）は本発明の薄膜トランジスタを実
現するための製造工程図。
第４図は本発明の薄膜トランジスタの構造の一実施例を
示す主要断面図。
第５図は本発明の構造と従来の構造の薄膜トランジスタ
のトランジスタ特性を示す図◇１・・・絶縁基板
２・・・イオン打込み絶縁層
３・・・ソース領域およびドレイン領域４・・・チャネ
ル領域 ５・・・ゲート絶縁層６・・・ゲート電極
７・・一層間絶縁層８・・・ソース電極およびドレ
イン領域９・・・非単結晶シリコン層
１０・・−レジスト層
１１・・・酸素イオンビームあるいは窒素イオンビーム
１２・・・不純物イオンビーム
１３・・・マスク絶縁層
第１図
第２図
０λン
ｔ＆）
第３図
第４図FIG. 1 is a main cross-sectional view showing one embodiment of the structure of a thin film transistor according to the present invention. FIG. 2 is a main cross-sectional view showing the structure of a conventional thin film transistor. FIGS. 5(α) to 5(d) are manufacturing process diagrams for realizing the thin film transistor of the present invention. FIG. 4 is a main cross-sectional view showing one embodiment of the structure of a thin film transistor of the present invention. FIG. 5 is a diagram showing the transistor characteristics of thin film transistors having the structure of the present invention and the conventional structure. 5... Gate insulating layer 6... Gate electrode
7... Interlayer insulating layer 8... Source electrode and drain region 9... Non-single crystal silicon layer 10...-Resist layer 11... Oxygen ion beam or nitrogen ion beam 12... Impurity ion beam 13 ...Mask insulating layer Fig. 1 Fig. 2 0λnt&) Fig. 3 Fig. 4
Claims (3)
た薄膜トランジスタにおいて、前記シリコン層に形成さ
れる少なくともチャネル領域に、選択的イオン打込みに
より形成した絶縁層を有し局所的に、前記チャネル領域
のシリコン層膜厚を薄くした構造を特徴とする薄膜トラ
ンジスタ。(1) In a thin film transistor in which a silicon layer on an insulating substrate is used as an active semiconductor layer, an insulating layer formed by selective ion implantation is provided at least in a channel region formed in the silicon layer, and the insulating layer is locally formed in the channel region. A thin film transistor characterized by a structure in which the thickness of the silicon layer in the region is reduced.
記シリコンの酸化膜および窒化膜であることを特徴とす
る特許請求の範囲第１項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the insulating layer formed by selective ion implantation is an oxide film and a nitride film of the silicon.
レイン領域と外部配線とのコンタクト形成領域の前記シ
リコン層の膜厚は、チャネル領域の膜厚より厚いことを
特徴とする特許請求の範囲第１項記載の薄膜トランジス
タ。(3) The film thickness of the silicon layer in the contact formation region between the source region and the drain region formed in the silicon layer and the external wiring is thicker than the film thickness of the channel region. The thin film transistor described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22155784A JPH0612826B2 (en) | 1984-10-22 | 1984-10-22 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22155784A JPH0612826B2 (en) | 1984-10-22 | 1984-10-22 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61100967A true JPS61100967A (en) | 1986-05-19 |
| JPH0612826B2 JPH0612826B2 (en) | 1994-02-16 |
Family
ID=16768586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22155784A Expired - Lifetime JPH0612826B2 (en) | 1984-10-22 | 1984-10-22 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0612826B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05136167A (en) * | 1991-09-20 | 1993-06-01 | Mitsubishi Electric Corp | Thin film transistor and its manufacture |
| US5821563A (en) * | 1990-12-25 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device free from reverse leakage and throw leakage |
| US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
| US6214684B1 (en) * | 1995-09-29 | 2001-04-10 | Canon Kabushiki Kaisha | Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
| US7253437B2 (en) | 1990-12-25 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device having a thin film transistor |
-
1984
- 1984-10-22 JP JP22155784A patent/JPH0612826B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821563A (en) * | 1990-12-25 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device free from reverse leakage and throw leakage |
| US6838698B1 (en) | 1990-12-25 | 2005-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having source/channel or drain/channel boundary regions |
| US7253437B2 (en) | 1990-12-25 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device having a thin film transistor |
| US7375375B2 (en) | 1990-12-25 | 2008-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JPH05136167A (en) * | 1991-09-20 | 1993-06-01 | Mitsubishi Electric Corp | Thin film transistor and its manufacture |
| US5281828A (en) * | 1991-09-20 | 1994-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor with reduced leakage current |
| US5436184A (en) * | 1991-09-20 | 1995-07-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
| US6380036B1 (en) | 1994-06-22 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US6214684B1 (en) * | 1995-09-29 | 2001-04-10 | Canon Kabushiki Kaisha | Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0612826B2 (en) | 1994-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5320974A (en) | Method for making semiconductor transistor device by implanting punch through stoppers | |
| US5371024A (en) | Semiconductor device and process for manufacturing the same | |
| US4463492A (en) | Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state | |
| US5898203A (en) | Semiconductor device having solid phase diffusion sources | |
| US4395726A (en) | Semiconductor device of silicon on sapphire structure having FETs with different thickness polycrystalline silicon films | |
| US6163053A (en) | Semiconductor device having opposite-polarity region under channel | |
| US4891326A (en) | Semiconductor device and a process for manufacturing the same | |
| JPH02237160A (en) | Semiconductor device | |
| US6596593B2 (en) | Method of manufacturing semiconductor device employing oxygen implantation | |
| US6451676B2 (en) | Method for setting the threshold voltage of a MOS transistor | |
| JPS61100967A (en) | Thin-film transistor | |
| JPH08330590A (en) | Insulated gate field-effect transistor structure and its manufacture | |
| JPH09135029A (en) | Mis semiconductor device and manufacturing method therefor | |
| US4196507A (en) | Method of fabricating MNOS transistors having implanted channels | |
| JPH05198804A (en) | Semiconductor device and manufacturing method thereof | |
| JPH05218417A (en) | Integrated circuit transistor structure and manufacture thereof | |
| JPS5868979A (en) | Semiconductor device | |
| JP2611363B2 (en) | Insulated gate field effect transistor and method of manufacturing the same | |
| JPH0812917B2 (en) | Method of operating MIS transistor and MIS transistor | |
| JP2513634B2 (en) | Method for manufacturing semiconductor device | |
| JPH05335503A (en) | Manufacture of semiconductor device | |
| JP2796655B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH09252130A (en) | Semiconductor device and its manufacturing method | |
| KR910009742B1 (en) | High voltage semiconductor device and its manufacturing method | |
| JPH05235290A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |