JPS6117153B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a junction field effect transistor having a high breakdown voltage and a large drain saturation current.

An example of a conventional junction field effect transistor formed on a dielectric insulating isolation substrate or a high-ratio/low-resistance semiconductor substrate is schematically shown in FIG. 1st
In the figure, 1 is a dielectric insulating isolation substrate, 2 is an n-type semiconductor layer, 3 and 4 are n ⁺ type source and drain diffusion regions, 5 is a p ⁺ type gate diffusion region, and 6 is a protective film. Silicon dioxide coating, 7
is metal electrode wiring.

A so-called junction field effect transistor is operated by controlling the thickness of a channel region 8 connecting a drain electrode 4 and a source electrode 3 with a depletion layer region 9 extending from a gate electrode 5. In this case, the resistance Ron at the time of rising of the junction field effect transistor is proportional to the thickness d and width of the channel region 8 that operates as a variable resistor, that is, the cross-sectional area in the source and drain directions, and the length L in the source and drain directions. is inversely proportional to. Further, it changes in proportion to the impurity concentration of the channel region 8 and the semiconductor layer 2 (the n-type impurity concentration N _D in the case of the n-channel junction field effect transistor shown in FIG. 1). Therefore, in order to increase the drain saturation current of a junction field effect transistor, it is necessary to increase the channel region 8.
It is also necessary to increase the impurity concentration N _D of the semiconductor layer 2, increase the thickness d, and lower the on-resistance Ron. On the other hand, the pinch-off voltage V _p required to cut off the drain current changes in proportion to the product of the impurity concentration N _D of the channel region 8 and the thickness d, so if d is set large, V _p It increases rapidly. Therefore, in order to lower the on-resistance Ron of the junction field effect transistor, it is desirable and common to select a high impurity concentration N _D in the channel region 8 and the semiconductor layer 2.

Now, the usable voltage range of such a junction field effect transistor, that is, the drain-source breakdown voltage BVN _DSX , is usually limited by the reverse breakdown voltage BV _DGO of the drain-gate PN junction.
Therefore, in order to obtain a junction field effect transistor with a higher operating voltage, it is necessary to increase the drain-gate indirect breakdown voltage, and it becomes necessary to select a lower impurity concentration N _D in the channel region 8 and the semiconductor layer 2. . That is, in a junction field effect transistor, lowering the on-resistance to increase the drain saturation current and increasing the drain-source breakdown voltage to widen the operable voltage range are contradictory factors.

For example, in the transistor of FIG.
Assuming a channel region of _D = 5×10 ¹⁵ cm ^-3 and thickness d = 2 μm, the pinch-off voltage is approximately 15 V.
become. At this time, the current density per unit area of the channel region is approximately 1×10 ¹² cm ⁻² . Now, in order to increase the drain-gate breakdown voltage BV _DGO , N
If we reduce _D by a tenth to 5×10 ¹⁴ cm ^-3 and try to maintain the same on-resistance, the thickness of the channel region d
must be set to 20 μm. At this time,
The pinch-off voltage V _p is calculated to be 150V. However, since it is desirable that the gate applied voltage necessary to control the channel resistance of the transistor be low, if the pinch-off voltage is maintained at approximately 15 V, d must be suppressed to approximately 6.2 μm. In this case, the channel resistance per unit channel width will increase by more than three times. Needless to say, if N _D is selected to be even lower in order to further enhance the drain-gate durability, the conditions for the pinch-off voltage and on-resistance will become even more severe.

Furthermore, if the impurity concentration of the semiconductor layer 2 is lowered, a large depletion layer region will expand between the drain and gate when a high drain voltage is applied, so the distance between the drain and gate electrodes must be set sufficiently wide. The result is that the resistance is increased.

An object of the present invention is to alleviate the relationship between on-resistance and drain-gate breakdown voltage, which has been an obstacle to increasing the breakdown voltage of conventional junction field effect transistors, by using a new device structure. An object of the present invention is to provide a junction field effect transistor that has high breakdown voltage and low on-resistance.

According to the present invention, a semiconductor layer provided on an insulating substrate includes a source region and a drain region of the same first conductivity type as the semiconductor layer, and a surface of the semiconductor layer between the source region and the drain region. An extension consisting of a gate region of a second conductivity type different from the semiconductor layer, and a low impurity concentration region of the same second conductivity type as the gate region, which is in contact with the gate region between the gate region and the drain region. The gate region is configured such that, at the time of gate pinch-off, the entire semiconductor layer portion consisting of the extended gate region and the channel region under the extended gate region becomes a depletion layer in a direction perpendicular to the channel direction. A junction field effect transistor is obtained, characterized in that the impurity concentration and its distribution in the extension gate region and the channel region under the extension region are selected.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention will be described in detail with reference to the drawings, in which a junction field effect transistor is used as an insulating substrate in an SOS (silicon on sapphire) substrate, which is a dielectric isolation isolation substrate.

FIG. 2 is a schematic diagram for explaining one embodiment of the present invention. First, as a semiconductor layer, the film thickness is approximately 3 μm.
An n-type silicon epitaxial film 2 having an impurity concentration of 5 to 7×10 ¹⁵ cm ^-3 was formed on a sapphire substrate 1, and the unnecessary silicon epitaxial film portion was removed by etching, leaving the element component portion.

Next, using the silicon oxide film as a master, boron,
Then, phosphorus was diffused to form n ⁺ high concentration diffusion regions 3 and 4 for source and drain electrodes and p ⁺ high concentration diffusion region 5 for gate electrode. These steps can be performed in exactly the same way as the MOSIC manufacturing process using an SOS substrate. Then about
A high concentration gate electrode region 5 is formed as a photoresistor through a thermally oxidized silicon oxide film of 1400 Å.
Bocon ions were implanted into the surface of the silicon epitaxial layer between the drain region 4 and in contact with the high concentration gate electrode region 5 at an acceleration voltage of 50 Kev to form a low concentration extended gate electrode region 10 having a length of 30 μm. Furthermore, in order to protect the surface, the main surface of the wafer is covered with a silicon dioxide film containing phosphorus using a vapor phase growth method, which also serves to activate the implanted ions.
Annealing treatment was performed at 950°C in a nitrogen atmosphere. Finally, contact holes are provided in the source, drain, and gate electrode diffusion regions 3, 4, and 5, respectively.
A1 wiring 7 was applied.

Boro ion implantation dose is 0, 1.5, 2.0,
Drain-gate junction breakdown voltage for transistor samples with various changes of 2.5, 3.0, and 3.5×10 ¹² cm ^-2
When we looked at the BV _DGO , we found that the BV _DGO of a transistor without ion implantation is about 70V, while it is 2.5V.
A BV _DGO of more than 600V was obtained in a transistor implanted with ×10 ¹² cm ^-2 boro ions. Furthermore, when BV _GDO was investigated for various transistors with different lengths L _G of the low concentration extended gate region 10, it was found that
The results show that BV _DGO increases in proportion to L _G and is highest when an ion implantation dose of 2.5×10 ¹² cm ⁻² is applied for a constant L _G .

That is, in the junction field effect transistor according to the present invention, although the impurity concentration in the channel region 8 is high, the length L _G of the low concentration extended gate region 10 is set longer, and ions are implanted into the same region. By appropriately selecting the dose,
Since the drain-gate breakdown voltage can be significantly increased, a transistor with high drain breakdown voltage and low on-resistance can be realized.

The high drain-gate junction breakdown voltage of the junction field effect transistor according to the present invention is based on the operation disclosed in Japanese Patent Application No. 81314/1983, which was filed by the present applicant and others and relates to increasing the breakdown voltage of a PN junction diode element on a dielectric isolation substrate. It can be explained in the same way as the principle. That is, the total amount of effective impurity ions contained in the corresponding portion of the low concentration extended gate region 10 should be controlled to be equal to the total amount of effective impurity ions contained in a unit area of the channel region 8 below the low concentration extended gate region 10. For example, between the drain 4, the gate electrode 5, and the low concentration extended gate region 10,
When a reverse voltage is applied to the PN junction and a depletion layer spreads between the junctions, the low concentration extended gate region 10
Electric lines of force emitted from impurity ions therein can be terminated by almost all impurity ions of opposite polarity in the channel region 8 below the same region. That is, the low concentration extended gate region 10 and the channel region 8 below the same region have a depletion layer extending between the regions in the direction perpendicular to the channel direction, so that at the gate pinch-off voltage V _p , the low concentration extended gate region 10 , to the silicon-silicon dioxide interface, and the channel region 8 below the same region is simultaneously reached through to the silicon-insulator substrate interface. Therefore, in the range of the drain-gate voltage exceeding _Vp , there is a low concentration extended gate region between the drain electrode 4 and the gate electrode 5 or the source electrode 3.
There is a region where the entire region becomes a depletion layer in the film thickness direction, which is approximately proportional to the length L _G of 10, and the drain -
The gate-to-gate breakdown voltage or the drain-source breakdown voltage increases in accordance with L _G . Here, the thickness, impurity concentration and distribution of the channel region 8 and the low concentration extended gate region 10 should be set in consideration of the junction breakdown voltage in the film thickness direction so that the channel is pinched off at the appropriate gate voltage. Of course.

In fact, in the junction field effect transistor of the example, the impurity concentration of the semiconductor thin film 2 is approximately 5×10 ¹⁵
cm ^-3 , the film has a thickness of 3 μm.
Therefore, approximately 1.5×10 ¹² cm ^-2 of impurity ions exist per unit area. On the other hand, the amount of active impurity ions introduced into the low concentration extended gate region 10 by ion implantation is reduced to 6 of the ion implantation dose.
If estimated to be ~70%, the effective impurity ion implantation amount in this example is 1.5×1.75×10 ¹² cm ⁻² for the ion implantation dose of 2.5×10 ¹² cm ⁻² . That is, under the optimal ion implantation conditions in this example, the 1×2×10 ¹¹ cm contained in the surface oxide film
Considering the surface level of about ^-2 , the total amount of impurity ions of opposite polarity contained in each of the low concentration extended gate region 10 and the channel region 8 below the low concentration extended gate region 10 is approximately equal. Ori,
It is considered that the conditions for increasing the withstand voltage between the drain and gate have been met.

As described above, according to the present invention, the drain-gate breakdown voltage is not restricted by the impurity concentration of the direct channel region 8 or the semiconductor region 2, as shown in the embodiments, but rather by the impurity concentration of the low concentration extended gate region 10.
_Therefore , by selecting a higher impurity concentration in the channel region 8 or the semiconductor thin film 2 within the above range, it is possible to obtain a high drain breakdown voltage, a low channel resistance, and a gate pinch-off voltage. It is possible to realize a junction field effect transistor with low

In the junction field effect transistor according to the present invention, the gate length increases by the length of the lightly doped extended gate region 10, which is unfavorable for high frequency characteristics. However, in order to obtain a high drain breakdown voltage,
A sufficient distance is required between the drain and the gate to allow the depletion layer to expand, and the fact that the channel region 8 has a higher impurity concentration and low resistivity makes it possible for junction field effect transistors with the same drain breakdown voltage to The comparison is much more favorable.

By the way, in the present invention, when the voltage between the drain and the gate increases, the breakdown voltage between the drain and the gate or between the drain and the source is increased by creating a region where the entire area is depleted in the film thickness direction between the drain and the gate. The purpose is to provide a low concentration extended gate region in contact with the gate electrode 5 in which the effective amount of impurity ions is controlled, and in order to realize the structure of the present invention, manufacturing steps other than those shown in this embodiment are required. It goes without saying that various modifications of the manufacturing process are possible. From the same point of view, the gate electrode high concentration diffusion region 5 only needs to have a necessary and sufficient size and depth in order to make electrical contact with the outside.

Although this embodiment has been described with respect to an n-channel junction field effect transistor, it is clear from the above description that the present invention can be implemented in the same manner with a p-channel junction field effect transistor.

Furthermore, although a silicon-on-sapphire substrate was used as the insulating substrate in this example, the substrate material in the present invention need not necessarily be a silicon-on-sapphire substrate; for example, silicon oxide on a polysilicon thick film is used. It may also be a dielectric insulating isolation substrate such as a silicon single crystal thin film formed through a film. Further, the insulating substrate may be a semi-insulating high-ratio/low-resistance semiconductor substrate as long as the gist of the present invention is utilized, and in particular, a second conductive substrate different from the semiconductor layer on the insulating substrate may be used. It is advantageous to use a high resistivity semiconductor substrate having a shape. Furthermore, it goes without saying that the present invention can be practiced using materials other than silicon as the semiconductor layer.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional schematic diagram of a conventional junction field effect transistor provided on a dielectric insulating substrate.
FIG. 2 is a cross-sectional structural diagram showing an embodiment of a high voltage junction field effect transistor provided on a dielectric insulating isolation substrate according to the present invention. In the figure, 1 is a dielectric insulating substrate, 2 is a semiconductor thin film, and 3 and 4 are for source and drain electrodes.
N ⁺ diffusion region, 5 is for gate electrode, P ⁺ diffusion region,
6 is silicon dioxide film, 7 is Al electrode wiring, 8 is
9 indicates a channel region, 9 indicates an end of a depletion layer extending around the gate electrode, and 10 indicates a low concentration extended gate region.

Claims (1)

[Claims] 1 A semiconductor layer provided on an insulating substrate has a source region and a drain region of the same first conductivity type as the semiconductor layer, and a region different from the semiconductor layer on the surface of the semiconductor layer between the source region and the drain region. Second
An extended gate region is formed between the gate region and the drain region, and in contact with the gate region, the extended gate region is composed of a low impurity concentration region of the same second conductivity type as the gate region. ,and,
The extended gate region and the area under the extended gate region are formed such that the entire semiconductor layer portion consisting of the extended gate region and the channel region under the extended gate region becomes a depletion layer in the direction perpendicular to the channel direction during gate pinch-off. A junction field effect transistor characterized in that the impurity concentration and its distribution in the channel region are selected.