JP2008091699A - Method of manufacturing semiconductor transistor - Google Patents

Method of manufacturing semiconductor transistor Download PDF

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JP2008091699A
JP2008091699A JP2006271988A JP2006271988A JP2008091699A JP 2008091699 A JP2008091699 A JP 2008091699A JP 2006271988 A JP2006271988 A JP 2006271988A JP 2006271988 A JP2006271988 A JP 2006271988A JP 2008091699 A JP2008091699 A JP 2008091699A
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nitride semiconductor
group iii
protective film
semiconductor layer
forming
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JP5520432B2 (en
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Takehiko Nomura
剛彦 野村
Shigeaki Ikeda
成明 池田
Yuuki Niiyama
勇樹 新山
Ko Ri
江 李
Kiyoteru Yoshida
清輝 吉田
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Furukawa Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce a current collapse phenomenon of a semiconductor transistor having a group III-V nitride semiconductor as a channel region. <P>SOLUTION: The method of manufacturing the semiconductor transistor comprises the stages of: forming group III-V nitride semiconductor layers 3 and 4 on a substrate 1; forming a protective film 5 on the group III-V nitride semiconductor layers 3 and 4; annealing the protective film 5 and group III-V nitride semiconductor layers 3 and 4 at temperature of ≥900°C; forming first and second openings 7s and 7d at least in source regions and drain regions of the group III-V nitride semiconductor layers 3 and 4 in the protective film 5; forming a source electrode 9s which comes into ohmic contact with the group III-V nitride semiconductor layers 3 and 4 in the first opening 7s; forming a drain electrode 9d which comes into ohmic contact with the group III-V nitride semiconductors 3 and 4 in the second opening 7d; and forming a gate electrode 11 which comes into Schottky contact with the group III-V nitride semiconductor layers 3 and 4 between the source electrode 9s and drain electrode 9d. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体トランジスタの製造方法に関し、より詳しくは、III−Ｖ族窒化物半導体をチャネル領域とする半導体トランジスタの製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor transistor, and more particularly to a method for manufacturing a semiconductor transistor having a group III-V nitride semiconductor as a channel region.

III−Ｖ族窒化物に代表されるワイドバンドギャップ半導体は、高い絶縁破壊耐圧、良好な電子輸送特性、良好な熱伝導度を持ち、高温で大きなパワー用のデバイスとして非常に有用である。   Wide band gap semiconductors typified by III-V nitrides have high breakdown voltage, good electron transport properties, and good thermal conductivity, and are very useful as devices for large power at high temperatures.

種々のIII−Ｖ族窒化物の中で、例えばＡｌＧａＮ／ＧａＮヘテロ接合構造はピエゾ効果によって高い電子移動度とキャリア密度を持つ２次元電子ガスを有している。   Among various III-V nitrides, for example, an AlGaN / GaN heterojunction structure has a two-dimensional electron gas having high electron mobility and carrier density due to the piezoelectric effect.

ＡｌＧａＮ／ＧａＮを用いたヘテロ接合電界効果トランジスタ（ＨＦＥＴ）はシリコン結晶を用いた種々のＦＥＴよりも良好な特性を持ち、また、そのＨＦＥＴのオン抵抗は、シリコン結晶やＧａＡｓ結晶を用いたトランジスタよりも低くなることが期待できる。   Heterojunction field effect transistors (HFETs) using AlGaN / GaN have better characteristics than various FETs using silicon crystals, and the on-resistance of the HFETs is higher than that of transistors using silicon crystals or GaAs crystals. Can be expected to be lower.

このように、ＨＦＥＴは、低いオン抵抗、速いスイッチング特性を持ち、高温動作が可能であり、パワースイッチングの応用に非常に好適であり、システムの冷却系の簡略化が可能になる。   Thus, the HFET has low on-resistance and fast switching characteristics, can operate at high temperature, is very suitable for power switching applications, and can simplify the cooling system of the system.

次に、従来のＨＦＥＴの製造方法を、図７に基づいて簡単に説明する。   Next, a conventional HFET manufacturing method will be briefly described with reference to FIG.

まず、図７（ａ）に示すように、サファイア基板１０１上にＡｌＮよりなるバッファ層１０２、アンドープＧａＮよりなる電子走行層１０３、アンドープＡｌＧａＮよりなる電子供給層１０４を順にエピタキシャル成長した後に、ＳｉＯ2よりなる保護膜１０５をＣＶＤ法により成長する。 First, as shown in FIG. 7A, a buffer layer 102 made of AlN, an electron transit layer 103 made of undoped GaN, and an electron supply layer 104 made of undoped AlGaN are epitaxially grown in this order on a sapphire substrate 101, and then SiO 2 . A protective film 105 to be formed is grown by the CVD method.

次に、図７（ｂ）に示すように、フォトレジストとエッチングを用いたリソグラフィにより、保護膜１０５のうちソース領域とドレイン領域のそれぞれに第１、第２の開口部１０５ｓ、１０５ｄを形成する。   Next, as shown in FIG. 7B, first and second openings 105s and 105d are formed in the source region and the drain region of the protective film 105 by lithography using a photoresist and etching, respectively. .

さらに、図７（ｃ）に示すように、第１、第２の開口部１０５ｓ、１０５ｄを通して電子供給層１０４にオーミック接触するソース電極１０６ｓとドレイン電極１０６ｄをリフトオフ法により形成する。   Further, as shown in FIG. 7C, a source electrode 106s and a drain electrode 106d that are in ohmic contact with the electron supply layer 104 through the first and second openings 105s and 105d are formed by a lift-off method.

続いて、図７（ｄ）に示すように、フォトレジストとエッチングを用いたリソグラフィにより、ソース電極１０６ｓとドレイン電極１０６ｄの間に配置されるゲート領域に第３の開口部１０５ｇを形成する。   Subsequently, as shown in FIG. 7D, a third opening 105g is formed in the gate region disposed between the source electrode 106s and the drain electrode 106d by lithography using a photoresist and etching.

さらに、図７（ｅ）に示すように、第３の開口部１０５ｇを通して電子供給層１０４にショットキー接触するゲート電極１０７を形成する。以上のような工程は、例えば下記の特許文献１に記載されている。   Further, as shown in FIG. 7E, a gate electrode 107 that is in Schottky contact with the electron supply layer 104 through the third opening 105g is formed. The above process is described in, for example, Patent Document 1 below.

これにより、ＨＦＥＴのユニットが形成され、大電流動作用のマルチフィンガーＦＥＴを作成する場合には、必要に応じて多層配線が形成されてＨＦＥＴのユニット同士が連結される。
特開２００３−５９９４６号公報 Thereby, an HFET unit is formed, and when a multi-finger FET for large current operation is created, a multilayer wiring is formed as necessary to connect the HFET units to each other.
JP 2003-59946 A

ところで、ＡｌＧａＮとＧａＮヘテロ接合構造を有するＨＦＥＴにおいて、ソース・ドレイン間に印可する電圧を高くするとオン抵抗が増大する電流コラプス現象が知られている。この現象は、高電圧印可時のＨＦＥＴにおける発熱の発生や消費電力の増大、素子寿命の短命化などを引き起こす要因の１つとなっている。   By the way, in the HFET having an AlGaN and GaN heterojunction structure, a current collapse phenomenon is known in which the on-resistance increases when the voltage applied between the source and the drain is increased. This phenomenon is one of the factors that cause generation of heat in the HFET when a high voltage is applied, an increase in power consumption, and a shortened device life.

電流コラプスの原因としては、ＨＦＥＴのＡｌＧａＮ層と保護膜の間の界面準位や、ＨＦＥＴのＧａＮ層内の深い準位が影響していると考えられている。   The cause of current collapse is considered to be influenced by the interface level between the AlGaN layer of the HFET and the protective film and the deep level in the GaN layer of the HFET.

本発明の目的は、電流コラプス現象の低減を図ることができる半導体トランジスタの製造方法を提供することにある。   An object of the present invention is to provide a method for manufacturing a semiconductor transistor capable of reducing the current collapse phenomenon.

上記の課題を解決するための本発明の第１の態様は、基板の上にIII−Ｖ族窒化物半導体層を形成する工程と、前記III−Ｖ族窒化物半導体層の上に保護膜を形成する工程と、前記保護膜及び前記III−Ｖ族窒化物半導体層を９００℃以上の温度でアニールする工程と、前記保護膜のうち前記III−Ｖ族窒化物半導体層の少なくともソース領域とドレイン領域に第１、第２の開口を形成する工程と、前記III−Ｖ族窒化物半導体層にオーミック接触するソース電極を前記第１の開口内に形成し、前記III−Ｖ族窒化物半導体層にオーミック接触するドレイン電極を前記第２の開口内に形成する工程と、前記ソース電極と前記ドレイン電極の間の領域で前記III−Ｖ族窒化物半導体層にショットキー接触するゲート電極を形成する工程とを有することを特徴とする半導体トランジスタの製造方法である。   A first aspect of the present invention for solving the above-described problems includes a step of forming a group III-V nitride semiconductor layer on a substrate, and a protective film on the group III-V nitride semiconductor layer. A step of forming, a step of annealing the protective film and the group III-V nitride semiconductor layer at a temperature of 900 ° C. or higher, and at least a source region and a drain of the group III-V nitride semiconductor layer of the protective film. Forming a first and second opening in the region; forming a source electrode in ohmic contact with the group III-V nitride semiconductor layer in the first opening; and group III-V nitride semiconductor layer Forming a drain electrode in ohmic contact with the second opening, and forming a gate electrode in Schottky contact with the III-V nitride semiconductor layer in a region between the source electrode and the drain electrode. And having a process That is a method of manufacturing a semiconductor transistor.

本発明の第２の態様は、前記第１の態様に係る半導体トランジスタの製造方法において、前記保護膜及び前記III−Ｖ族窒化物半導体層をアニールする工程において、前記保護膜は窒素雰囲気、窒素含有雰囲気のいずれかの中に配置されることを特徴とする。   According to a second aspect of the present invention, in the method of manufacturing a semiconductor transistor according to the first aspect, in the step of annealing the protective film and the group III-V nitride semiconductor layer, the protective film has a nitrogen atmosphere, nitrogen It is arranged in any of the contained atmospheres.

本発明の第３の態様は、前記第１又は第２の態様に係る半導体トランジスタの製造方法において、前記保護膜及び前記III−Ｖ族窒化物半導体層をアニールする温度は、９００℃〜１０００℃の範囲にあることを特徴とする。   According to a third aspect of the present invention, in the method of manufacturing a semiconductor transistor according to the first or second aspect, the temperature for annealing the protective film and the group III-V nitride semiconductor layer is 900 ° C. to 1000 ° C. It is characterized by being in the range of

本発明の第４の態様は、前記第１乃至第３の態様のいずれかに係る半導体トランジスタの製造方法において、前記保護膜は、二酸化シリコン、窒化シリコン、酸化マグネシウム、アルミナのいずれかの絶縁膜であることを特徴とする。   According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor transistor according to any one of the first to third aspects, the protective film is an insulating film of any one of silicon dioxide, silicon nitride, magnesium oxide, and alumina. It is characterized by being.

本発明の第５の態様は、前記第１乃至第４の態様のいずれかに係る半導体トランジスタの製造方法において、前記III−Ｖ族窒化物半導体層は、互いにヘテロ接合される第１のIII−Ｖ族窒化物半導体層と第２のIII−Ｖ族窒化物半導体層を有し、前記第１のIII−Ｖ族窒化物半導体層と前記第２のIII−Ｖ族窒化物半導体層の界面には二次元電子ガスが生成されることを特徴とする。   According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor transistor according to any one of the first to fourth aspects, the III-V nitride semiconductor layers are heterojunctioned with each other. A group V nitride semiconductor layer and a second group III-V nitride semiconductor layer are provided at the interface between the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer. Is characterized in that a two-dimensional electron gas is produced.

本発明によれば、III−Ｖ族窒化物半導体層の表面を保護膜で覆った状態で９００℃以上の温度でアニールしている。
これによれば、III−Ｖ族窒化物半導体層の表面の界面準位等を低減することができ、電流コラプスが抑制された半導体トランジスタを得ることが可能になる。 According to the present invention, annealing is performed at a temperature of 900 ° C. or higher with the surface of the III-V nitride semiconductor layer covered with the protective film.
According to this, it is possible to reduce the interface state on the surface of the III-V nitride semiconductor layer, and to obtain a semiconductor transistor in which current collapse is suppressed.

以下に本発明の実施の形態を図面に基づいて詳細に説明する。
図１〜図３は、本発明の実施形態に係る半導体トランジスタの製造工程を示す断面図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1 to 3 are cross-sectional views illustrating manufacturing steps of a semiconductor transistor according to an embodiment of the present invention.

まず、図１（ａ）に示すように、有機金属気相成長（ＭＯＣＶＤ）法によりサファイア基板１上に、ＡｌＮ又はＧａＮよりなる厚さ２０ｎｍ程度のバッファ層２と、厚さ１μｍ程度のＧａＮよりなる電子走行層３と、厚さ２０ｎｍ程度のＡｌＧａＮよりなる電子供給層４とを順に形成する。電子走行層３と電子供給層４はヘテロ接合であり、その界面には二次元電子ガス３Ｅが生成される。   First, as shown in FIG. 1A, a buffer layer 2 made of AlN or GaN having a thickness of about 20 nm and a GaN having a thickness of about 1 μm are formed on a sapphire substrate 1 by metal organic chemical vapor deposition (MOCVD). An electron transit layer 3 and an electron supply layer 4 made of AlGaN having a thickness of about 20 nm are sequentially formed. The electron transit layer 3 and the electron supply layer 4 are heterojunction, and a two-dimensional electron gas 3E is generated at the interface.

なお、基板として、サファイア基板に限られるものではなく、ＳｉＣ、Ｓｉ、ＧａＮ等の他の基板を用いてもよい。また、基板上に成長されるＧａＮ等は、ＭＯＣＶＤ法に限られるものではなく、ハイドライド気相成長（ＨＶＰＥ）法、分子線エピタキシー（ＭＢＥ）法等の他の成長法を用いてもよい。   The substrate is not limited to the sapphire substrate, and other substrates such as SiC, Si, and GaN may be used. Further, GaN or the like grown on the substrate is not limited to the MOCVD method, and other growth methods such as a hydride vapor phase epitaxy (HVPE) method and a molecular beam epitaxy (MBE) method may be used.

次に、図１（ｂ）に示すように、電子供給層４上にフォトレジスト５を塗布し、これを露光、現像することにより、トランジスタ活性領域Ａを覆い且つその周囲を露出させるパターンを形成する。   Next, as shown in FIG. 1B, a photoresist 5 is applied on the electron supply layer 4, and this is exposed and developed to form a pattern that covers the transistor active region A and exposes its periphery. To do.

さらに、図１（ｃ）に示すように、パターニングされたフォトレジスト５をマスクにして、電子供給層４から電子走行層３の途中までエッチングして凹状の素子分離部６を形成する。エッチングとして反応性イオンエッチング（ＲＩＥ）、誘導結合方式（ＩＣＰ）エッチング等を用いる。   Further, as shown in FIG. 1C, using the patterned photoresist 5 as a mask, etching is performed from the electron supply layer 4 to the middle of the electron transit layer 3 to form a concave element isolation portion 6. As the etching, reactive ion etching (RIE), inductive coupling (ICP) etching, or the like is used.

この後に、図１（ｄ）に示すように、溶剤を用いてフォトレジスト５を除去し、電子供給層４の表面を露出させる。   Thereafter, as shown in FIG. 1D, the photoresist 5 is removed using a solvent to expose the surface of the electron supply layer 4.

さらに、図２（ａ）に示すように、二酸化シリコン（ＳｉＯ2）からなる保護膜７を電子供給層４及び電子走行層３の表面上にプラズマＣＶＤ法により形成する。その厚さは、０．５μｍ程度が好ましい。 Further, as shown in FIG. 2A, a protective film 7 made of silicon dioxide (SiO 2 ) is formed on the surfaces of the electron supply layer 4 and the electron transit layer 3 by plasma CVD. The thickness is preferably about 0.5 μm.

次に、図２（ｂ）に示すように、基板１を窒素雰囲気の加熱室（不図示）内に搬送して例えば９００℃で３０分間アニールを行う。
これにより、電子供給層４と保護膜７との界面の準位や半導体中の深い準位が低減するとともに、保護膜７の緻密化が図れる。
保護膜７の緻密化によりエッチングレートは遅くなるが、外部からのイオン等の汚染に対する耐性が向上するという利点があり、保護膜７としての保護機能が高められる。 Next, as shown in FIG. 2B, the substrate 1 is transferred into a heating chamber (not shown) in a nitrogen atmosphere and annealed at, for example, 900 ° C. for 30 minutes.
Thereby, the level of the interface between the electron supply layer 4 and the protective film 7 and the deep level in the semiconductor are reduced, and the protective film 7 can be densified.
Although the etching rate is slowed by densification of the protective film 7, there is an advantage that resistance to contamination such as external ions is improved, and the protective function as the protective film 7 is enhanced.

なお、加熱室内は窒素雰囲気の他、窒素と他のガス、例えばアルゴン（Ａｒ）等の他の不活性ガスを混合した窒素含有雰囲気であってもよい。
続いて、図２（ｃ）に示すように、フォトレジスト８を保護膜７上に塗布し、これを露光、現像してソース領域とドレイン領域にそれぞれ窓８ｓ、８ｄを形成する。さらに、フォトレジスト８をマスクにして保護膜７を例えばフッ酸溶液を用いてエッチングして、図２（ｄ）に示すように窓８ｓ、８ｄを通して開口部７ｓ、７ｄを形成する。 Note that the heating chamber may be a nitrogen-containing atmosphere in which nitrogen and another gas such as argon (Ar) are mixed in addition to the nitrogen atmosphere.
Subsequently, as shown in FIG. 2C, a photoresist 8 is applied on the protective film 7, and this is exposed and developed to form windows 8s and 8d in the source region and the drain region, respectively. Further, the protective film 7 is etched using, for example, a hydrofluoric acid solution using the photoresist 8 as a mask to form openings 7s and 7d through the windows 8s and 8d as shown in FIG.

次に、フォトレジスト８の開口部７ｓ、７ｄを通してスパッタ等によりアルミニウム（Ａｌ）とチタン（Ｔｉ）を順に積層し、その後にフォトレジスト８を溶剤により除去すると、図３（ａ）に示すように、Ｔｉ／Ａｌからなる金属膜は、ソース電極９ｄ及びドレイン電極９ｓとして適用され、開口７ｓ、７ｄを通して電子供給層４上に形成されてオーミック接触する。   Next, aluminum (Al) and titanium (Ti) are sequentially laminated by sputtering or the like through the openings 7s and 7d of the photoresist 8, and then the photoresist 8 is removed with a solvent, as shown in FIG. The metal film made of Ti / Al is applied as the source electrode 9d and the drain electrode 9s, and is formed on the electron supply layer 4 through the openings 7s and 7d to be in ohmic contact.

さらに、図３（ｂ）、（ｃ）に示すように、保護膜７、ソース電極９ｓ及びドレイン電極９ｄの上にフォトレジスト１０を塗布し、これを露光、現像してゲート領域に窓１０ｇを形成し、続いて、窓１０ｇを通して保護膜７をエッチングして開口部７ｇを形成する。   Further, as shown in FIGS. 3B and 3C, a photoresist 10 is applied on the protective film 7, the source electrode 9s and the drain electrode 9d, and this is exposed and developed to form a window 10g in the gate region. Then, the protective film 7 is etched through the window 10g to form an opening 7g.

開口部７ｇは、ドレイン電極９ｄとソース電極９ｓの間の領域に形成され、ドレイン電極９ｄから約１５〜２０μｍ程度の間隔で、且つソース電極９ｓから約３μｍの間隔で配置される。   The openings 7g are formed in a region between the drain electrode 9d and the source electrode 9s, and are arranged at an interval of about 15 to 20 μm from the drain electrode 9d and at an interval of about 3 μm from the source electrode 9s.

さらに、スパッタ等によって、開口部７ｇと窓１０ｇを通して金（Ａｕ）、ニッケル（Ｎｉ）を電子供給層４上に順に積層する。そして、フォトレジスト１０を除去することにより、図３（ｄ）に示すように、開口部７ｇを通して電子供給層４にショットキー接触するＮｉ／Ａｕからなるゲート電極１１が形成される。   Further, gold (Au) and nickel (Ni) are sequentially stacked on the electron supply layer 4 through the opening 7g and the window 10g by sputtering or the like. Then, by removing the photoresist 10, as shown in FIG. 3D, a gate electrode 11 made of Ni / Au that is in Schottky contact with the electron supply layer 4 through the opening 7g is formed.

以上のような工程により、電界効果トランジスタとしてＨＦＥＴが形成される。
ノーマリオンのＨＦＥＴの製造工程において、電子供給層４を保護膜７により覆った後に、図２（ｂ）に示すようにアニールを行った場合と従来技術のように行わなかった場合について、オン抵抗を測定したところ図４に示すような結果が得られた。 Through the above process, an HFET is formed as a field effect transistor.
In the normally-on HFET manufacturing process, after the electron supply layer 4 is covered with the protective film 7, the annealing is performed as shown in FIG. 2B, and the case where the annealing is not performed as in the prior art. As a result, the results as shown in FIG. 4 were obtained.

オン抵抗の測定は、ゲート電極１１に電圧を印可しない状態で、ソース電極９ｓとドレイン電極９ｄの間の電圧を変化させ、ソース電極９ｓとドレイン電極９ｄの間の電流１０Ａ当たりのオン抵抗を測定して求めた。   The on-resistance is measured by changing the voltage between the source electrode 9s and the drain electrode 9d in a state where no voltage is applied to the gate electrode 11, and measuring the on-resistance per current 10A between the source electrode 9s and the drain electrode 9d. And asked.

図４によれば、保護膜７の形成後にアニールしなかった場合には、ソース・ドレイン間電圧Ｖdsが２５０Ｖ以上になるとオン抵抗Ｒｏｎの上昇率が高くなるのに対し、保護膜７の形成後にアニールを行った場合には、ソース・ドレイン間電圧Ｖdsが２５０Ｖ以上になってもオン抵抗の上昇率は殆ど変化せずに低い状態のままとなっていた。   According to FIG. 4, when annealing is not performed after the formation of the protective film 7, the rate of increase of the on-resistance Ron increases when the source-drain voltage Vds becomes 250 V or higher, whereas after the formation of the protective film 7. When annealing was performed, even when the source-drain voltage Vds was 250 V or higher, the increase rate of the on-resistance remained almost unchanged and remained low.

このように、本実施形態のように電子供給層４の上に保護膜７を形成した後に窒素雰囲気でアニールを施すと電流コラプスの効果が低減するのは、そのアニールによって保護膜７と電子供給層４の間の界面準位が低減したり、ＧａＮのバンドギャップ間の準位密度が低減したりすることに起因すると考えられる。   Thus, when annealing is performed in a nitrogen atmosphere after the protective film 7 is formed on the electron supply layer 4 as in this embodiment, the effect of current collapse is reduced by the annealing. It is considered that the interface state between the layers 4 is reduced or the state density between the band gaps of GaN is reduced.

しかも、保護膜７はそのアニールによって膜質が緻密になるので、外部からのイオン等による耐性が向上する効果がある。   In addition, since the film quality of the protective film 7 becomes dense by the annealing, there is an effect of improving the resistance due to external ions and the like.

次に、保護膜７の形成後のアニールの効果を検証するために、アニール温度をパラメータにして実験を行った。   Next, in order to verify the effect of annealing after the formation of the protective film 7, an experiment was performed using the annealing temperature as a parameter.

例えば、図５に示すように、ｎ型不純物を含むシリコン（Ｓｉ）基板１１上にｎ型ＧａＮ層１２を成長しその上に二酸化シリコンの保護膜１３を形成し、さらに保護膜１３上に第１電極１４を形成し、シリコン基板１１の下に第２の電極１５を形成して、保護膜１３の形成後に行うアニール温度を８００℃、９００℃、１０００℃と変えた試料をそれぞれ複数用意してＣＶ測定を行って不純物準位を求めたところ、図６に示すような結果が得られた。   For example, as shown in FIG. 5, an n-type GaN layer 12 is grown on a silicon (Si) substrate 11 containing an n-type impurity, a silicon dioxide protective film 13 is formed on the n-type GaN layer 12, and a protective film 13 is formed on the protective film 13. 1 electrode 14 is formed, second electrode 15 is formed under silicon substrate 11, and a plurality of samples are prepared in which the annealing temperatures performed after formation of protective film 13 are changed to 800 ° C., 900 ° C., and 1000 ° C., respectively. Then, the CV measurement was performed to obtain the impurity level, and the result shown in FIG. 6 was obtained.

それらの試料のアニールは、全て窒素雰囲気で３０分間行われている。   All of these samples are annealed in a nitrogen atmosphere for 30 minutes.

図６によれば、ＧａＮの伝導帯Ｅcを基準にして示される不純物準位Ｅc−Ｅの密度Ｄitをアニールにより小さくすることが可能であることがわかる。特に、不純物準位Ｅc−Ｅのうち０．６ｅＶ以下の浅い準位については、アニール温度を特に９００℃〜１０００℃の範囲に設定することにより、その密度Ｄitを確実に小さくすることができる。   According to FIG. 6, it can be seen that the density Dit of the impurity level Ec-E shown with reference to the conduction band Ec of GaN can be reduced by annealing. In particular, regarding the shallow level of 0.6 eV or less among the impurity levels Ec-E, the density Dit can be reliably reduced by setting the annealing temperature in the range of 900 ° C. to 1000 ° C. in particular.

図６と図４によれば、保護膜７の形成後の窒素雰囲気中でのアニールにより、界面準位、不純物準位の密度を低減して電流コラプス効果の低減を図ることが可能になることがわかる。   According to FIG. 6 and FIG. 4, it is possible to reduce the current collapse effect by reducing the density of interface states and impurity levels by annealing in a nitrogen atmosphere after the formation of the protective film 7. I understand.

なお、上記した実施形態においては、電子供給層４、電子走行層５を覆う保護膜７として二酸化シリコン膜を形成したが、窒化シリコン（ＳｉＮx、酸化マグネシウム（ＭｇＯ）、アルミナ（Ａｌ2Ｏ3）のいずれかの絶縁膜を形成してもよい。 In the embodiment described above, a silicon dioxide film is formed as the protective film 7 covering the electron supply layer 4 and the electron transit layer 5, but silicon nitride (SiN x , magnesium oxide (MgO), alumina (Al 2 O 3). )) May be formed.

また、上記した実施形態では、ＡｌＧａＮ／ＧａＮヘテロ接合構造を基板上に形成したが、その他のIII−Ｖ族窒化物半導体層を基板上に形成してもよい。また、電界効果トランジスタとしては、ＨＦＥＴに限るものではなく、ショットキーゲートを有するＭＥＳＦＥＴ(Metal Semiconductor Field Effect Transistor)、その他のIII−Ｖ族窒化物半導体トランジスタであってもよい。   In the above-described embodiment, the AlGaN / GaN heterojunction structure is formed on the substrate. However, other group III-V nitride semiconductor layers may be formed on the substrate. Further, the field effect transistor is not limited to the HFET, but may be a MESFET (Metal Semiconductor Field Effect Transistor) having a Schottky gate or other group III-V nitride semiconductor transistor.

それらのトランジスタは、同一基板上に複数個形成された大電流動作用のマルチフィンガーＦＥＴを構成するものであってもよく、必要に応じて多層配線が形成されてユニットＦＥＴが連結される。   These transistors may constitute a multi-finger FET for large current operation formed on the same substrate, and multilayer FETs are formed as necessary to connect unit FETs.

図１は、本発明の実施形態に係る半導体トランジスタの形成工程を示す断面図（その１）である。FIG. 1 is a cross-sectional view (No. 1) showing a process for forming a semiconductor transistor according to an embodiment of the present invention. 図２は、本発明の実施形態に係る半導体トランジスタの形成工程を示す断面図（その２）である。FIG. 2 is a cross-sectional view (No. 2) showing a step of forming a semiconductor transistor according to the embodiment of the present invention. 図３は、本発明の実施形態に係る半導体トランジスタの形成工程を示す断面図（その３）である。FIG. 3 is a cross-sectional view (No. 3) showing the formation process of the semiconductor transistor according to the embodiment of the present invention. 図４は、本発明の実施形態に係る半導体トランジスタのノーマリオン型についてのオン抵抗を示す特性図である。FIG. 4 is a characteristic diagram showing the on-resistance of the normally-on type semiconductor transistor according to the embodiment of the present invention. 図５は、本発明の実施形態に係る半導体トランジスタの界面準位を測定するための試料の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of a sample for measuring the interface state of the semiconductor transistor according to the embodiment of the present invention. 図６は、本発明の実施形態に係る半導体トランジスタを構成するＧａＮのエネルギーギャップの伝導帯近傍での界面準位密度分布を示す図である。FIG. 6 is a diagram showing an interface state density distribution in the vicinity of the conduction band of the energy gap of GaN constituting the semiconductor transistor according to the embodiment of the present invention. 図７は、従来の半導体トランジスタの製造工程を示す断面図である。FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional semiconductor transistor.

符号の説明Explanation of symbols

１：基板
２：バッファ層
３：電子走行層
４：電子供給層
５、８、１０：フォトレジスト
６：素子分離部
７：保護膜
９ｓ：ソース電極
９ｄ：ドレイン電極
１１：ゲート電極 1: Substrate 2: Buffer layer 3: Electron travel layer 4: Electron supply layers 5, 8, 10: Photoresist 6: Element isolation part 7: Protective film 9s: Source electrode 9d: Drain electrode 11: Gate electrode

Claims (5)

基板の上にIII−Ｖ族窒化物半導体層を形成する工程と、
前記III−Ｖ族窒化物半導体層の上に保護膜を形成する工程と、
前記保護膜及び前記III−Ｖ族窒化物半導体層を９００℃以上の温度でアニールする工程と、
前記保護膜のうち前記III−Ｖ族窒化物半導体層の少なくともソース領域とドレイン領域に第１、第２の開口を形成する工程と、
前記III−Ｖ族窒化物半導体層にオーミック接触するソース電極を前記第１の開口内に形成し、前記III−Ｖ族窒化物半導体層にオーミック接触するドレイン電極を前記第２の開口内に形成する工程と、
前記ソース電極と前記ドレイン電極の間の領域で前記III−Ｖ族窒化物半導体層にショットキー接触するゲート電極を形成する工程と
を有することを特徴とする半導体トランジスタの製造方法。 Forming a group III-V nitride semiconductor layer on the substrate;
Forming a protective film on the III-V nitride semiconductor layer;
Annealing the protective film and the III-V nitride semiconductor layer at a temperature of 900 ° C. or higher;
Forming first and second openings in at least a source region and a drain region of the III-V nitride semiconductor layer of the protective film;
A source electrode in ohmic contact with the group III-V nitride semiconductor layer is formed in the first opening, and a drain electrode in ohmic contact with the group III-V nitride semiconductor layer is formed in the second opening. And a process of
Forming a gate electrode in Schottky contact with the III-V nitride semiconductor layer in a region between the source electrode and the drain electrode. 前記保護膜及び前記III−Ｖ族窒化物半導体層をアニールする工程において、前記保護膜は窒素雰囲気、窒素含有雰囲気のいずれかの中に配置される請求項１に記載の半導体トランジスタの製造方法。   2. The method of manufacturing a semiconductor transistor according to claim 1, wherein in the step of annealing the protective film and the group III-V nitride semiconductor layer, the protective film is disposed in either a nitrogen atmosphere or a nitrogen-containing atmosphere. 前記保護膜及び前記III−Ｖ族窒化物半導体層をアニールする温度は、９００℃〜１０００℃の範囲にあることを特徴とする請求項１又は請求項２に記載の半導体トランジスタの製造方法。   3. The method of manufacturing a semiconductor transistor according to claim 1, wherein a temperature for annealing the protective film and the group III-V nitride semiconductor layer is in a range of 900 ° C. to 1000 ° C. 3. 前記保護膜は、二酸化シリコン、窒化シリコン、酸化マグネシウム、アルミナのいずれかの絶縁膜であることを特徴とする請求項１乃至請求項３のいずれか１つに記載の半導体トランジスタの製造方法。   4. The method of manufacturing a semiconductor transistor according to claim 1, wherein the protective film is an insulating film of any one of silicon dioxide, silicon nitride, magnesium oxide, and alumina. 前記III−Ｖ族窒化物半導体層は、互いにヘテロ接合される第１のIII−Ｖ族窒化物半導体層と第２のIII−Ｖ族窒化物半導体層を有し、前記第１のIII−Ｖ族窒化物半導体層と前記第２のIII−Ｖ族窒化物半導体層の界面には二次元電子ガスが生成されることを特徴とする請求項１乃至請求項４のいずれか１つに記載の半導体トランジスタ。   The group III-V nitride semiconductor layer includes a first group III-V nitride semiconductor layer and a second group III-V nitride semiconductor layer that are heterojunctioned with each other, and the first group III-V 5. The two-dimensional electron gas is generated at an interface between the group nitride semiconductor layer and the second group III-V nitride semiconductor layer, according to claim 1. Semiconductor transistor.
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