JP2003045896A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of keeping a wafer surface from damages by organic chemicals and plasmas in a GaAs semiconductor process. SOLUTION: The manufacturing method is provided with, as the pre- processing of an ion implantation process, the process (ST10) of forming an insulation film on a GaAs semiconductor substrate surface, the process (ST20) of forming a resist pattern for forming an alignment mark to be used in photolithography in a succeeding process, the process (ST21) of etching the insulation film of a region to form the alignment mark with the resist pattern as a mask by dry etching, the process (ST22) of forming the alignment mark by etching the GaAs semiconductor substrate of the region to form the alignment mark by wet etching, and the process (ST23) of removing the resist pattern after forming the alignment mark.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a Ga of an IC built-in Hall sensor chip.
The present invention relates to a method for manufacturing a semiconductor device for forming an As field effect transistor.

[0002]

2. Description of the Related Art FIGS. 8 to 10 are a flow chart and a sectional view showing a manufacturing process of a conventional GaAs field effect transistor (GaAs MESFET). Hereinafter, FIG. 8 to FIG.
A conventional example will be described using 0. GaAs MESF
The manufacturing process of ET is the alignment mark forming process (ST
100), an ion implantation step (ST110), an annealing step (ST120), and an electrode forming step (ST130).

Alignment mark forming step (ST10
In the case of 0), first, in FIG. 9A, the resist 101 is uniformly applied on the GaAs semiconductor substrate 100 by a spin coater or the like. Next, in FIG. 9B, a mask in which a portion where an alignment mark is formed is made to pass light is used as a resist 1 on the GaAs semiconductor substrate 100.
Then, the exposed portion of the resist is dissolved by immersing it in a developing solution, and the opening is formed by rinsing with a rinse solution.

Next, referring to FIG. 9 (c), sulfuric acid / hydrogen peroxide (H
₂ SO ₄ : H ₂ O: H ₂ O ₂ ) and phosphoric acid hydrogen peroxide (H ₃ PO ₄ : H ₂
By performing wet etching with O: H ₂ O ₂ ) or the like, GaAs in the opening 102 of the resist is etched and the alignment mark 103 is formed. After that, in FIG. 9D, the resist is removed by a solvent to obtain the GaAs semiconductor substrate 100 on which the alignment mark 103 is formed.

In the ion implantation step (ST110), first,
In FIG. 10A, a resist 104 is applied to the GaAs semiconductor substrate 100 on which the alignment mark 103 is formed by a spin coater, and the resist 104 reacts with a mask that allows light to pass through in the portions corresponding to the drain region and the source region. It is exposed to light of the desired wavelength. After that, the resist 104 in the exposed portion is immersed in a developing solution.
Are dissolved and washed with a rinse liquid to form openings 105 and 106.

In FIG. 10B, the resist 104 is used as a mask by an ion implantation apparatus (not shown) and 160 ke
High-dose Si ⁺ ion implantation of V × 2.0 × 10 ¹³ / cm ² is performed, and a high impurity concentration active layer 107 forming a drain region and a source region is formed in the GaAs substrate 100 corresponding to the openings 105 and 106 of the resist. , 108 are formed. In FIG. 10C, the resist 104 is removed. At this time, the resist residue that cannot be peeled off is removed by dry etching. In FIG. 10D, Ga
A resist 109 is applied to the As semiconductor substrate 100 by a spin coater, a mask that allows light to pass through the portion corresponding to the channel layer is applied, and exposure is performed with light having a wavelength with which the resist reacts. After that, the resist in the exposed portion is dissolved by immersing in a developing solution, and the opening 110 is washed with a rinse solution.
Is formed.

In FIG. 10 (e), Si ⁺ is used with the resist 109 as a mask by an ion implantation device (not shown).
Is ion-implanted at 120 keV and 2.0 × 10 ¹² / cm ² to form a channel layer 111 on the GaAs semiconductor substrate 100. After that, the resist 109 is peeled off. At this time, the resist residue that cannot be completely removed is removed by dry etching (FIG. 10F).

The annealing process (ST120) is shown in FIG.
The GaAs semiconductor substrate 100 shown in (f) is placed in an annealing furnace (not shown) and heated at 850 ° C. for about 15 minutes in an arsine (AsH3) atmosphere. As a result, Si ions in the channel layer, the drain region and the source region are activated.

In the electrode forming step (ST130), first, a gate metal is deposited by vapor deposition or sputtering using a resist mask. After that, a gate electrode is formed by a lift-off technique using a resist mask. After that, a drain for forming a drain metal electrode and a source metal electrode by a resist mask,
A source metal film is formed by vapor deposition or the like, and a metal other than the drain region and the source region is separated by a lift-off technique to form a drain metal electrode and a source metal electrode.

[0010]

However, in the above-mentioned conventional method for manufacturing a semiconductor device, the GaAs is removed by the step of stripping the resist with an organic solvent at the end of each step.
The wafer surface was damaged. Particularly in ion implantation, since the resist is greatly damaged, it is necessary to perform the peeling condition so as to promote damage to the GaAs wafer. The condition is that the GaAs surface is etched by several hundred angstroms, and the channel layer itself is lost. In addition, since the resist residue that cannot be completely peeled off must be removed by dry etching, plasma damage to the channel layer occurs. Due to the damage, there is a problem that the transistor characteristics of the completed semiconductor device are not stable (variation occurs on the wafer).

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the wafer surface from being damaged by organic chemicals and plasma in a GaAs semiconductor process in order to solve the above problems.

[0012]

The method for manufacturing a semiconductor device according to the present invention is configured as follows in order to achieve the above object.

According to a first method of manufacturing a semiconductor device (corresponding to claim 1), a high impurity concentration activity forming a drain region formed in a GaAs semiconductor substrate by a plurality of ion implantation steps and at least one annealing step is used. A layer, a high impurity concentration active layer forming a source region, a high impurity concentration active layer forming a drain region and a high impurity concentration active layer forming a source region, and a channel layer joined to a gate electrode In the method of manufacturing a semiconductor device, a step of forming an insulating film on the surface of a GaAs semiconductor substrate as a pre-step of the ion implantation step, and a step of forming a resist pattern for forming an alignment mark used for photolithography in the subsequent steps. And dry the insulating film in the area where the alignment mark is to be formed using the resist pattern as a mask. A step of etching by etching, a step of forming an alignment mark by etching the GaAs semiconductor substrate in the region where the alignment mark is to be formed by wet etching, and a step of removing the resist pattern after forming the alignment mark. It is characterized by having.

According to the first method of manufacturing a semiconductor device, as a pre-step of the ion implantation step, a step of forming an insulating film on the surface of a GaAs semiconductor substrate and an alignment mark used for photolithography in the subsequent steps are formed. For forming a resist pattern for etching, a step of etching the insulating film in a region where an alignment mark is to be formed by dry etching using the resist pattern as a mask, and a GaAs region where an alignment mark is to be formed.
The surface of the GaAs semiconductor substrate in the step of resist stripping with an organic solvent because it has a step of forming an alignment mark by etching the semiconductor substrate by wet etching and a step of removing the resist pattern after forming the alignment mark. Does not damage. Further, since it is not necessary to remove the resist residue that cannot be completely removed by dry etching, the channel layer is not damaged by the plasma. As a result, the transistor characteristics of the semiconductor device do not vary due to damage and are stable.

In the second method for manufacturing a semiconductor device (corresponding to claim 2), preferably, the insulating film is completely removed after a plurality of ion implantation steps and at least one annealing step are completed. It is characterized by doing.

According to the second method of manufacturing a semiconductor device, after the ion implantation process and the annealing process of at least one time are completed, all the insulating film is removed, so that the temperature is raised to room temperature and then to room temperature. It is possible to remove the strain applied to the GaAs semiconductor substrate due to the thermal stress applied due to the difference in the thermal expansion coefficient between the insulating film and the GaAs semiconductor substrate in the cooling annealing process.

A third method of manufacturing a semiconductor device (corresponding to claim 3) is characterized in that, in the above method, the dry etching is preferably reactive ion etching (RIE).

According to the third method of manufacturing a semiconductor device, since dry etching is reactive ion etching (RIE), a fine pattern excellent in anisotropy can be processed and surface damage is relatively small. It can be processed.

A fourth method for manufacturing a semiconductor device (corresponding to claim 4) is the above method, preferably, wet etching is performed using phosphoric acid / hydrogen peroxide (H ₃ PO ₄ : H ₂ ) as an etchant.
O: H ₂ O ₂ ) or sulfuric acid / hydrogen peroxide (H ₂ SO ₄ : H ₂ O: H ₂
It is characterized by using O ₂ ).

According to the fourth method of manufacturing a semiconductor device, since phosphoric acid / hydrogen peroxide or sulfuric acid / hydrogen peroxide is used as an etchant for wet etching, the reaction rate-determining etching can be realized with phosphoric acid / hydrogen peroxide and the composition with sulfuric acid / hydrogen peroxide. By changing the concentration, the etching property can be changed in a wide range, and high-speed etching and precision etching can be performed.

A fifth semiconductor device manufacturing method (corresponding to claim 5) is characterized in that, in the above method, the insulating film is preferably a silicon oxide film or a silicon nitride film.

According to the fifth method of manufacturing a semiconductor device, since the insulating film is a silicon oxide film or a silicon nitride film, it can be easily formed by thermal CVD, plasma CVD, or sputtering. Also, thermal stability with the substrate,
Denseness, adhesion, crack resistance, and no diffusion of substrate constituents into the film. Further, in the case of a silicon nitride film, G
Since it does not contain O ₂ which forms a deep level in the aAs semiconductor, it is also suitable as a protective film for through injection in which the knock-on phenomenon of film constituent elements poses a problem.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

The configurations, shapes, sizes, and arrangement relationships described in the embodiments are merely shown to the extent that the present invention can be understood and put into practice, and numerical values and compositions (materials) of each configuration Is merely an example. Therefore, the present invention is not limited to the embodiments described below, and can be modified into various forms without departing from the scope of the technical idea shown in the claims.

1 to 4 are a flow chart and a sectional view showing a process of manufacturing a GaAs field effect transistor (GaAs MESFET) by the method of manufacturing a semiconductor device according to the embodiment of the present invention. The GaAs MESFET manufacturing process includes an insulating film forming process (ST10), an alignment mark forming process (ST11), and an ion implantation process (ST1).
2), annealing step (ST13), electrode forming step (ST)
14).

The insulating film forming step (ST10) is shown in FIG.
In (a), after removing the natural oxide film from the GaAs semiconductor substrate 10 by washing with buffered hydrofluoric acid (BHF),
A SiO ₂ film 11 having a film thickness of 300 Å is formed as an insulating film by sputtering or CVD.

FIG. 5 shows the alignment mark forming step (S
It is a flowchart of T11). The alignment mark forming step (ST11) includes a step of forming a resist pattern including resist coating, exposure, development and post-baking (ST20), a step of etching the insulating film by dry etching (ST21), RIE etching, and GaAs. The phosphoric acid etching, which is a step (ST22) of etching the semiconductor substrate by wet etching, and the step (ST23) of removing the resist pattern by removing the resist are performed in this order.

Alignment mark forming step (ST11)
First, in FIG. 2B, the GaAs semiconductor substrate 1
A resist 12 is evenly coated on the SiO ₂ film 11 which is an insulating film deposited on the substrate 0 by a spin coater or the like.
Next, in FIG. 2C, a mask in which a portion for forming an alignment mark is made to pass light is formed of GaAs.
The exposed portion of the resist is melted by bringing it into close contact with the resist 12 on the SiO ₂ film 11 which is an insulating film on the semiconductor substrate 10, exposing it with light having a wavelength with which the resist 12 reacts, and then immersing it in a developing solution. The opening 13 is formed.
Then, the developing solution is washed with the rinse solution.

After that, the developing solution or rinsing solution existing in the resist 12 is removed, and post-baking is performed in order to increase the adhesiveness between the resist 12 and the SiO ₂ film 11 which is an insulating film. Next, the SiO ₂ in the opening 13 of the resist 12 is removed by reactive ion etching (RIE) (FIG. 2D).

Next, in FIG. 2E, wet etching with phosphoric acid / hydrogen peroxide mixture (H ₃ PO ₄ : H ₂ O: H ₂ O ₂ ) is performed, so that Ga of the opening 13 of the resist 12 is removed.
As is etched and the alignment mark 14 is formed. After that, in FIG. 2F, the resist 12 is removed to obtain the GaAs semiconductor substrate 10 on which the alignment mark 14 is formed. At this time, G
An SiO ₂ film 11 as an insulating film is formed on the aAs semiconductor substrate.
As a result, the organic solvent is not damaged when the resist is peeled off.

FIG. 6 is a flowchart of the ion implantation step (ST12). The ion implantation step (ST12) is
The steps of forming a resist pattern including resist coating, exposure, development, and post-baking (ST30), through ion implantation (ST31), ashing (ST32), and resist stripping (ST33) are performed in this order.

In the ion implantation step (ST12), first, in FIG. 3A, a resist 15 is spin-coated on the SiO ₂ film 11 which is an insulating film deposited on the GaAs semiconductor substrate 10 on which the alignment mark 14 is formed. Then, a mask that allows light to pass through the portions corresponding to the drain region and the source region is applied, and the resist 15 is exposed to light having a wavelength with which the resist 15 reacts. After that, by immersing it in a developing solution,
The resist 15 in the exposed portion is dissolved, and the opening 16 is formed. Then, rinse the developer with a rinse solution,
Post-baking is performed to remove the developing solution or rinsing solution existing in the resist 15 and increase the adhesiveness between the resist 15 and the SiO ₂ film 11 which is an insulating film.

In FIG. 3B, Si ⁺ is replaced with SiO ₂ by using the resist 15 as a mask with an ion implantation apparatus (not shown).
Through the film 11, 160 keV, 2.0 × 10 ¹³ / cm ²
Through ion implantation is performed to form a drain region 17 and a source region 18 in the GaAs substrate corresponding to the opening 16 of the resist 15. In FIG. 2C, ashing is performed to remove the resist 15. At this time, since the SiO ₂ film 11 which is an insulating film is deposited on the surface of the GaAs semiconductor substrate, the surface of the GaAs semiconductor substrate is not damaged in the resist stripping process by the organic solvent. Further, since it is not necessary to remove the resist residue that cannot be completely removed by dry etching, the channel layer is not damaged by the plasma.

In FIG. 3D, a resist 19 is applied to the GaAs semiconductor substrate 10 by a spin coater, and a mask is applied so that a portion corresponding to the channel layer transmits light.
The resist 19 is exposed to light having a wavelength with which the resist 19 reacts. afterwards,
The resist 19 on the exposed portion is immersed in a solvent.
Melts and an opening 20 is formed.

In FIG. 3 (e), Si ⁺ S is added to the resist 19 as a mask by an ion implantation device (not shown).
120 keV, 2.0 × 10 ¹² / cm ² through the iO ₂ film
Through ion implantation is performed to form a channel layer 21 on the GaAs semiconductor substrate. After that, the resist 19 is peeled off (FIG. 3F). At this time, since the SiO ₂ film 11, which is an insulating film, is deposited on the portion to be the channel layer 21, Ga in the step of stripping the resist by the organic solvent is used.
The surface of the As semiconductor substrate 10 is not damaged. Further, since it is not necessary to remove the resist residue that cannot be completely removed by dry etching, the channel layer is not damaged by the plasma.

Next, the SiO ₂ film 11 is removed by buffered hydrofluoric acid (BHF) (FIG. 3 (g)). At this time, the surface damage can be processed relatively little.

FIG. 7 is a flow chart showing the annealing step (ST13). First, ion-implanted GaAs
The semiconductor substrate is washed with buffered hydrofluoric acid (BHF) (S
T40), SiO by plasma CVD (P-CVD)
_A film of 3000 angstrom is formed by using the _two films as a cap layer (ST41). After that, annealing is performed (ST4
2), washing with water (ST43).

It should be noted here that, while forming a capping layer after removing an SiO ₂ film 11, without removing the SiO ₂ film 11 of 300 Å thickness, on the SiO ₂ film 11 SiO by plasma CVD (P-CVD)
By depositing _two films with a film thickness of 2700 angstroms, an S film with a total film thickness of 3000 angstroms can be obtained.
The iO ₂ film can also be used as the cap layer.

The annealing step (ST13) is shown in FIG.
In FIG. 4, the GaAs semiconductor substrate 10 capped with the SiO ₂ film 22 as an insulating film is put in an annealing furnace (not shown) and heated at 850 ° C. for about 15 minutes (FIG. 4).
(B)). Thereby, Si ions in the channel layer 21, the drain region 17, and the source region 18 are activated. After that, the SiO ₂ film 22 which is an insulating film as a cap film is formed.
Are removed (FIG. 4 (c)). As a result, in order to remove all of the insulating film, the strain applied to the GaAs semiconductor substrate 10 due to the thermal stress caused by the difference in the thermal expansion coefficient between the insulating film and the GaAs semiconductor substrate in the annealing process of raising the temperature to high temperature and then cooling to room temperature. Can be removed.

In the electrode forming step (ST14), first, an SiO ₂ film which is an insulating film is deposited on the surface of the GaAs semiconductor substrate 10 shown in FIG.
After etching SiO ₂ at the position where the gate electrode is formed by reactive ion etching (RIE), a gate metal is deposited by vapor deposition or sputtering. After that, a gate electrode is formed by a lift-off technique using a resist mask. After that, SiO ₂ at the position where the drain metal electrode and the source metal electrode are formed is subjected to reactive ion etching (RI
After etching by E), a drain and source metal film for forming a drain metal electrode and a source metal electrode is formed by vapor deposition or the like. Then, the drain metal electrode and the source metal electrode are formed by separating the metal other than the drain region and the source region by the lift-off technique.

Since no resist is applied to the gate portion in all steps, the gate portion is free from contamination by organic substances. Further, the surface of the GaAs semiconductor substrate is not damaged in the resist stripping process by the organic solvent. Further, since it is not necessary to remove the resist residue that cannot be completely removed by dry etching, the channel layer is not damaged by the plasma. Therefore, when the gate electrode is formed, a good Schottky barrier can be formed, the channel layer can be stably formed, and an FET having no variation can be formed.

Although the silicon oxide film (SiO ₂ film) is used as the insulating film in this embodiment, a silicon nitride film may be used as the insulating film. At that time, since it does not contain O ₂ which forms a deep level in the GaAs semiconductor, it is also suitable as a protective film for through injection in which the knock-on phenomenon of film constituent elements poses a problem.

Further, although phosphoric acid / hydrogen peroxide is used as the etchant for wet etching, sulfuric acid / hydrogen peroxide may be used as the etchant. In that case, the etching property can be changed in a wide range by changing the composition and the concentration, and high-speed etching or precision etching can be performed.

[0044]

As is apparent from the above description, the present invention has the following effects.

In the GaAs semiconductor process, by forming an insulating film on the wafer substrate after opening the wafer and before starting the process, the wafer surface is prevented from being exposed to organic chemicals and plasma. It is possible to prevent damage and stabilize the transistor characteristics of the completed semiconductor device. In addition, through ion implantation and cap annealing can be performed, leading to reduction in man-hours.

[Brief description of drawings]

FIG. 1 shows a GaAs field effect transistor (GaAs MES) manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
It is a flowchart which shows the process of manufacturing (FET).

FIG. 2 shows a GaAs field effect transistor (GaAs MES) manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a process of manufacturing a FET).

FIG. 3 shows a GaAs field effect transistor (GaAs MES) manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a process of manufacturing a FET).

FIG. 4 shows a GaAs field effect transistor (GaAs MES) manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a process of manufacturing a FET).

FIG. 5 is a flowchart of an alignment mark forming step.

FIG. 6 is a flowchart of an ion implantation process.

FIG. 7 is a flowchart showing an annealing process.

FIG. 8 shows a conventional GaAs field effect transistor (GaA).
It is a flowchart which shows the manufacturing process of sMESFET).

FIG. 9 shows a conventional GaAs field effect transistor (GaA).
It is sectional drawing which shows the manufacturing process of sMESFET).

FIG. 10 shows a conventional GaAs field effect transistor (Ga
It is sectional drawing which shows the manufacturing process of (AsMESFET).

[Explanation of symbols]

10 GaAs semiconductor substrate 11 SiO ₂ film 12 resist 13 opening 14 alignment mark 15 resist 16 opening 17 drain region 18 source region 19 resist 20 opening 21 channel layer ST10 insulating film forming step ST11 alignment mark forming step ST12 ion implantation step ST13 annealing step ST14 Electrode forming step ST20 Step of forming resist pattern ST21 Step of etching insulating film by dry etching ST22 Step of etching GaAs semiconductor substrate by wet etching ST23 Step of removing resist pattern

Claims (5)

[Claims] 1. A high impurity concentration active layer forming a drain region and a high impurity concentration active layer forming a source region, which are formed by a plurality of ion implantation steps and at least one annealing step on a GaAs semiconductor substrate. A method of manufacturing a semiconductor device comprising a channel layer that is joined to a gate electrode with the high impurity concentration active layer forming the drain region and the high impurity concentration active layer forming the source region interposed therebetween, the ion implantation step As a pre-step, a step of forming an insulating film on the surface of the GaAs semiconductor substrate, a step of forming a resist pattern for forming an alignment mark used in photolithography in the subsequent steps, and the step of using the resist pattern as a mask Dry etching the insulating film in the area where the alignment mark is to be formed A step of further etching, the GaA of the to be formed an alignment mark region
s A method of manufacturing a semiconductor device, comprising: a step of forming the alignment mark by etching the semiconductor substrate by wet etching; and a step of removing the resist pattern after forming the alignment mark. 2. The method of manufacturing a semiconductor device according to claim 1, wherein all of the insulating film is removed after completion of the plurality of ion implantation steps and the at least one annealing step. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dry etching is reactive ion etching (RIE). 4. In the wet etching, phosphoric acid / hydrogen peroxide (H ₃ PO ₄ : H ₂ O: H ₂ O ₂ ) or sulfuric acid / hydrogen peroxide (H ₂ SO ₄ : H ₂ O: H ₂ O ₂ ) is used as an etchant. The method for manufacturing a semiconductor device according to claim 1, wherein the method is used. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film or a silicon nitride film.