JPH01214161A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPH01214161A JPH01214161A JP3851188A JP3851188A JPH01214161A JP H01214161 A JPH01214161 A JP H01214161A JP 3851188 A JP3851188 A JP 3851188A JP 3851188 A JP3851188 A JP 3851188A JP H01214161 A JPH01214161 A JP H01214161A
- Authority
- JP
- Japan
- Prior art keywords
- impurities
- compound semiconductor
- layers
- ion implantation
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 230000001133 acceleration Effects 0.000 abstract description 7
- 239000000370 acceptor Substances 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000011084 recovery Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 21
- 239000000758 substrate Substances 0.000 description 16
- 239000010408 film Substances 0.000 description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 12
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 239000010931 gold Substances 0.000 description 10
- 239000013078 crystal Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005275 alloying Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 Silicon ions Chemical class 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は化合物半導体装置の製造方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for manufacturing a compound semiconductor device.
（従来の技術）
従来、オーム性コンタクト抵抗の低減は、■半導体基板
を高濃度にドープさせる■被着するコンタトメタル内に
、ドナー又はアクセプタとなる不純物をドープしておき
、アロイ工程中に半導体基板中に拡散させるという二つ
の方向で試みられてきた。(Prior art) Conventionally, the ohmic contact resistance has been reduced by: ■ doping the semiconductor substrate with a high concentration; and doping the contact metal to be deposited with an impurity that will serve as a donor or acceptor. Attempts have been made in two directions: to diffuse the
半導体基板の高濃度ドーピングの手段としては、■−１
イオン注入技術により、不純物を注入し、８００℃程度
の高温でアニールして、注入不純物を結晶格子に取り込
み電気的に活性化する。■−２ＭＢＥ （分子線エピタ
キシー） 、 ＭＯＣＶＤ（有機金属化学蒸着）法等に
より、高濃度にドナー又はアクセプタをドープした結晶
層を成長させる１次に、コンタクトメタル中に不純物を
ドープする方法としては、金属としてＡｕ（金）を主体
として、Ｚｎ、 Ｇｅ等の不純物をドープする方法が採
られている。As a means of high concentration doping of a semiconductor substrate, ■-1
Impurities are implanted using ion implantation technology and annealed at a high temperature of about 800° C. to incorporate the implanted impurities into the crystal lattice and electrically activate them. ■-2 The first method of doping impurities into the contact metal is to grow a crystal layer doped with donors or acceptors at a high concentration using MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), etc. A method is adopted in which the metal is mainly Au (gold) and doped with impurities such as Zn and Ge.
■−１．■−２の基板の高濃度ドーピングの持つ問題点
は以下の通りである。すなわち実際のデバイス製造プロ
セスに於いては、６００℃以上の高温で、拡散・反応等
により、デバイスの他の部位が劣化することがしばしば
である。ところが、不純物の電気的活性化のためのアニ
ールでは８００℃付近、エピタキシャル成長では６００
℃程度の基板温度が必要であるため、これらの技術の適
用は、他の部位の特性の劣化を招く。次にコンタクトメ
タル中にドナー又はアクセプタとなる不純物をドープさ
せる場合、メタル中の不純物の化合物の化合物半導体中
への拡散は充分ではなく、得られるコンタクト抵抗の低
さには限界があった。■-1. The problems associated with high concentration doping of the substrate in (2)-2 are as follows. That is, in actual device manufacturing processes, other parts of the device often deteriorate due to diffusion, reactions, etc. at high temperatures of 600° C. or higher. However, the annealing temperature for electrical activation of impurities is around 800°C, and the temperature for epitaxial growth is around 600°C.
Since a substrate temperature on the order of degrees Celsius is required, application of these techniques leads to deterioration of the characteristics of other parts. Next, when doping a contact metal with an impurity to serve as a donor or acceptor, the impurity compound in the metal does not diffuse sufficiently into the compound semiconductor, and there is a limit to the low contact resistance that can be obtained.
（発明が解決しようとする課題）
このように、オーミックコンタクトの形成には実際の製
造プロセス中では高温工程を用いることが望ましくなく
、８００℃アニール、６００℃エピタキ兵ル成長は使用
できない。コンタクトメタル中の不純物は、半導体中へ
の拡散が不充分であり、低いコンタクト抵抗が得られな
いといった問題点があった。(Problems to be Solved by the Invention) As described above, it is not desirable to use a high-temperature process in the actual manufacturing process to form an ohmic contact, and 800° C. annealing and 600° C. epitaxial growth cannot be used. Impurities in the contact metal are insufficiently diffused into the semiconductor, resulting in a problem that low contact resistance cannot be obtained.
本発明はこのような問題点に鑑みなされたものであり、
デバイスの特性を劣化することなくオーム性コンタクト
抵抗を低減することができる化合物半導体装置の製造方
法を提供することを目的とする。The present invention was made in view of these problems,
An object of the present invention is to provide a method for manufacturing a compound semiconductor device that can reduce ohmic contact resistance without deteriorating device characteristics.
（課題を解決するための手段）
本発明は、化合物半導体層上に電極となる金属薄膜を形
成する化合物半導体装置の製造方法において、化合物半
導体層上に不純物原子をイオン注入す工程と、該化合物
半導体基層を１５０〜４００℃の低温で熱処理する工程
と、熱処理後のイオン注入領域の表面に、金属薄膜を被
着する工程と、金属薄膜及び化合物半導体層を３００〜
４５０℃で熱処理する工程とを具備することを特徴とす
る化合物半導体装置の製造方法である。(Means for Solving the Problems) The present invention provides a method for manufacturing a compound semiconductor device in which a metal thin film serving as an electrode is formed on a compound semiconductor layer, including a step of ion-implanting impurity atoms onto the compound semiconductor layer, and a step of ion-implanting impurity atoms onto the compound semiconductor layer. A process of heat treating the semiconductor base layer at a low temperature of 150 to 400°C, a process of depositing a metal thin film on the surface of the ion implantation region after the heat treatment, and a process of depositing the metal thin film and the compound semiconductor layer at a temperature of 300 to 400°C.
This method of manufacturing a compound semiconductor device is characterized by comprising a step of heat treatment at 450°C.
（作 用）
本発明では、化合物半導体基板上に、極く表面近傍に注
入不純物が分布するように低い加速エネルギーで不純物
のイオン注入を行ない、その後、２５０℃程度の低温処
理でイオン注入により生じた結晶のダメージを回復させ
る。格子間に不純物が分布したこの状態で、Ａｕ、 Ｐ
ｔ等のコンタクトメタロイ
ルを基板表面に被着して、ア士コグすることにより、低
抵抗のオーミックコンタクト抵抗を実現する。(Function) In the present invention, impurity ions are implanted into a compound semiconductor substrate at low acceleration energy so that the implanted impurities are distributed very close to the surface, and then a low-temperature process of about 250°C is performed to improve the ion implantation. Recovers damage from crystals. In this state with impurities distributed between the lattices, Au, P
A low ohmic contact resistance can be achieved by depositing a contact metal foil such as T on the surface of the substrate and cogging it.
イオン注入により生じた結晶のダメージは、２５０℃程
度の熱処理により回復する。この時、注入不純物は、そ
の系が充分な活性化エネルギーを持たないため、格子位
置に取り込まれ電気的に活性化されることはない。この
低温の熱処理後、結晶のダメージは回復するが、注入不
純物は格子間原子として表面に残留する。また、２５０
℃程度の低温では、デバイス上の他の部位を劣化させた
りすることもなく、また、注入不純物が半導体内部に拡
散することもない。Damage to the crystal caused by ion implantation can be recovered by heat treatment at about 250°C. At this time, the implanted impurity is incorporated into the lattice position and is not electrically activated because the system does not have sufficient activation energy. After this low-temperature heat treatment, the damage to the crystal is recovered, but the implanted impurities remain on the surface as interstitial atoms. Also, 250
At a low temperature of about .degree. C., other parts of the device will not deteriorate, and the implanted impurities will not diffuse into the semiconductor.
このようにドナー又はアクセプタとなる不純物を、格子
間原子として持たせた状態で、基板表面にＡｕ、Ｐｔ等
のコンタクトメタルを被着し、アロイすることにより、
Ａｕ等の■族原子の捕獲作用のある原子により、■族す
イトに空孔が生じ、この時、格子間位置にある注入不純
物原子が空孔へ取り込まれるに必要なエネルギーは、４
００℃程度のアロイ温度で充分に与えられ、アロイ中、
注入不純物は電気的に活性化することになる。この結果
、有効にドナー又はアクセプターが生成され、高濃度に
ドーピングされた半導体表面が得られるため。By depositing and alloying a contact metal such as Au or Pt on the substrate surface with impurities that serve as donors or acceptors as interstitial atoms,
A vacancy is created in the group II group by an atom such as Au that has a trapping effect on the group II atom, and at this time, the energy required for the implanted impurity atom at the interstitial position to be taken into the vacancy is 4.
It is sufficiently given at the alloy temperature of about 00℃, and during alloying,
The implanted impurities will be electrically activated. As a result, donors or acceptors are effectively generated and a highly doped semiconductor surface is obtained.
結果として、低抵抗のオーミックコンタクトが実現され
る。As a result, a low resistance ohmic contact is realized.
（実施例）
ｉ）実施例Ｉ
ＡＱＧｅＡｓ／ＧａＡｓヘテロ接合バイポーラトランジ
スタ（ＨＢ Ｔ）製造へ適用した場合について以下に示
す。(Examples) i) Example I A case where the present invention is applied to the manufacture of an AQGeAs/GaAs heterojunction bipolar transistor (HBT) will be described below.
半絶縁性ガリウム砒素基板上にＭＢＥ （分子線エピタ
キシー）により、半導体層構造を形成する（第１図（ａ
） ） 、 ＶＳｉ（タングステンシリサイド）を、基
板表面にスパッタ蒸着し、続いて酸化膜（ＳｉＯ□膜）
を、ＣＶＤ法により蒸着する（第１図（ｂ） ） 、ホ
トリソグラフィーにより、フォトレジストのパターニン
グを行ない、ＲＩＥ （反応性イオンエツチング）によ
って、５ｉｎ２膜及びＶＳｉ膜を加工する（第１図（Ｃ
））。次にＳｉｎ、 、ＷＳｉをマスクにしながらリン
酸＋過酸化水素水の水溶液にて、半導体基板を％ｉｅｔ
メサエッチングすることにより、ベース層にあたるｐ型
ＧａＡｓ層を露出させる（第１図（ｄ）） 、次に同じ
く、Ｓｕｎ、膜、 ＶＳｉ膜をストッパーとしながら、
Ｚｎイオン注入を加速エネルギー３０ｋｅＶ、ドーズ量
５ Ｘ １０” ｃｘａ−”で行なう（第１図（ｅ））
。A semiconductor layer structure is formed on a semi-insulating gallium arsenide substrate by MBE (molecular beam epitaxy) (see Fig. 1(a)).
) ), VSi (tungsten silicide) is sputter-deposited on the substrate surface, followed by an oxide film (SiO□ film).
The photoresist is patterned by photolithography, and the 5in2 film and VSi film are processed by RIE (reactive ion etching) (Fig. 1(C)).
)). Next, the semiconductor substrate was etched with an aqueous solution of phosphoric acid and hydrogen peroxide using Sin, WSi as a mask.
The p-type GaAs layer, which is the base layer, is exposed by mesa etching (Fig. 1(d)). Next, using the Sun film and VSi film as a stopper,
Zn ion implantation is performed at an acceleration energy of 30 keV and a dose of 5 x 10"cxa-" (Fig. 1(e)).
.
この後レジストを完全に除去しＮ２ガス雰囲気中で基板
を２５０℃で、６０分間加熱する。この時、イオン注入
により、発生した半導体表面のダメージはぼぼ完全に回
復し、基板は格子間にＺｎを持つ結晶となる０次にＡｕ
、 Ｐｔをそれぞれ抵抗加熱、Ｅ１２ｅｃｔｒｏｎ−Ｂ
ｅａｍ加熱により蒸着する。Ａｕは、５００人、ｐｔは
、２０００人の薄膜とする。酸化膜を除去することによ
りリフトオフし、これをＮ２雰囲気中で、３６０’Ｃ，
４０秒のラピッドサーマルアロイ（第１図（ｆ））し、
アロイ層を形成する（第１図（ｇ） ） 、コレクタ領
域を、メサエッチング最後にＡｕ／ＡｕＧｅアロイによ
りコレクタ電極を形成し、プロトン注入により素子間分
層を行ない、ＨＢＴを完成する。（第１ 図（ｈン ）
。Thereafter, the resist is completely removed and the substrate is heated at 250° C. for 60 minutes in an N2 gas atmosphere. At this time, the damage to the semiconductor surface caused by the ion implantation is almost completely recovered, and the substrate becomes a zero-order Au crystal with Zn between the lattices.
, Pt resistance heating, E12ectron-B
Vapor deposition is performed by eam heating. The thickness of Au is 500, and the thickness of PT is 2000. Lift-off is performed by removing the oxide film, and this is heated at 360'C in a N2 atmosphere.
Rapid thermal alloying for 40 seconds (Fig. 1 (f)),
An alloy layer is formed (FIG. 1(g)). The collector region is mesa-etched.Finally, a collector electrode is formed from Au/AuGe alloy, and interlayer separation is performed by proton injection to complete the HBT. (Figure 1 (h)
.
このプロセスにより、低抵抗の外部ベースのオーム性接
触が得られ、しかも充分な低温で行なわれるプロセスで
あるため、他の部位例えば１１ｓｉ／ＩｎＧａＡｓ界面
、真性ベース領域で、それぞれ反応、不純物の異常拡散
が起こらないため、良好な特性が保持される。結果とし
て、低抵抗の外部ベース寄生抵抗を有する高周波動作可
能のＨＢＴが実現される。By this process, a low-resistance external-based ohmic contact is obtained, and since it is a process carried out at a sufficiently low temperature, reactions and abnormal diffusion of impurities occur in other regions, such as the 11si/InGaAs interface and the intrinsic base region, respectively. Since this does not occur, good characteristics are maintained. As a result, an HBT capable of high frequency operation with low external base parasitic resistance is realized.
本実施例ではベース電極の形成に本発明を実施したが、
この他、エミッタ及びコレクタ電極の形成に本発明を適
用することができる。また、ＧａＡｓ等の化合物半導体
を用いたＭＩＳＦＥＴのゲート電極あるいはソース・ド
レイン電極、ＭＩＳＦＥＴのソース・ドレイン電極の形
成に本発明を適用してもよい。In this example, the present invention was applied to the formation of the base electrode, but
In addition, the present invention can be applied to the formation of emitter and collector electrodes. Further, the present invention may be applied to the formation of a gate electrode or a source/drain electrode of a MISFET, or a source/drain electrode of a MISFET using a compound semiconductor such as GaAs.
■）実施例２
ＧａＡｓＭＥＳＦＥＴ （金属−半導体接触型電界効果
トラ製
ンジスタ）の新造へ適用した場合について以下に示す。(2) Example 2 A case where the present invention is applied to the new manufacture of a GaAs MESFET (metal-semiconductor contact field effect transistor) will be described below.
半絶縁性ガリウム砒素基板に、活性層形成の為のシリコ
ンのイオン注入を加速電圧３０ｋｅＶ、 ドーズ量３．
ＯＸ １０” ｃｘａ−”で２選択的に行なう、この後
、アルシン雰囲気中で８００℃でアニールを行なう。Silicon ions were implanted into a semi-insulating gallium arsenide substrate to form an active layer at an acceleration voltage of 30 keV and a dose of 3.
OX 10"cxa-" selectively, followed by annealing at 800 DEG C. in an arsine atmosphere.
タングステンシリサイド（ＶＳｉ）を基板表面に１００
０人の厚さでスパッタ蒸着する。さらに、シリコン酸化
膜をＣＶＤ蒸着し、フォトリソグラフィーによってゲー
ト電極形状のパターンニングを行なって、反応性イオン
エツチング（ＲＩＥ）によってシリコン酸化膜とタング
ステンシリサイド膜の加工を行なう。この時、エツチン
グ条件を適当に選ぶことにより、タングステンシリサイ
ド膜にサイドエッチを入れる。フォトレジスト、シリコ
ン酸化膜とゲート電極をストッパーとして用いながら、
シリコンのイオン注入を加速電圧３０ｋｅＶ、ドーズ量
３．ＯＸ １０１３ａ１″′２で行なう。この時の注入
加速電圧は通常二二で用いられる１２０〜１８０ｋｅＶ
よりも遥かに小さいものである。次に、ＡｕＧｅ、 Ａ
ｕを抵抗加熱蒸着法により連続的に、それぞれ１５００
人、 １０００人蒸着口重フォトレジスト上のＡｕＧｅ
／Ａｕをリフトオフ法により除去し、３５０℃で１０分
のアロイを行杭は、ｌＸｌ０−’ΩＩ程度の低い値であ
り、ＧａＡｓＭＥＳＦＥＴの高速動作にとって充分の特
性である。しかもＧａＡｓＭＥＳＦＥＴの高性能化にと
って最も大きな障害となる短チヤネル効果は、一般にソ
ース、ドレイン領域形成の為に注入された高ドーズ量の
Ｓｉ原子が、この原子を活性化するための８００℃付近
での高温の７ニールエ程中に、チャネル領域に拡散しチ
ャネル領域のキャリア分布を乱すことに起因するのであ
るが、本発明によれば高温のアニール工程は不必要な為
、上記の拡散が起こらず良好な素子特性が得られる。100% tungsten silicide (VSi) on the substrate surface
Sputter deposit with a thickness of 0. Further, a silicon oxide film is deposited by CVD, patterned into a gate electrode shape by photolithography, and the silicon oxide film and tungsten silicide film are processed by reactive ion etching (RIE). At this time, side etching is performed on the tungsten silicide film by appropriately selecting etching conditions. Using photoresist, silicon oxide film and gate electrode as a stopper,
Silicon ion implantation was performed at an acceleration voltage of 30 keV and a dose of 3. The injection acceleration voltage at this time is 120 to 180 keV, which is usually used in 22.
It is much smaller than. Next, AuGe, A
1,500 μm each by a resistance heating evaporation method.
1000 people AuGe on heavy photoresist
/Au is removed by lift-off method and alloyed at 350° C. for 10 minutes. The value is as low as lXl0-'ΩI, which is a sufficient characteristic for high-speed operation of GaAs MESFET. Moreover, the short channel effect, which is the biggest obstacle to improving the performance of GaAs MESFETs, is caused by the high dose of Si atoms implanted to form the source and drain regions, which is activated at around 800 degrees Celsius. This is caused by diffusion into the channel region during the high-temperature 7-annealing step, which disturbs the carrier distribution in the channel region. However, according to the present invention, since the high-temperature annealing step is unnecessary, the above-mentioned diffusion does not occur and the result is good. It is possible to obtain excellent device characteristics.
本発明によれば、デバイス特性を劣化することなく、オ
ーム性抵抗が低減した電極形成をかることができる化合
物半導体の製造方法を提供することができる。According to the present invention, it is possible to provide a method for manufacturing a compound semiconductor that can form electrodes with reduced ohmic resistance without deteriorating device characteristics.
第１図は本発明の一実施例を説明するための図である。
１・・・半絶縁性ガリウム砒素基板
２−ｎ”ＧａＡｓＮ
３ ・・・ｎ−ＧａＡｓ層
４・・・ｐ ＱａＡｓ層
５−ｎ ＡｕＧａＡｓ層
６−ｎ”ＧａＡｓ層
７−ｎ＋ＩｎＧａＡｓ層
８・・・エピタキシャル層＋Ｓ、１．ＧａＡｓ基板９・
・・ＷＳｉ膜
１０・・・５ｉｎ２膜
１１・・・フォトレジスト
１２・・・頭出しされたｐ−ＧａＡｓｍ（イ）１３・・
・Ｚｎイオン注入層
１４・・・Ｚｎイオン
１５・＝Ａｕ／Ｔｉ膜
１６・・・低温アニールされたＺｕイオン注入層１７・
＝Ａｕ／ＡｕＧｅアロイ層
１８・・・頭出しされたコレクタ層■
代理人 弁理士 則 近 憲 佑
同 松山光之
第 １ 図FIG. 1 is a diagram for explaining one embodiment of the present invention. 1... Semi-insulating gallium arsenide substrate 2-n'' GaAsN 3... n-GaAs layer 4... p QaAs layer 5-n AuGaAs layer 6-n'' GaAs layer 7-n+InGaAs layer 8... epitaxial Layer+S, 1. GaAs substrate 9・
...WSi film 10...5in2 film 11...Photoresist 12...p-GaAsm (a) 13...
・Zn ion implantation layer 14...Zn ion 15=Au/Ti film 16...Zu ion implantation layer 17 annealed at low temperature
=Au/AuGe alloy layer 18... Collector layer identified ■ Agent Patent attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama Figure 1
Claims (1)
合物半導体装置の製造方法において、化合物半導体層上
に不純物原子をイオン注入する工程と、該化合物半導体
層を１５０〜４００℃の低温で熱処理する工程と、熱処
理後のイオン注入領域の表面に金属薄膜を被着する工程
と、金属薄膜及び化合物半導体層を３００〜４５０℃で
熱処理する工程とを具備することを特徴とする化合物半
導体装置の製造方法。A method for manufacturing a compound semiconductor device in which a metal thin film serving as an electrode is formed on a compound semiconductor layer, which includes a step of ion-implanting impurity atoms onto the compound semiconductor layer, and a step of heat-treating the compound semiconductor layer at a low temperature of 150 to 400°C. A method for manufacturing a compound semiconductor device, comprising the steps of: depositing a metal thin film on the surface of the ion-implanted region after heat treatment; and heat treating the metal thin film and the compound semiconductor layer at 300 to 450°C. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3851188A JPH01214161A (en) | 1988-02-23 | 1988-02-23 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3851188A JPH01214161A (en) | 1988-02-23 | 1988-02-23 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01214161A true JPH01214161A (en) | 1989-08-28 |
Family
ID=12527294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3851188A Pending JPH01214161A (en) | 1988-02-23 | 1988-02-23 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01214161A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003045896A (en) * | 2001-07-26 | 2003-02-14 | Honda Motor Co Ltd | Manufacturing method for semiconductor device |
-
1988
- 1988-02-23 JP JP3851188A patent/JPH01214161A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003045896A (en) * | 2001-07-26 | 2003-02-14 | Honda Motor Co Ltd | Manufacturing method for semiconductor device |
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