JPH0373540A - Hetero-junction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress leak current by providing high resistance regions of small lateral size at a border between an intrinsic transistor and an external base region with p-type dopant ion-implanted. CONSTITUTION:An SiO2 film 7 is deposited on an entire wafer wherein an n<+>-GaAs layer 2, an N-AlGaAs layer 3, a p<+>-GaAs layer 4, an n-GaAs layer 5 and an n<+>-GaAs layer 6 are sequentially grown on a GaAs substrate 1 by MBE method. Then the SiO2 film is etched with a photoresist 8 used as a mask and with the same mask collector layers 6, 5 are further etched so that double ion implantation of Be and F is performed to form an external base region 9 with the collector layer left on the p<+>-GaAs base layer 4. Then staired parts are embedded with SiO2 films 10 and O<+> ions are implanted through a groove hole 10a to form high resistance regions 11. Then after lamp annealing is performed, the SiO2 film 10 is etched and after an SiN film is deposited on the entire face and etched to form a side wall 12, Zn is diffused to form a p-type highly concentrated layer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ultrahigh-speed heterojunction bipolar transistor and a method for manufacturing the same.

(Prior Art) A vertical bipolar transistor having a mesa-type structure has an emitter amplifier structure in which the emitter is provided on the semiconductor surface side, and a collector amplifier structure in which the collector is provided on the semiconductor surface side.
It is broadly divided into up structure.

The current gain cutoff frequency f is the main index that determines the high frequency 5 high speed performance of bipolar transistors.

and the highest oscillation frequency f. In order to improve
It is essential to reduce the collector junction capacitance CIC, but the collector-up structure with significantly less parasitic capacitance is the best way to reduce the collector junction capacitance CIC.
It is extremely advantageous for reducing Cm c (for example, F'
ROCEED[niS OF THE IEEE, vo
l, 70°No, 1. In addition, in the collector-up structure, the vines can be provided on the semiconductor substrate side, so the influence of surface wiring, etc., which poses problems in integration and mounting, is reduced to the emitter. It also has the advantage of being smaller than the up structure. Therefore, it is super fast.

A collector amplifier structure is optimal for achieving high integration.

In this way, the collector amplifier structure is excellent for ultra-high speed and high integration, but it is necessary to form an external base region to suppress carrier injection into regions other than the intrinsic transistor that operates as a transistor. For example, in order to take advantage of the collector-up structure and improve its performance, it is necessary to form a high-quality external base region.
- In a heterojunction bipolar transistor (hereinafter referred to as HBT) using a group compound semiconductor, the intrinsic Carrier injection into the external base region can be suppressed by utilizing the difference between the barrier potential of the hetero PN junction in the transistor portion and the barrier potential of the homo PN junction in the wide bandgap. In particular, the n-p-n type At
GaAs/GaAs HBT is fabricated by forming a P-N junction in a wide bandgap AlGaAs emitter by ion-implanting acceptor impurities such as C, Be, or Mg (for example, Electro
nicsLettsrs, vat, 2L p, 3
15-316.1986) aHowever, N type A
It is well known that a P-N junction formed by ion implantation of Naxebuta impurity into the lGaAs layer has a higher n value and a larger recombination current component than a junction formed by epitaxial growth such as MBE (for example, , J.A.
ppl, Phys.

vol, 62(7), p, 3042-3046.1
987), in order to suppress carrier injection due to the difference in barrier potential with the intrinsic transistor EB junction, it is required that the recombination current component of such an extrinsic base^lGaAs PN junction be small. A P-N junction formed by ion implantation has a large recombination current component and cannot sufficiently suppress carrier injection.

In particular, at a high current density [1], the external base AlGaAs diode operates, the leakage current increases, and the transistor characteristics deteriorate significantly.

Hereinafter, a method for manufacturing a conventional external base of a collector-up structure HBT will be specifically described with reference to the drawings.

FIGS. 3(a) and 3(b) show typical conventional fi-p-n
Figure 2 shows a schematic diagram of the inner and outer base regions of a type collector-up structure ^lGaAs/GaAs-based HBT.

Figure 3 (3) shows an n+-
GaAS (Si doping) layer 2 is 0.7n, N
- AIlliaAi (Si doping) layer 3 of 0.5n
, the p″″-GaAS (Be doped) layer 4 is 0.
In, n-GaAS (5i doping) layer 5 of 0.3
g, n”-GaAs (Si doping) layer 6 is 0
．． 5iOJj was deposited on the entire surface of the wafer, which was sequentially epitaxially grown using the 15n molecular beam epitaxial growth (MBE) method.
7 was deposited by the plasma CVD method, patterning was performed by photolithography, and the stow film was etched by the CJa gas RIE method using the patterned photoresist as a mask.
．． BCI the collector layer of 5! Gas ECR Plasma RrB
Etching is performed using the E method, leaving about 0.05 nm of the collector layer on the p'' GaAs base layer, and forming an external base region 9.
Double ion implantation of Be and F (Be/F
) shows the process of performing. This Be/F double ion implantation method is known to be particularly effective in AlGaAs because it provides a sufficient electrical activation rate and a well-controllable p-type carrier implantation profile. (Appl, Phys, Lett, v
ol, 52゜p, 1493-p, 1495.1988)
, such an effect can be obtained even with the Be/P double ion implantation method.
i? ! ! has been done. After implantation, a short (1-10+) lamp anneal at 800-900° C. is performed to activate the implanted dopants.

(in Fig. 3) is then deposited on the entire surface of the SiN film by plasma CVD.
This figure shows a process in which Zn is diffused at 550'C for 3 minutes in order to reduce the base resistance, after being deposited by the method and then etched by carbon dioxide and gas RIE to form sidewalls 12 in the figure.

Since the P-N junction in the external base region 9 is formed by Be/F ion implantation, the n value is higher than that of the EB junction formed by epitaxial growth, and the recombination current component is dominant. Therefore, leakage current increases particularly in the high current density 6I region, causing a significant deterioration of transistor characteristics.

(Issue 11 to be solved by the invention) In a conventional collector-up type HBT, a wide bandgap external base formed by ion implantation has a P-N
Since n(a of the junction is high and there are many recombination 'rji flow components), there is a problem in that leakage current from the external base increases, particularly in a high current density region, and transistor characteristics are significantly deteriorated.

The present invention was proposed to improve the above-mentioned drawbacks, and its purpose is to reduce leakage of AlGaAs P-N junctions formed by ion implantation by providing a high resistance region at the boundary between the extrinsic base and the intrinsic transistor. suppresses the current,
An object of the present invention is to provide a transistor with a current gain of 6 and excellent high frequency characteristics.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an emitter layer made of a first semiconductor layer having a first conductivity type, and a first semiconductor layer formed on the emitter layer. a base layer consisting of a second semiconductor layer having a second conductivity type and having a smaller bandgap than the base layer; and a first semiconductor layer formed on the base layer.
In a heterojunction bipolar transistor configured of a semiconductor layer including a collector layer separated from a third semiconductor layer having an R electric type, the transistor is provided in a region including at least the first semiconductor layer and the second semiconductor layer. A high resistance region generated by a carrier compensation effect is provided at a boundary between the external base region and the intrinsic transistor in the region including at least the first semiconductor layer and the second semiconductor layer. The gist of the invention is a heterojunction bipolar transistor.

Furthermore, the present invention further provides an emitter layer made of a first semiconductor layer having a first conductivity type, and a second semiconductor layer having a smaller band gap than the first semiconductor layer formed on the emitter layer.
A heterojunction comprising a semiconductor layer including a base layer consisting of a second semiconductor layer having a conductivity type, and a collector layer consisting of a third semiconductor layer having a first conductivity type formed on the base layer. In bipolar transistors,
A process of forming a mesa-type structure by patterning and etching the collector layer, and a groove of ultra-fine dimensions created between the side surface of the collector layer of the mesa-type structure and the dielectric film embedded in the etched region. 0゛ (oxygen) through
A heterojunction comprising the steps of implanting ions and then performing high-temperature annealing to generate a high-resistance region by a carrier compensation effect at a microdimensional boundary between an extrinsic base region and an intrinsic transistor region. The gist of the invention is a method for manufacturing a bipolar transistor.

(Function) In order to solve the problem that the P-N junction in the external base has many recombination current components and it is not possible to sufficiently suppress carrier injection, in the present invention, a high resistance is provided outside the P-N junction. By providing a region, leakage current from the external base can be suppressed, and the HBT has good transistor characteristics.
It is possible to obtain

In order to provide a high resistance region outside the extrinsic base, that is, at the boundary between the extrinsic base and the intrinsic transistor, inert ion species that do not generate carriers by themselves are implanted.
It is considered effective to compensate for carriers by utilizing trap levels caused by semiconductor crystal defects due to implantation damage that occurs at this time.

In GaAs and AIGaAs, H7Q is an ion species that has a carrier compensation effect and makes it semi-insulating.
', 8', etc. are often used, but if high-temperature heat treatment in the actual process is considered, crystal defects caused by implantation damage will be recovered and the carrier compensation effect will be halved. However, among these 0° ions, especially in AIGaAs,
By performing high temperature annealing at about 900° C., a deep level is generated, which increases the carrier compensation effect. On the other hand, in GaAs, deep levels do not occur even when high-temperature annealing is applied; on the contrary, levels caused by semiconductor crystal defects due to implantation damage disappear, and the carrier compensation effect is halved (Appl, Phys. , Lett,
, vol, 52. p, 395-397゜1988)
.

By the way, the problem here is the method of selectively implanting 0° ions into the microscopic boundary region in order to provide this high resistance region in the microscopic boundary region between the extrinsic base and the intrinsic transistor. Needless to say, if this high-resistance region extends beyond the external base, the base resistance, which has an important effect on the device characteristics, will increase significantly, making it impossible to achieve the initial purpose. This creates a need for 0° ions to be selectively implanted only in the critical dimension boundary regions of the intrinsic transistor.

The most effective means for this purpose is to form an implantation mask in a self-aligned manner, and as shown in Figure 2, a dielectric material such as Sing is formed on both sides of the collector mesa using the ECR plasma method and the lift-off method. 01 ions are implanted between the semiconductor layers 5 and 6 and the dielectric film through the grooves formed during lift-off to form a high resistance region in the fine dimension boundary region of the extrinsic base and the intrinsic transistor. becomes possible.

By introducing such a high resistance region at the boundary between the AfGaAs extrinsic base and the intrinsic transistor, leakage current caused by the P-N junction formed by ion implantation is suppressed.
Collector-up structure with excellent current gain and high frequency characteristics ^
It will be possible to provide lGaAs/GaAs HBT.

Examples will be described below based on the drawings.

Note that in the present invention, a case has been described in which a high resistance region capable of suppressing leakage current of the P-N junction is provided mainly on the outside of the external base in the lateral direction. It is also fully possible to suppress the leakage current of the PN junction by providing it outside in the depth direction. If this is the case,
Immediately after performing Be/F double ion implantation to form an external base, the Be/F projected range (Projected R
By implanting 04 ions deeper than the extrinsic base, a high resistance region is easily formed under the extrinsic base.

Further, this embodiment is merely an example, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 illustrates the manufacturing process of an n-p-n type collector-up structure HBT according to the present invention. In this embodiment, an AlGaAs/GaAs semiconductor crystal epitaxially grown on a semi-insulating GaAs substrate will be explained as an example of a crystal material of a transistor.

FIG. 1 (6) shows an n-
GaAs (Si doping concentration; 3 x 10'
@cm-”) layer 2 is 0.7nSN-AIGaAs
(Sl doping concentration i 1 XIO”C13) layer 3
0.5ns p' -GaAs (Be doping concentration i2XIO"am-") layer 4 is O, l, n, n
-GaAs (Si doping concentration; I
? cm-'') layer 5 is 0.3n, and E-GaAs (Si doping concentration; 5XIO''cm-') layer 6 is 0.15n.
This figure shows a process in which a slow film 7 is deposited by plasma CVD on the entire surface of a wafer that has been sequentially epitaxially grown by n-molecular beam epitaxial growth (MBE).

Figure 1 (b) shows a patterned photoresist (PR) 8 that is patterned by photolithography.
Using the same mask, the 5 lot film 7 was etched by the C1Fi gas RIE method, and the collector layer 6.5 in the figure was further etched by the BCIs gas BCR plasma RIBE method using the same mask to form a collector layer on the p4'-GaAs base layer 4. This figure shows the process of forming the external base region 9 by performing double ion implantation of Be and F (Be/F) while leaving 0.05 to 0.1 nm of the layer.

FIG. 1(C) shows the S
i[14 and 0. 5IOJI is deposited on the entire surface from gas at low temperature (room temperature), and by a lift-off method, the stepped portion on one side of the mesa-etched collector semiconductor is etched with the S10□
This figure shows the step of filling the semiconductor layer with a film 10 and implanting 0° ions through a one-side V-shaped groove 10a created between the 1sio□ film and the collector semiconductor to form a high-resistance region 11. ECR plasma deposition layer deposited 5
The ill film has a property that the portion deposited on the side surface is extremely fragile.
In step 20), wet etching was performed for 30 seconds to remove the 510 g film on the weak side surfaces to facilitate lift-off. In this series of steps, a keyed one-sided V-shaped groove hole 10a shown in the figure is formed between the 5iot film 10 and the collector semiconductors 5 and 6. It can be formed easily and with good reproducibility only when the 5rOx film is deposited, lift-off is performed, and a 5rOx film is buried. Other dielectric film deposition methods, e.g.
With CVD and plasma CVD methods, it is difficult to deposit high-quality dielectric films at low temperatures with good reproducibility.Also, sputtering allows dielectric films to be deposited at low temperatures, but ECR It is difficult to form grooves with good reproducibility due to the formation of a film that is weak only on the sides and is effectively etched and then lifted off, as seen in dielectric films deposited by plasma methods. It is known that the angle formed by the single-shaped slot is 20 to 30 degrees.

The thickness of the SiO□ film 10 deposited by the ECR plasma method is set to a thickness that provides sufficient stopping power for the ion-implanted 0*, and is deposited on the collector by the plasma CVD method. The thickness of the Stow film 7 shall not be greater than that of the Stow film 7.

Furthermore, the implantation energy of 01 ions is selected to be deeper than the PN junction formed by Be/F double ion implantation.

Figure 1 (ψ is 5 lots of film 10 deposited by ECR plasma method after lamp annealing at 850°C for about 5 seconds to activate the double ion-implanted Bs).
After etching with F&gas RIE to expose the semiconductor surface 9, a SiN film is deposited on the entire surface by plasma CVD, and C
*After etching with Fi gas, SF, and gas RIB to form sidewalls 12 in the figure, Zn diffusion was performed at 550°C for 3 minutes using the open method to reduce base resistance.
This figure shows the process of forming a p-type high concentration layer (about 10!·elm-" H3. At this time, the width of the sidewall 12 is made to be thicker than the high resistance region 11, and Zn diffusion is prevented. In this embodiment, in which the process is performed from outside the high resistance region 11, the width of the sidewall 12 is about 0.15a.

When the AjGaAsll region in which O''' is implanted in the Keyaki mentioned above is annealed at a high temperature of 850°C, a deep level is generated.
In GaAs, such a deep level does not occur, but rather crystal defects caused by implantation damage are recovered and the carrier compensation effect is reduced. Therefore, even if the high resistance region 11 exists, it is considered that there is almost no increase in the GaAa base resistance.

In FIG. 1(e), patterning is performed by photolithography in order to reduce the area of the external base, and using this patterned photoresist as a mask, the external base region 9.13 is formed using the acts gas ECR plasma RIBE method.
After etching to a depth deeper than the P-N junction formed in the AlGaAs emitter at least in the extrinsic base region, an ECR plasma deposited layer, sio
z 1114 was embedded, and 5 inches was added as an insulating film between the eyebrows.
The process of depositing the I film 15 by plasma CVD, patterning by photolithography, and forming the base electrode 16 by using the spacer lift-off method is shown in this example.
Pt/^U was used.

In FIG. 1(f), the Sing film 15, which is an interlayer insulating film, is patterned by photolithography on the ξ ivy part.
and the embedded BCR plasma sio* film 14 by Cth
The surface of the ri'-GaAs layer 2 is exposed by etching with gas, SP, and gas RIE, and a 510 g film 15 is deposited as an interlayer insulating film by plasma CVD, and an emitter electrode 17 is formed by a spacer lift-off method. Furthermore, the collector portion is patterned by photolithography, and an interlayer insulating film, SlO! Wj41
The surface of the n''-GaAs layer 6 is exposed by etching 5, and the collector electrode 18 is formed by a spacer lift-off method.
In this example, AuG is used as the electrode metal for the emitter electrode and the collector electrode.
e/Ni/Tt/Pt/Au was used. Thereafter, alloy ohmic processing is performed at 360'C, and 11" is implanted for isolation between elements. Pad wiring is performed and the element fabrication process is completed.

In the description of this example, a Be/F double ion implantation method was used to form the external base, but when the double ion implantation method is used, the activation rate in AlGaAs increases compared to single Be'' implantation. However, it is known that a good implantation profile can be obtained.In addition to Be/F used in this example, combinations of double ion implantation include Be/P, Be/
Almost the same effect can be expected with As. Furthermore, C and Mg are also effective as p-type dopants.

In the description of this embodiment, an HBT with a collector-up structure has been described, but the present invention describes an HBT with an emitter-up structure.
It is also applicable to external bases of BT.

(Effects of the Invention) In forming an external base region of a collector-up structure HBT, the present invention provides a high width micro dimension at the boundary between an intrinsic transistor and an external base region into which P-type dopants (Be, Mg, etc.) are ion-implanted. By providing a resistance region, leakage current caused by the external base P-N junction can be suppressed, and a good collector with excellent current gain and high frequency characteristics can be achieved.
It becomes possible to provide up-structured AlGaAs, /GaAs HBT.

[Brief explanation of drawings]

Figures 1(a) to (0) illustrate a series of manufacturing steps for an n-p-n type collector-up structure heterojunction bipolar transistor according to the present invention, and all of them show cross-sectional views of the device. Figure 2 shows a schematic diagram of an ion implantation mask that utilizes the groove created between the ECR buried 5 lots and the collector mesa in order to form a high resistance region with a fine width dimension by 0° ion implantation. Figures 3(a) and 3(b) show a typical conventional Q-p-n
2 shows a schematic diagram of the external base region of a type collector amplifier structure AlGaAs/GaAs heterojunction bipolar transistor. 1...Semi-insulating GaAs substrate 2...r: -GaAs (Si doping concentration;
3X10'・cm-') layer 3---N-^lGaAs (Si doping concentration;
I XIO"C13) Layer 4...p'-GaAs (Be doping concentration;
2 XIO"C13) layer 5...n-GaAs (Si doping concentration;
I Xl0I? c13) Layer 6---n"-GaAs (54 doping concentration, 5'
X10"C11) Layer 7 ・ ・ 8 ・ ・ 9 ・ ・ 10 ・ 10a ・ 11 ・ 12 ・ 13 ・ 14 ・ 15 ・ 16 ・ 17 ・ 18 ・ ・ 7" Las? CV DSi, O1 film/photoresist (PR) ・External base formed by Be/F double ion implantation ・04
ECR-embedded 5tot film for ion implantation mask, groove, uniform resistance region formed by 0° ion implantation, plasma CVD 5iN sidewall, high concentration layer with Zn diffusion, ECR-embedded SiO layer for EB capacitance reduction, interlayer insulation Plasma CV DSIOt film・τi/Pt/^U base electrode・AuGe/Ni/Tl/Pt/Au process Q vine electrode・
AuGe/Ni/Tl/Pt/Au collector electrode Fig. 1 Fig. 4 Fig. 2 Fig. n”-GaAs S, L GaAs

Claims (2)

[Claims] (1) an emitter layer made of a first semiconductor layer having a first conductivity type; a second emitter layer having a second conductivity type and having a smaller band gap than the first semiconductor layer formed on the emitter layer; A heterojunction bipolar transistor configured of a semiconductor layer including a base layer made of a semiconductor layer, and a collector layer made of a third semiconductor layer having a first conductivity type formed on the base layer. Carrier compensation is provided at a boundary between an extrinsic base region provided in a region including the first semiconductor layer and the second semiconductor layer and an intrinsic transistor in the region including at least the first semiconductor layer and the second semiconductor layer. A heterojunction bipolar transistor characterized in that it is provided with a high resistance region generated by the effect. (2) an emitter layer made of a first semiconductor layer having a first conductivity type; a second emitter layer having a second conductivity type and having a smaller band gap than the first semiconductor layer formed on the emitter layer; In a heterojunction bipolar transistor configured of a semiconductor layer including a base layer consisting of a semiconductor layer and a collector layer consisting of a third semiconductor layer having a first conductivity type formed on the base layer, patterning is performed. A process of forming a mesa-type structure by etching the collector layer, and a step of forming a mesa-type structure by etching the collector layer, and O^ A feature of the method is that it includes a step of implanting + (oxygen) ions, and then a step of generating a high-resistance region at the microscopic boundary between the external base region and the intrinsic transistor region by a carrier compensation effect by performing high-temperature annealing treatment. A method for manufacturing a heterojunction bipolar transistor.