JP2728427B2 - Field effect transistor and its manufacturing method - Google Patents

Description

The present invention relates to a field effect transistor using a compound semiconductor, a structure of an integrated circuit using the same, and a method of manufacturing the same.

[Conventional technology]

In order to improve the performance of a field effect transistor using a compound semiconductor such as a GaAs MESFET or a heterojunction FET (hereinafter, abbreviated as HJFET), a structure shown in FIG. 3 has been conventionally known. These conventional GaAs MESFETs basically use an n-type active layer 2 formed on a semi-insulating substrate 1, and have a heat-resistant gate electrode 5, an n-type layer 3 ion-implanted using the electrode 5 as a mask, Further, Si provided on the side wall of the gate electrode 5
It was composed of a sidewall pattern 6 of O ₂ , a structure of an n + -type GaAs epitaxial layer 7 obtained by selective growth, and a source electrode 8 and a drain electrode 9 formed of AuGe-based metal. Here, the sidewall pattern 6 separates the gate electrode 5 and the n + type GaAs epitaxial layer 7,
It is provided to secure a breakdown voltage between the gate and the source and between the gate and the drain.
The mold layer 3 is provided to reduce the resistance of the portion separated by the sidewall pattern 6.

With such a configuration, the formation temperature of the n + -type epitaxial layer 7 can be reduced to 700 ° C. or lower, and the sheet resistance can be reduced by an order of magnitude from the prior art, so that the series resistance of the FET is reduced and the performance is improved. However, the annealing treatment for activating the ion-implanted layer 3 to reduce the resistance between the n + -type epitaxial layer 7 and the gate electrode 5 causes
The drawback is that the characteristics of the shot junction of the gate electrode are degraded, or when an epitaxial layer is used for the n-type active layer 2, impurities contained therein are diffused and the steepness of the carrier concentration is impaired. Atsuta.

[Problems to be solved by the invention]

GaAs FETs using the above-mentioned conventional technology are particularly enhanced type.
The FET (normally OFF type) has a problem that the performance is greatly deteriorated due to annealing at around 800 ° C. after ion implantation.

An object of the present invention is to solve the problem by stopping performing the above-described ion implantation and annealing at a high temperature.

[Means for solving the problem]

The above object is attained by using the step of forming the epitaxial layer by selective growth at least twice.

[Action]

FIG. 1 is a basic structural diagram for explaining the gist of the present invention. Conventionally, in order to avoid the influence of the surface depletion layer, the resistance is reduced by the ion implantation layer 3 using the gate electrode 5 as a mask (FIG. 3). The n ⁺ -type GaAs layer 27 is selectively grown to form a low-resistance layer. Subsequently, after separating a predetermined amount from the side wall of the gate electrode 5, the second selective growth of the n-type GaAs layer 17 is performed to form a sufficiently low electrode layer. With the FET having this basic structure and the manufacturing method, the heat treatment step can be performed at a low temperature, the problem of the shottack characteristics and the deterioration of the active layer, which have conventionally been problems, can be solved, and the performance can be improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in a second manner. This is an element cross section in a main step for explaining a manufacturing procedure of the GaAs FET according to the present invention.

An n-type active layer 2 having a thickness of about 100 nm is formed on the surface of a semi-insulating substrate crystal 1. This n-type active layer is a layer activated by annealing by ion implantation of Si,
An epitaxial layer formed by E, MOCVD, or the like, or more specifically, a layer in which a p-type or undoped GaAs layer is provided below an n-type active layer may be used. Then WSi _x
After the (Dangstin silicide) layer is formed, the gate electrode 5 is formed by a processing step such as dry etching.
In the case of the present invention, the gate electrode has a heat resistant temperature of 600 ° C. for the junction, which is less loose than conventional conditions requiring a heat resistance of 800 ° C., such as W, Mo, and Al alloys. Can be expanded. Next, CVD SiO ₂ 300
After being deposited to a thickness of nm, a sidewall pattern 6 can be formed on the side wall of the gate electrode 5 where the SiO ₂ is etched by RIE (reactive etching apparatus). This thickness is about 200 nm (FIG. 2 (a)).

Subsequently, when an n + type GaAs layer 27 doped with Si is provided as an epitaxially grown layer by MOCVD, the gate electrode 5 and the Si
The layer 27 can be selectively formed on the O ₂ pattern 6 without growing GaAs (FIG. 2B). n + GaAs layer
The thickness of 27 is 200200 nm and the carrier concentration is × 3 × 10 ¹⁸ cm ^-3 .

Subsequently, the sidewall pattern 6 of SiO ₂ is removed using a buffer HF solution (FIG. 3C). Thereafter, an n-type GaAs layer 17 doped with Si is formed again by the same MOCVD method as described above (FIG. 4D). The conditions for this layer are a thickness of 50 nm and a carrier concentration of ８8 × 10 ¹⁷ cm ^-3 . Even if a layer having such a carrier concentration is in contact with the edge of the gate electrode 5, the breakdown of the Schottky junction does not fall below the standard value, but if the n + type GaAs layer shown in FIG. Since the voltage becomes 3 V or less, the selective growth divided into two times is necessary as described above.

Subsequently, the SiO ₂ film 10 is deposited, and lift-off method is used.
An AuGe-based ohmic metal is formed to form a source electrode 8 and a drain electrode 9 (FIG. 3E). In this formation step, the surface where the AuGe-based metal and the GaAs layer are in contact with each other has a reduced contact resistance.
The processing is performed after the type GaAs layer 27 is exposed.

Next, a method of manufacturing the HJFET according to the present invention will be described. The crystal structure of the HJFET is formed on a semi-insulating substrate by MBE or MOCVD epitaxial growth.

The crystal structure of the HJFET basically has the following structure. The first structure has a structure in which an undoped GaAs buffer layer is first laid, an n + type GaAs layer (active layer), and then an undoped AlGaAs layer. In the second structure, an undoped GaAs buffer layer is laid first, followed by n-type Al.
Lay GaAs layer. In the second structure, a two-dimensional electron gas generated at a heterojunction interface between AlGaAs and GaAs forms an active layer.

The procedure for manufacturing an HJFET using this crystal is the same as in FIG. However, n + GaAs is selected by the first selective growth.
When forming the layer 27, it is preferable to perform a pretreatment for etching and removing the AlGaAs layer on the crystal surface. This is an n + GaAs layer
This is to ensure good electrical contact with the active layer below 27. However, when the n-type GaAs layer 17 is formed in the second selective growth, the lower AlGaAs layer may or may not be removed. When manufacturing the structure shown in FIG. 1, it is desirable to include a step of etching and removing the lower AlGaAs layer at least before the first or second selective growth.

〔The invention's effect〕

According to the present invention, since the temperature of the process is reduced,
It is possible to obtain an effect that deterioration of the shot junction does not occur and steepness of the epitaxial layer can be maintained. Further, conventionally in the selective growth method, as compared to the layer that has been formed by ion implantation, it is possible to carrier concentration and thickness can be formed by controlling an arbitrary value, performance such as breakdown voltage and g _m of the FET Can be precisely controlled and increased. Also,
The range of choice of Shotoki Metal has expanded,
The gate metal resistance is reduced by WSi _x
Can be significantly (less than an order of magnitude) lower than 0.3
The performance of a μm gate FET can be improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a GaAs FET device according to the present invention, FIG. 2 is a longitudinal sectional view of the device in each step describing the manufacturing procedure of FIG. 1, and FIG. is there. DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate, 2 ... n-type GaAs layer (active layer), 17 ... n-type GaAs layer formed by selective growth, 7, 27 ... n + type GaAs layer formed by selective growth, 5 ... gate electrode, 8 , 9 ... source and drain electrodes, 6 ... sidewall pattern.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tohru Haga 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-64-72567 (JP, A) JP-A-62 −65378 (JP, A)

Claims (2)

(57) [Claims] 1. A compound semiconductor substrate through which a current carrier of one conductivity type flows, a control electrode for controlling the flow of the current carrier formed on the compound semiconductor substrate by an electric field effect, and the compound semiconductor sandwiching the control electrode A field effect transistor having two power supply portions formed of a compound semiconductor of the same conductivity type as the current carrier formed on the base, and two ohmic electrodes formed in ohmic contact with each of the two power supply portions. The power supply portion has a first semiconductor portion farther from the control electrode and a second semiconductor portion closer to the control electrode, and the first semiconductor portion has a sheet carrier concentration higher than that of the second semiconductor portion. A path that is high and that passes through only the first semiconductor portion of the first and second semiconductor portions in the path of the current carrier flow between the two ohmic electrodes. Field-effect transistor to be. 2. A method for producing a field effect transistor having a control electrode for controlling the flow of a current carrier formed on a compound semiconductor substrate through which a current carrier of one conductivity type flows by an electric field effect. Forming two first compound semiconductor portions by selective epitaxial growth on and in contact with the compound semiconductor substrate with the control electrode interposed therebetween and spaced apart from the control electrode; After the semiconductor part forming step, a step of exposing a region of the compound semiconductor substrate corresponding to the space between the first compound semiconductor part and the control electrode to selective epitaxial growth; and after the exposing step,
Selectively epitaxially growing two second compound semiconductor portions of the same conductivity type as the current carrier and having a lower sheet carrier concentration than the first compound semiconductor portion on the region of the compound semiconductor substrate and the first compound semiconductor portion. And forming two ohmic electrodes so as to make ohmic contact with each of the two first compound semiconductor portions after the second compound semiconductor portion forming step. Manufacturing method of effect type transistor.