JP2904156B2 - Method of manufacturing ohmic electrode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming an ohmic electrode on a III-V compound semiconductor.

[0002]

2. Description of the Related Art Metal-semiconductor field effect transistors (MES) using III-V compound semiconductors such as GaAs.
FET), heterojunction field effect transistor (HJFE)
T) In a device such as a heterojunction bipolar transistor (HBT), it is very important to reduce the contact resistance in the ohmic electrode in order to improve the characteristics. Further, in order to improve long-term operation reliability and to widen a process window such as a wiring step performed after the formation of the ohmic electrode in the manufacturing process, it is important to improve the thermal stability of the ohmic electrode.

A method of manufacturing a high heat resistant ohmic electrode on N-type GaAs is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 6-2678.
87 has been proposed. In this method, first, FIG.
As shown in FIG. 1, a Ni thin film 4 and an In thin film 4 are formed on an N-type GaAs layer 2.
A thin film 5 and a Ge thin film 6 are deposited. Next, by performing a heat treatment, the N-type GaAs substrate 2 is formed as shown in FIG.
An N ⁺ -type GaAs regrowth layer 7 and an N ⁺ -type InGaAs
A regrowth layer 8 is formed, on which a NiGe alloy layer 9 is formed to form an ohmic electrode.

In this method, the energy barrier between the N-type GaAs substrate 2 and the NiGe alloy layer 9 is reduced by the N ⁺ -type InGaAs re-growth layer 8, and a low contact resistance is obtained. Furthermore, since the NiGe alloy has a high melting point of 800 ° C. or more, good heat resistance can be obtained. For example, 400
Even if heat treatment is performed at 1 ° C. for 1 hour, almost no change in contact resistance is observed.

Further, an ohmic electrode having low contact resistance and high heat resistance to N-type GaAs has been proposed by M.K. By Woodall in U.S.A. S. Patent 4801984. In this method, as shown in FIG. 8, on the N-type GaAs layer 2, the N-type InGaAs gradient composition layer 26 in which the InAs mixed crystal ratio of N-type InGaAs is gradually increased toward the surface and the N-type InGaAs mixed crystal ratio is large. Type InGaAs (for example, N-type InAs) layer 27 is formed, and an electrode metal 28 is formed thereon.
Is formed. The energy band of the conduction band from the N-type GaAs layer 2 to the N-type InAs layer 27 is smoothly connected by the N-type InGaAs gradient composition layer 26. N-type In
The Schottky barrier height between the As layer 27 and the electrode metal 28 is almost zero regardless of the type of the electrode metal. Thus, an ideal ohmic electrode having almost no energy barrier can be obtained. Furthermore, WSi is used for the electrode metal.
The use of such a high melting point metal improves the heat resistance without increasing the contact resistance.

[0006]

However, Japanese Patent Laid-Open No. 6-2 / 1994
In the method for manufacturing an ohmic electrode shown in US Pat.
Since the N ⁺ -type InGaAs layer formed by the regrowth is thin and difficult to form uniformly, the contact resistance tends to increase, and the uniformity of the contact resistance within the substrate surface and the uniformity between lots decrease. is there. This is a metal thin film,
In particular, the present inventor believes that the oxidation of In or the oxidation of the GaAs surface hinders the diffusion of metal and does not sufficiently cause regrowth.

The N ⁺ -type InGaAs regrown layer to be formed preferably has a gradient composition structure in which the InAs mixed crystal ratio gradually increases from the GaAs substrate side to the surface side in order to reduce the energy barrier. In the conventional manufacturing method, a gradient composition structure is not formed, and a large energy barrier is generated between the N ⁺ -type InGaAs regrown layer and the GaAs substrate or metal, so that there is a limit in reducing the contact resistance.

In the method for manufacturing an ohmic electrode by Woodall, InGaAs having a large InAs mixed crystal ratio is used.
When the s layer is grown, there is a problem that the lithography process becomes difficult due to a large surface roughness due to a large lattice constant difference from the GaAs substrate. In addition, it is difficult to dry-etch an InGaAs layer having a large InAs mixed crystal ratio, and there is a problem that an unnecessary InGaAs gradient composition layer such as a gate electrode forming portion cannot be removed. These problems can be solved by lowering the InAs mixed crystal ratio of the InGaAs gradient composition layer, but in that case, the contact resistance increases.

The present invention has been made in view of these problems, and a method of manufacturing an ohmic electrode having low contact resistance and high heat resistance with good uniformity in a substrate surface and uniformity between lots. The purpose is to provide.

Further, the present invention solves the problems when using the conventional InGaAs layer having a high InAs mixed crystal ratio, and provides an ohmic electrode having low contact resistance and high heat resistance without causing the problem of surface roughness. It is intended to provide a manufacturing method.

[0011]

[0012]

Means for Solving the Problems The first invention of the present application is:
A thin film made of the first element that becomes an N-type impurity with respect to the III-V compound semiconductor substrate, and a second element that lowers the height of an energy barrier between the III-V compound semiconductor and the metal; A thin film made of a third element, which forms a high melting point alloy by reacting with the first element,
Stacking a thin film made of a second element and a third element on a group V compound semiconductor substrate, and then stacking a thin film made of the first element; Heat treating the compound semiconductor substrate in a reducing gas atmosphere. Here, in the thin film composed of the second element and the third element, the second element and the third element may be continuously mixed in the thin film. A stacked structure of thin films such as element 2 / third element / second element / third element may be used.

According to a second aspect of the present invention, there is provided a semiconductor layer containing a second element for reducing the height of an energy barrier between a III-V compound semiconductor and a metal on a III-V compound semiconductor substrate. And forming I on the semiconductor layer.
A thin film made of a first element which becomes an N-type impurity and a thin film made of a third element which forms a high melting point alloy by a reaction with the first element are formed on a II-V compound semiconductor substrate by a third method. A method of manufacturing an ohmic electrode, comprising: a step of sequentially laminating thin films made of elements; and a step of heat-treating a III-V compound semiconductor substrate on which the semiconductor layer and the thin film are formed in a reducing gas atmosphere. About.

In this method, it is preferable that the semiconductor layer containing the second element is selectively formed in an ohmic electrode formation region.

In the present invention, the group III-V compound semiconductor substrate includes, for example, GaAs, AlGaAs, In
A substrate such as GaAs can be used. These substrates may contain donor impurities as necessary, and may have an epitaxial layer or the like formed on the surface.

The first element which becomes an N-type impurity with respect to the group III-V compound semiconductor can be easily selected from the elements which become the N-type impurity with respect to the group III-V compound semiconductor by heat treatment. It is preferable to select and use the following. For example, Ge, Si, Sn, S, Se, Te
In particular, Ge and Si are preferable because they can be easily formed by vapor deposition and become N-type impurities by heat treatment at a relatively low temperature.

The second element which lowers the height of the energy barrier between the III-V compound semiconductor and the metal is preferably a compound which forms a mixed crystal with the III-V compound semiconductor constituting the substrate, For example, In, Sb, and the like can be given. In particular, In is preferable because the formation of InGaAs makes it possible to make the height of the energy barrier almost zero.

The third element forming a high melting point alloy by reaction with the first element is Ni, Pd, Co,
Pt and the like can be mentioned, and Ni and Pd, which have high reactivity with the group III-V compound semiconductor, are particularly preferable.

As the reducing gas, H ₂ , HI, CO,
SO ₂ , N ₂ H ₄ , NH ₃ , SiH ₄ , Si ₂ H ₆ , PH ₃ , H
_{2 S, AsH 3, H 2} Se or the like can be exemplified without particular adverse effect on the compound semiconductor substrate or the like for use in the present invention, handling easy H ₂ is preferable. Further, hydrogen gas or the like may be diluted with an inert gas as needed.

The semiconductor layer containing the second element in the second invention is preferably a mixed crystal compound semiconductor layer containing the second element as a component, for example, a Ga compound such as a GaAs substrate.
For a substrate containing As, I with In being the second element
An nGaAs layer can be used. Further, a graded composition layer in which the ratio of In in the thickness direction is changed in the semiconductor layer may be used.

In the second invention, after a semiconductor layer containing a second element is formed on a III-V semiconductor substrate, a thin film made of a third element is formed thereon, and a thin film made of the third element is further formed. The thin film made of the second element may be formed between the thin film made of the third element and the thin film made of the first element.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, since the heat treatment is performed in a reducing gas atmosphere, the influence of the oxidation of the metal thin film, particularly the In thin film, and the oxidation of the GaAs surface can be removed, and a uniform and thick N ⁺ -type InGaAs layer is formed. Regrowth is possible. Accordingly, the contact resistance can be reduced, and the uniformity of the contact resistance in the substrate surface and the uniformity between lots can be improved.

In a method of first forming a semiconductor layer containing a second element, such as an InGaAs layer, on a substrate, a molecular beam epitaxy (MBE) method, a metal organic chemical vapor deposition (MOVPE) method, or the like is used. By InGaAs
The thickness of the layer and the InAs mixed crystal ratio can be freely designed, and the formation of the gradient composition layer is easy. Accordingly, InGa is formed so as to reduce the energy barrier between the N ⁺ -type InGaAs regrown layer formed after the heat treatment and the GaAs substrate or metal.
It is possible to optimize the structure of the As layer and reduce the contact resistance. Further, since a low contact resistance can be obtained without growing an InGaAs layer having a high InAs mixed crystal ratio, InA
The problem caused by the InGaAs layer having a high s mixed crystal ratio can be avoided.

Further, in the method of selectively forming an InGaAs layer as a semiconductor layer containing the second element in an ohmic electrode formation region on a substrate, a step of removing an unnecessary InGaAs layer such as a gate electrode formation portion is unnecessary. become. Therefore, since it is not necessary to use dry etching, InAs having a smaller InAs mixed crystal ratio having a smaller contact resistance can be used.
Forming a GaAs layer is allowed. In this case, G
Because of the large lattice constant difference from the aGaAs substrate, InGaAs
Although the surface is roughened in the layer, no problem arises because InGaAs on the surface is alloyed with Ni and Ge, and the surface is covered with the NiGe alloy and becomes flat.

[0025]

【Example】

[Embodiment 1] A first embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1D show the first element and the second element.
And the third element are Ge, In, and Ni, respectively.
FIG. 4 is a diagram illustrating an example in which the reducing gas is hydrogen, which is shown in the order of the manufacturing process.

First, as shown in FIG. 1A, a photoresist on an ohmic electrode forming portion is formed on a semi-insulating GaAs substrate 1 on an N-type GaAs layer 2 grown by MBE or MOVPE by photolithography. A pattern 3 is formed.

Next, as shown in FIG. 1B, N-type GaAs
After the GaAs oxide and contaminants on the surface of the s layer 2 are removed by an acid treatment such as phosphoric acid, a Ni thin film 4, an In thin film 5, and a Ge thin film 6 are sequentially deposited by a vacuum evaporation method or a sputtering method. The thickness of each thin film is 75 nm, 6 nm, 100
nm.

Next, as shown in FIG. 1C, the unnecessary metal film is lifted off by removing the photoresist 3 with an organic solvent to form an ohmic electrode pattern.

Next, as shown in FIG.
Method (Rapid Thermal Anneali)
ng (RTA) method). Atmosphere
Using hydrogen gas as the gas gas at 600 ° C for 5 seconds
U. This heat treatment may be performed in a usual electric furnace.
Due to the heat treatment, Ge diffuses into the N-type GaAs layer 2 and N
⁺Type GaAs regrown layer 7 is formed, and In and N⁺Type
N by reaction with GaAs layer⁺-Type InGaAs regrowth layer
8 are formed. A NiGe alloy layer 9 is formed thereon.
You. Thus, an ohmic electrode is formed. this
The contact resistance obtained at the ohmic electrode is 0.3Ωm
m, no change is observed even after storage at 400 ° C for 1 hour.
No. In addition, the uniformity of the contact resistance within the substrate surface and the uniformity between lots
Is also good.

In this embodiment, a Ni / In / Ge laminated film is used.
laminated film of n film / Ge film, Ni / In / Ni / In / N
An i / Ge multilayer film may be used. In that case, Ni
A uniform In layer is formed without depositing In like an island like a / In / Ge laminated film. Therefore, a more uniform N ⁺ -type InGaAs regrown layer 8 is formed, and a lower contact resistance can be obtained.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 (a) to (f)
Represents the first element, the second element, and the third element as G
FIGS. 7A and 7B are diagrams illustrating an example in which a semiconductor layer including e, In, and Ni is used as an N-type InGaAs layer, and a reducing gas is hydrogen, in the order of manufacturing steps.

First, as shown in FIG. 2A, an N-type GaAs layer 2 and an N-type InGaAs layer 10 are grown on a semi-insulating GaAs substrate 1 by MBE or MOVPE. The thickness of the N-type InGaAs layer 10 is set to 10 nm, and a graded composition layer in which the InAs mixed crystal ratio is increased from 0 to 0.3 from the GaAs substrate side to the surface side. The doping concentration of Si is set to 3 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 2B, unnecessary N-type InGaAs layers other than the ohmic electrode forming portion are removed by photolithography and dry etching using a mixed gas of BCl ₃ / SF ₆ .

Next, as shown in FIG. 2C, a photoresist pattern 3 at an ohmic electrode forming portion is formed by photolithography.

Next, as shown in FIG.
After the InGaAs oxide and contaminants on the surface of the aAs layer 10 are removed by an acid treatment such as phosphoric acid, a Ni thin film 4, an In thin film 5, and a Ge thin film 6 are sequentially deposited by a vacuum evaporation method or a sputtering method. The thickness of each thin film is 75 nm and 6 n, respectively.
m and 100 nm.

Next, as shown in FIG. 2E, the unnecessary metal film is lifted off by removing the photoresist 3 with an organic solvent to form an ohmic electrode pattern.

Next, as shown in FIG. 2F, heat treatment is performed at 600 ° C. for 5 seconds by the RTA method using hydrogen gas as an atmosphere gas. This heat treatment may be performed in a usual electric furnace. By the heat treatment, the N-type GaAs layer 2 and N
Ge diffuses into the N ⁺ -type InGaAs layer 10 to form N ⁺ -type GaAs.
An s regrowth layer 7 and an N ⁺ type InGaAs regrowth layer 8 are formed. A NiGe alloy layer 9 is formed thereon. Thus, an ohmic electrode is formed. Since the N ⁺ -type InGaAs regrown layer 8 formed in the ohmic electrode has a gradient composition structure, the N ⁺ -type InGaAs
Regrown layer 8 and N ⁺ -type GaAs regrown layer 7 or NiG
The energy barrier with the e-alloy layer 9 is reduced. Therefore, a lower contact resistance than that of the first embodiment can be obtained,
And the heat resistance does not decrease. Furthermore, N-type InG
Since the InAs mixed crystal ratio of the aAs layer 10 is low, the problem of the InGaAs layer having a high InAs mixed crystal ratio according to the conventional method can be avoided.

In this embodiment, a graded composition layer is used as the N-type InGaAs layer 10, but the InAs mixed crystal ratio may be constant. In addition, In _0.1 Ga _0.9 As / In _0.2 G
A multilayer structure such as a _0.8 As / In _0.3 Ga _0.7 As may be used.

As a metal film, a Ni thin film, an In thin film and G
Although the e thin film was used, only the Ni thin film and the Ge thin film may be used.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings. 3 (a) to 3 (f)
Represents the first element, the second element, and the third element as G
FIGS. 7A and 7B are diagrams illustrating an example in which a semiconductor layer containing e, In, and Ni is used as an N-type InGaAs selective growth layer, and a reducing gas is hydrogen, in the order of manufacturing steps.

First, as shown in FIG. 3A, an SiO ₂ film 11 is formed on a N-type GaAs layer 2 grown on a semi-insulating GaAs substrate 1 by MBE or MOVPE by a chemical vapor deposition method. Grow. By photolithography and dry etching using CF ₄ , an opening is formed in the SiO ₂ film 11 where the ohmic electrode is to be formed.

Next, as shown in FIG. 3B, N-type InGaAs is formed only on the N-type GaAs layer 2 at the opening of the SiO ₂ film by the metal organic molecular beam epitaxy (MOMBE) method.
The selective growth layer 12 is formed. In the MOMBE method,
By using triethylgallium as the Ga source, trimethylindium as the In source, metal arsenic as the As source, and disilane as the N-type dopant, the N-type InGaAs selective growth layer 12 can be easily formed, for example, at a substrate temperature of 500 ° C. . N-type InGaAs
The thickness of the layer 12 is 10 nm, and a graded composition layer in which the InAs mixed crystal ratio is increased from 0 to 0.3 from the GaAs substrate side to the surface side. The Si doping concentration is 3 × 10 ¹⁸ cm
^-3 .

Next, as shown in FIG. 3C, a photoresist pattern 3 is formed on the ohmic electrode forming portion by photolithography.

Next, as shown in FIG.
After removing the InGaAs oxide and contaminants on the surface of the aAs selective growth layer 12 by an acid treatment such as phosphoric acid, the Ni thin film 4, the In thin film 5, and the Ge thin film are formed by a vacuum deposition method or a sputtering method.
The thin films 6 are deposited in this order. Each thin film has a thickness of 75n
m, 6 nm, and 100 nm.

Next, as shown in FIG. 3E, the unnecessary metal film is lifted off by removing the photoresist 3 with an organic solvent to form an ohmic electrode pattern.

Next, as shown in FIG. 3 (f), the RTA method using hydrogen gas
Heat treatment is performed for seconds. This heat treatment may be performed in a usual electric furnace. Due to the heat treatment, Ge diffuses into the N-type GaAs layer 2 and the N-type InGaAs selective growth layer 12 to form N.
^{A +} type GaAs regrowth layer 7 and an N ⁺ type InGaAs regrowth layer 8 are formed. A NiGe alloy layer 9 is formed thereon. Thus, an ohmic electrode is formed. S
If unnecessary, the iO ₂ film 11 is removed with hydrofluoric acid or the like.

The N formed in the ohmic electrode
^{Since the +} type InGaAs regrowth layer 8 has a gradient composition structure, the energy barrier between the N ⁺ type InGaAs regrowth layer 8 and the N ⁺ type GaAs regrowth layer 7 or the NiGe alloy layer 9 is reduced. Therefore, a lower contact resistance than in the first embodiment can be obtained, and the heat resistance does not decrease. Unnecessary InGaAs such as a gate electrode forming part is unnecessary.
Since the step of removing the s layer becomes unnecessary, N-type InGaAs
The InAs mixed crystal ratio of the s selective growth layer 12 can be further increased, and the contact resistance can be further reduced. In this case, since the lattice constant difference from the GaAs substrate is large, the surface of the selectively grown N-type InGaAs layer is roughened. However, there is no problem because InGaAs on the surface is alloyed with Ni and Ge.

In this embodiment, the N-type InGaAs selective growth layer 12 is formed by the MOMBE method.
It can be easily formed by the PE method. Also, N-type InG
Although a graded composition layer was used as the aAs selective growth layer 12,
The InAs mixed crystal ratio may be constant. In addition, In _0.1 Ga _0.9
A multilayer structure such as As / In _0.2 Ga _0.8 As / In _0.3 Ga _0.7 As may be used. In addition, a Ni thin film and In
Although the thin film and the Ge thin film are used, only the Ni thin film and the Ge thin film may be used.

Embodiment 4 Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a cross-sectional view showing a metal / semiconductor field effect transistor (MESFET) having an ohmic electrode formed by the manufacturing method of the present invention.

N-type GaAs is formed on a semi-insulating GaAs substrate 1.
A layer 2 is formed, on which a source / drain electrode 13 and a gate electrode 14 are formed. The N-type GaAs layer 2 is formed by a Si ion implantation method, an MBE method, a MOVPE method, or the like. The source / drain electrodes 13 may be formed by any of the ohmic electrode manufacturing methods shown in the first, second and third embodiments. The gate electrode 14 can be formed by using a Ti / Pt / Au multilayer film, a WSi film, or the like, and combining lithography, vapor deposition, sputtering, lift-off, dry etching, or the like. In this embodiment, since the ohmic electrode having low contact resistance and high heat resistance can be manufactured with high yield, it is possible to improve the performance, reliability and yield of the MESFET.

Embodiment 5 Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a cross-sectional view showing a heterojunction field effect transistor (HJFET) having an ohmic electrode manufactured by the manufacturing method of the present invention.
A non-doped InGaAs channel layer 15 and an N-type AlGaAs electron supply layer 16 are formed on a semi-insulating GaAs substrate 1, and a gate electrode 14 is formed thereon.
In the source / drain electrode region, N ^{+ is} deposited on the N-type AlGaAs electron supply layer 16 to reduce the source resistance.
A type GaAs cap layer 17 is formed, and a source / drain electrode 13 is formed thereon.

The non-doped InGaAs channel layer 15 and the N-type AlGaAs electron supply layer 16 are formed by MBE or MO.
It can be formed by a VPE method or the like. The N ⁺ -type GaAs cap layer 17 can be formed by a method of etching the gate electrode formation portion after growth by the MBE method or the MOVPE method, or a method of selectively growing only the source / drain region by the MOMBE method or the MOVPE method.

The source / drain electrodes 13 may be formed by any of the ohmic electrode manufacturing methods shown in the first, second, and third embodiments. Gate electrode 14
Can be formed by using a Ti / Pt / Au multilayer film, a WSi film, or the like, and combining lithography, vapor deposition or sputtering, lift-off, or dry etching. In this embodiment, ohmic electrodes having low contact resistance and high heat resistance can be manufactured with a high yield, so that the performance and reliability of the HJFET and the yield can be improved.

Embodiment 6 Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a sectional view showing a heterojunction bipolar transistor (HBT) having an ohmic electrode formed by the manufacturing method of the present invention. An N ⁺ -type GaAs sub-collector layer 18, an N ⁻ -type GaAs collector layer 19, and a P ⁺ -type GaAs are formed on a semi-insulating GaAs substrate 1.
Base layer 20, N-type AlGaAs emitter layer 21, N ⁺
Type GaAs emitter cap layer 22 is formed by MBE or MO
It is formed by a VPE method or the like. Collector electrode 2
3, the base electrode 24 and the emitter electrode 25 are respectively
The N ⁺ -type GaAs sub-collector layer 18, the P ⁺ -type GaAs base layer 20, and the N ⁺ -type GaAs emitter cap layer 22 are formed.

For forming the collector electrode 23 and the emitter electrode 25, any of the methods for manufacturing an ohmic electrode shown in the first, second or third embodiment may be used. The base electrode 24 can be formed by depositing AuMn or a Pt / Ti / Pt / Au multilayer film by a combination of a lithography method, a vapor deposition method, a lift-off method, and the like, and alloying by heat treatment.

In this embodiment, an ohmic electrode having low contact resistance and high heat resistance can be manufactured with good yield, and high performance, high reliability and high yield of the HBT can be achieved.

[0057]

According to the present invention, an ohmic electrode having low contact resistance and high heat resistance can be manufactured with good uniformity on the substrate surface and uniformity between lots.

Further, according to the present invention, the problem of using the conventional InGaAs layer having a high InAs mixed crystal ratio is solved, and the ohmic electrode having low contact resistance and high heat resistance without causing the problem of surface roughness. Can be manufactured.

Further, by using the method of manufacturing an ohmic electrode of the present invention, MESFET, HJFET, H
It is possible to improve the performance, reliability and yield of devices such as BT.

[Brief description of the drawings]

FIG. 1 is a process chart of a method for manufacturing an ohmic electrode according to a first embodiment.

FIG. 2 is a process chart of a method for manufacturing an ohmic electrode according to a second embodiment.

FIG. 3 is a process chart of a method for manufacturing an ohmic electrode according to a third embodiment.

FIG. 4 is a cross-sectional view illustrating a structure of a MESFET according to a fourth embodiment.

FIG. 5 is a cross-sectional view for explaining a structure of an HJFET according to a fifth embodiment.

FIG. 6 is a cross-sectional view for explaining a structure of an HBT according to a sixth embodiment.

FIG. 7 is a diagram showing a conventional method for manufacturing an ohmic electrode.

FIG. 8 is a cross-sectional view illustrating a structure of a conventional ohmic electrode.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semi-insulating GaAs substrate 2 N-type GaAs layer 3 photoresist 4 Ni thin film 5 In thin film 6 Ge thin film 7 N ⁺ type GaAs regrowth layer 8 N ⁺ type InGaAs regrowth layer 9 NiGe alloy layer 10 N-type InGaAs layer 11 SiO ₂ film 12 N-type InGaAs selective growth layer 13 source / drain electrode 14 gate electrode 15 non-doped InGaAs channel layer 16 N-type AIGAAs electron supply layer 17 N ⁺ type GaAs cap layer 18 N ⁺ type GaAs subcollector layer 19 N ⁻ type GaAs collector Layer 20 P ⁺ -type GaAs base layer 21 N-type AIGaAs emitter layer 22 N ⁺ -type GaAs emitter cap layer 23 Collector electrode 24 Base electrode 25 Emitter electrode 26 N-type InGaAs gradient composition layer 27 N-type InAs layer 28 Electrode metal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/778 29/812 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/51

Claims (8)

(57) [Claims] A thin film made of a first element which becomes an N-type impurity with respect to a group III-V compound semiconductor substrate;
Forming a thin film made of a third element that forms a high melting point alloy by a reaction between the second element that lowers the height of the energy barrier between the group IV compound semiconductor and the metal and the first element; Stacking a thin film made of the second element and the third element on the group III-V compound semiconductor substrate, and then stacking a thin film made of the first element; Heat treating the group V compound semiconductor substrate in a reducing gas atmosphere. 2. The method according to claim 1, further comprising the step of:
Forming a semiconductor layer containing a second element that reduces the height of the energy barrier between the II-V compound semiconductor and the metal; and forming a semiconductor layer on the III-V compound semiconductor substrate on the semiconductor layer. Laminating a thin film made of a first element to be an N-type impurity and a thin film made of a third element to form a high melting point alloy by reacting with the first element in order from a thin film made of the third element; Heat-treating the group III-V compound semiconductor substrate on which the semiconductor layer and the thin film are formed in a reducing gas atmosphere. 3. The method according to claim 2, wherein the semiconductor layer containing the second element is selectively formed in an ohmic electrode formation region. 4. The method according to claim 1, wherein the first element is Ge or Si, the second element is In, and the third element is N.
The method for producing an ohmic electrode according to claim 1, wherein the method is i or Pd. 5. The method according to claim 1, wherein the reducing gas is hydrogen.
5. The method for producing an ohmic electrode according to any one of 4. 6. A method for manufacturing a metal / semiconductor field effect transistor, comprising the method for manufacturing an ohmic electrode according to claim 1 as one step. 7. A method for manufacturing a heterojunction field-effect transistor, comprising the method for manufacturing an ohmic electrode according to claim 1 as one step. 8. A method for manufacturing a heterojunction bipolar transistor, comprising the method for manufacturing an ohmic electrode according to claim 1 as one step.