JP2667840B2 - Method for manufacturing compound semiconductor device - Google Patents

Method for manufacturing compound semiconductor device

Info

Publication number
JP2667840B2
JP2667840B2 JP62297549A JP29754987A JP2667840B2 JP 2667840 B2 JP2667840 B2 JP 2667840B2 JP 62297549 A JP62297549 A JP 62297549A JP 29754987 A JP29754987 A JP 29754987A JP 2667840 B2 JP2667840 B2 JP 2667840B2
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
silicon oxide
oxide film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62297549A
Other languages
Japanese (ja)
Other versions
JPH01140715A (en
Inventor
淳二 重田
修 加賀谷
康成 梅本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62297549A priority Critical patent/JP2667840B2/en
Publication of JPH01140715A publication Critical patent/JPH01140715A/en
Application granted granted Critical
Publication of JP2667840B2 publication Critical patent/JP2667840B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体装置の製造方法、とくにガリウ
ム・ヒ素を用いた集積回路の製造方法に係り、とくにゲ
ート・リーク電流の少ない電界効果トランジスタの製造
法を提供するものである。 〔従来の技術〕 従来化合物半導体集積回路に用いられる電界効果トラ
ンジスタの製造法は、例えば特開昭58-157172号に記載
されているように、窒化ケイ素膜などの絶縁性の耐熱性
被膜を被着して熱処理する工程を含んでいた。 〔発明が解決しようとする問題点〕 上記従来技術では第2図(a)に示すようにGaAs基板
1にイオン注入で導電層2を形成した後耐熱性被膜3を
被着して熱処理を行ない、不純物を活性化する。次いで
第2図(b)に示すように耐熱性被膜を除去して、TiN,
WSiなどの耐熱性金属4を被着し、次いで第2図(c)
のように該耐熱性金属を加工してゲート電極5を形成し
ていた。 上記従来技術ではゲート電極5は導電層2以外に基板
1と直接接触する構造が形成されていた。このため、基
板−ゲート電極の不要なリーク電流(ゲートリーク電
流)が多いという問題があつた。また、この問題を避け
るため第3図(a)に示すように第2図に示したと同様
の第3図(a)の状態で熱処理し、この熱処理後に耐熱
性被膜を導電層の部分のみを除去する方法も考えられる
が、この方式でもフオトレジスト・パターンに合わせ誤
差があるため、導電層と耐熱性被膜の穴の位置は一致せ
ず、第3図(c)の丸印のようにゲート電極5が基板1
と接触することは避けられずゲートリーク電流の問題が
残る。本発明の目的はゲートリーク電流の少ない電界効
果トランジスタを有する化合物半導体装置の製造方法を
提供するものである。 〔問題点を解決するための手段〕 上記目的は、ゲート電極と基板が接触しない構造とな
るように、熱処理の際に互に選択的にエツチングが可能
な複数の耐熱性被膜を用いることにより達成される。 〔作用〕 すなわちイオン注入に先立ち、耐熱性被膜である窒化
ケイ素膜および酸化ケイ素膜を積層被着した後、酸化ケ
イ素膜の所定の部分を除去して窒化ケイ素膜を露出させ
る。しかる後、イオン注入を行えば、酸化ケイ素膜が除
去された部分のみに窒化ケイ素膜を貫通して不純物がイ
オン注入される。この後熱処理を行ない、酸化ケイ素膜
のみを選択的に除去すれば、第3図(c)の構造が、導
電層2と耐熱性被膜3の穴の位置がずれることなく形成
される。この後ゲート電極5を形成すればゲート電極5
と基板1が接触することがない。 〔実施例〕 以下実施例により本発明を説明する。 まず、第1図により本発明の参考例を説明する。半絶
縁性GaAs基板1に、第1図(a)に示すように窒化ケイ
素膜6を2000Åの厚さに被着した後所定の部分をフオト
レジストをマスクとしてCF4ガスを用いてエツチング除
去した。次いで第1図(b)のように該窒化ケイ素膜を
マスクとしてSiイオンを注入し、導電層2を形成した。
次いで第1図(c)のように酸化ケイ素膜7を3000Å被
着して800℃の温度で熱処理を行ない、注入されたSiイ
オンの活性化を行なつた。次いで第1図(d)のように
弗酸を用いて酸化ケイ素のみを選択的に除去し、ケイ化
タングステン膜8を被着し、第1図(e)のようにゲー
ト電極5を形成した。このような方法では導電層2と窒
化ケイ素膜6の穴の位置はほぼ完全に一致するので、ゲ
ート電極5が基板1に接触することがなくなる。 〔実施例1〕 第4図は本発明による実施例1を説明する図である。
第4図(a)に示すように半絶縁性GaAs基板1上に窒化
ケイ素膜6および酸化ケイ素膜7を積層被着した。次い
で、第4図(b)のようにフオトレジストをマスクとし
て弗酸を用いて酸化ケイ素膜7のみを部分的に除去し、
露出した窒化ケイ素膜6を貫通してSiイオンを注入し、
導電層2を形成した。次いで800℃で熱処理した後第4
図(c)のように、酸化ケイ素膜7をマスクとして窒化
ケイ素6をCF4ガスを用いてエツチング除去した。次い
で酸化ケイ素膜7のみを弗酸で選択除去し、ケイ化タン
グステン膜8を被着すれば第1図(d)と同様な構造が
得られ、次いでケイ化タングステン膜8を加工すれば、
第1図(e)と同様、ゲート電極5が基板1に接触しな
い構造が得られる。 この方法ではイオン注入工程でGaAs結晶が露出してお
らず、不純物汚染を防止することが容易となる。 〔発明の効果〕 以上のように本発明によれば、ゲート電極が導電層の
みと接し、基板部とは接触しない構造を形成できるた
め、ゲートリーク電流の少ない電界効果トランジスタを
得ることができる。 また本実施例によれば酸化ケイ素膜と窒化ケイ素膜を
耐熱性膜に用いたが、他に酸化アルミニウム膜,窒化ア
ルミニウム等、互に選択エツチング可能な複数の耐熱性
膜の組合せなら使用可能である。また基板としてGaAs結
晶を用いたが、シヨツトキーゲート電極電界効果トラン
ジスタを用いた集積回路を形成することのできるGaP,In
P,GaAlAs等にも適用することができるのは勿論である。
Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing an integrated circuit using gallium arsenide. It provides a manufacturing method. [Prior Art] Conventionally, a method of manufacturing a field effect transistor used for a compound semiconductor integrated circuit is to coat an insulating heat-resistant film such as a silicon nitride film as described in, for example, JP-A-58-157172. It included the step of wearing and heat treating. [Problems to be Solved by the Invention] In the above prior art, as shown in FIG. 2 (a), a conductive layer 2 is formed on a GaAs substrate 1 by ion implantation, and then a heat-resistant coating 3 is applied and heat treatment is performed. , Activate impurities. Next, as shown in FIG. 2 (b), the heat-resistant coating was removed, and TiN,
A heat resistant metal 4 such as WSi is deposited, and then FIG. 2 (c).
As described above, the heat resistant metal was processed to form the gate electrode 5. In the above prior art, a structure in which the gate electrode 5 directly contacts the substrate 1 other than the conductive layer 2 is formed. For this reason, there is a problem that there is much unnecessary leak current (gate leak current) between the substrate and the gate electrode. In order to avoid this problem, as shown in FIG. 3 (a), heat treatment is performed in the same state as shown in FIG. 3 (a) as shown in FIG. Although the removal method is conceivable, even in this method, since the photoresist pattern has an alignment error, the positions of the holes in the conductive layer and the heat-resistant film do not coincide with each other, and as shown in FIG. The electrode 5 is the substrate 1
It is inevitable to contact with the gate leakage current. An object of the present invention is to provide a method for manufacturing a compound semiconductor device having a field-effect transistor with a small gate leakage current. [Means for Solving the Problems] The above object is achieved by using a plurality of heat-resistant coatings that can be selectively etched during heat treatment so that the gate electrode and the substrate do not come into contact with each other. To be done. [Operation] That is, prior to ion implantation, a silicon nitride film and a silicon oxide film, which are heat-resistant films, are laminated and applied, and a predetermined portion of the silicon oxide film is removed to expose the silicon nitride film. Thereafter, if ion implantation is performed, impurities are ion-implanted only through the portion where the silicon oxide film has been removed through the silicon nitride film. Thereafter, by performing a heat treatment and selectively removing only the silicon oxide film, the structure shown in FIG. 3C is formed without displacing the positions of the holes in the conductive layer 2 and the heat-resistant film 3. If the gate electrode 5 is formed thereafter, the gate electrode 5
And the substrate 1 do not come into contact with each other. [Examples] The present invention will be described below with reference to Examples. First, a reference example of the present invention will be described with reference to FIG. As shown in FIG. 1 (a), a silicon nitride film 6 was applied to a thickness of 2000 ° on a semi-insulating GaAs substrate 1, and a predetermined portion was etched and removed using CF 4 gas using a photoresist as a mask. . Next, as shown in FIG. 1B, Si ions were implanted using the silicon nitride film as a mask to form a conductive layer 2.
Next, as shown in FIG. 1 (c), a silicon oxide film 7 was applied at 3000 ° C. and heat-treated at a temperature of 800 ° C. to activate the implanted Si ions. Next, as shown in FIG. 1D, only silicon oxide was selectively removed using hydrofluoric acid, a tungsten silicide film 8 was deposited, and a gate electrode 5 was formed as shown in FIG. 1E. . In such a method, the positions of the holes in the conductive layer 2 and the silicon nitride film 6 almost completely coincide with each other, so that the gate electrode 5 does not contact the substrate 1. [Embodiment 1] FIG. 4 is a diagram for explaining Embodiment 1 according to the present invention.
As shown in FIG. 4 (a), a silicon nitride film 6 and a silicon oxide film 7 were laminated on a semi-insulating GaAs substrate 1. Next, as shown in FIG. 4 (b), only the silicon oxide film 7 is partially removed using hydrofluoric acid with the photoresist as a mask.
Si ions are implanted through the exposed silicon nitride film 6,
The conductive layer 2 was formed. 4th after heat treatment at 800 ℃
As shown in FIG. 2C, the silicon nitride 6 was etched and removed using CF 4 gas using the silicon oxide film 7 as a mask. Next, if only the silicon oxide film 7 is selectively removed with hydrofluoric acid and a tungsten silicide film 8 is applied, a structure similar to that shown in FIG. 1D is obtained. Then, if the tungsten silicide film 8 is processed,
As in FIG. 1E, a structure in which the gate electrode 5 does not contact the substrate 1 is obtained. In this method, the GaAs crystal is not exposed in the ion implantation step, and it becomes easy to prevent impurity contamination. [Effects of the Invention] As described above, according to the present invention, a structure in which the gate electrode is in contact with only the conductive layer and not in contact with the substrate can be formed, so that a field-effect transistor with small gate leak current can be obtained. According to the present embodiment, the silicon oxide film and the silicon nitride film are used as the heat-resistant film. However, a combination of a plurality of heat-resistant films that can be selectively etched, such as an aluminum oxide film and an aluminum nitride, can be used. is there. Although a GaAs crystal was used as a substrate, GaP, In which can form an integrated circuit using a Schottky gate electrode field effect transistor is used.
Of course, it can be applied to P, GaAlAs and the like.

【図面の簡単な説明】 第1図は本発明の参考例、第4図は本発明の実施例1を
示す図、第2図および第3図は従来例を示す図である。 1……GaAs基板、2……導電層、3……耐熱性被膜、4
……耐熱性金属、5……ゲート電極、6……窒化ケイ素
膜、7……酸化ケイ素膜、8……ケイ化タングステン
膜。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a reference example of the present invention, FIG. 4 shows a first embodiment of the present invention, and FIGS. 2 and 3 show conventional examples. 1 ... GaAs substrate, 2 ... conductive layer, 3 ... heat resistant coating, 4
... heat-resistant metal, 5 ... gate electrode, 6 ... silicon nitride film, 7 ... silicon oxide film, 8 ... tungsten silicide film.

Claims (1)

(57)【特許請求の範囲】 1.半絶縁性GaAs基板上に窒化ケイ素膜および酸化ケイ
素膜をこの順序で積層被着する工程と、上記酸化ケイ素
膜の一部を除去して上記窒化ケイ素膜を露出させる工程
と、該窒化ケイ素膜の露出部を貫通してイオン注入する
工程と、上記窒化ケイ素膜および上記酸化ケイ素膜で積
層被覆された状態で上記イオン注入された不純物を熱処
理により活性化する工程と、該活性化工程後に上記窒化
ケイ素膜の露出部を除去して上記イオン注入部を露出す
る工程と、該窒化ケイ素膜の露出部の除去工程後に上記
酸化ケイ素膜を全て除去する工程と、上記除去工程によ
り露出された上記イオン注入部および上記窒化ケイ素膜
上に電界効果トランジスタのゲート電極を被覆形成する
工程を有することを特徴とする化合物半導体装置の製造
方法。
(57) [Claims] Stacking and depositing a silicon nitride film and a silicon oxide film in this order on a semi-insulating GaAs substrate; removing a portion of the silicon oxide film to expose the silicon nitride film; Implanting ions through the exposed portion of the silicon nitride film and the silicon oxide film, a step of activating the ion-implanted impurities by heat treatment in a state of being covered with the silicon oxide film, and after the activation step, Removing the exposed portion of the silicon nitride film to expose the ion-implanted portion; removing the exposed portion of the silicon nitride film after removing the exposed portion of the silicon oxide film; and removing the exposed portion by the removing step. A method for manufacturing a compound semiconductor device, comprising a step of forming a gate electrode of a field effect transistor on an ion implantation part and the silicon nitride film.
JP62297549A 1987-11-27 1987-11-27 Method for manufacturing compound semiconductor device Expired - Lifetime JP2667840B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62297549A JP2667840B2 (en) 1987-11-27 1987-11-27 Method for manufacturing compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62297549A JP2667840B2 (en) 1987-11-27 1987-11-27 Method for manufacturing compound semiconductor device

Publications (2)

Publication Number Publication Date
JPH01140715A JPH01140715A (en) 1989-06-01
JP2667840B2 true JP2667840B2 (en) 1997-10-27

Family

ID=17847979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62297549A Expired - Lifetime JP2667840B2 (en) 1987-11-27 1987-11-27 Method for manufacturing compound semiconductor device

Country Status (1)

Country Link
JP (1) JP2667840B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112658A (en) * 1982-12-20 1984-06-29 Toshiba Corp Field effect transistor and manufacture thereof

Also Published As

Publication number Publication date
JPH01140715A (en) 1989-06-01

Similar Documents

Publication Publication Date Title
US4149307A (en) Process for fabricating insulated-gate field-effect transistors with self-aligned contacts
JP2673109B2 (en) Method of manufacturing self-aligned T-gate gallium arsenide metal semiconductor field effect transistor
GB2040564A (en) Method of fabricating MOSFETs
JP2667840B2 (en) Method for manufacturing compound semiconductor device
KR960004087B1 (en) Contact hole forming method of self aligned silicid
KR100448087B1 (en) Method for fabricating spacer of transistor to obtain good profile of subsequent interlayer dielectric
JPH11186548A (en) Semiconductor device and manufacture thereof
JPH06232155A (en) Manufacture of semiconductor device
JP2974839B2 (en) Method for manufacturing semiconductor device
KR100451756B1 (en) Method for fabricating semiconductor device the same
KR100334869B1 (en) Forming method for gate electronic of semiconductor device
JPH04208570A (en) Manufacture of semiconductor device
JP2567845B2 (en) Method for manufacturing field effect transistor
JPH0213929B2 (en)
JPS6151941A (en) Manufacture of electrode wiring film
JPS60110163A (en) Manufacture of mos transistor
JP2001110912A (en) Manufacturing method of semiconductor device
JPH01119071A (en) Compound semiconductor field-effect transistor
JPH01161873A (en) Manufacture of semiconductor device
JPH02218164A (en) Mis type field-effect transistor
JPH0221136B2 (en)
JPS62126631A (en) Formation of contact electrode
JPS58158968A (en) Manufacture of semiconductor device
JPH0783026B2 (en) Method for manufacturing field effect transistor
JPH01233775A (en) Manufacture of mes type semiconductor device