JPH0213929B2 - - Google Patents
Info
- Publication number
- JPH0213929B2 JPH0213929B2 JP58222083A JP22208383A JPH0213929B2 JP H0213929 B2 JPH0213929 B2 JP H0213929B2 JP 58222083 A JP58222083 A JP 58222083A JP 22208383 A JP22208383 A JP 22208383A JP H0213929 B2 JPH0213929 B2 JP H0213929B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- insulating film
- mask
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000002844 melting Methods 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- 230000008018 melting Effects 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 239000010936 titanium Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HXBCHXQSHJCYFO-UHFFFAOYSA-N [Si].[Si].[Si].[W].[W].[W].[W].[W] Chemical compound [Si].[Si].[Si].[W].[W].[W].[W].[W] HXBCHXQSHJCYFO-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
発明の技術分野
本発明は、シヨツトキ・ゲート電極を有する半
導体装置をセルフ・アライメント方式を適用して
製造するのに好適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method suitable for manufacturing a semiconductor device having a shot gate electrode by applying a self-alignment method.
従来技術と問題点
従来、化合物半導体を材料とし、シヨツトキ・
ゲート電極を有する高速動作可能な電界効果半導
体装置が知られている。Conventional technology and problems Conventionally, compound semiconductors have been used as material,
2. Description of the Related Art Field-effect semiconductor devices having a gate electrode and capable of high-speed operation are known.
近年、前記シヨツトキ・ゲート電極を高融点金
属或いはその珪化物、例えば、タングステン・シ
リサイド（W5Si3）で形成し、そのシヨツトキ・
ゲート電極をマスクにして不純物イオンの注入を
行い、所謂、セルフ・アライメント方式でソース
領域及びドレイン領域を形成することが行なわれ
ている。ここで、高融点金属或いはその珪化物を
用いるのは、後の熱処理工程に対処する為のもの
であることは云うまでもない。 In recent years, the shot gate electrode has been formed of a high melting point metal or its silicide, such as tungsten silicide (W 5 Si 3 ),
Impurity ions are implanted using a gate electrode as a mask to form a source region and a drain region by a so-called self-alignment method. It goes without saying that the reason for using the high melting point metal or its silicide here is to cope with the subsequent heat treatment process.
ところで、前記セルフ・アライメント方式でソ
ース電極及びドレイン領域を形成する場合、如何
にイオン注入法を適用してマスク通りの不純物デ
ポジシヨンを行うとは云え、その後、活性化の為
の熱処理を行つた際、かなり横広がりが発生し、
ソース領域及びドレイン領域がシヨツトキ・ゲー
ト電極と重なり、所謂、シヨート・チヤネル効果
に依り閾値電圧Vthが変動することになる。 By the way, when forming the source electrode and drain region using the self-alignment method, no matter how ion implantation is applied to perform impurity deposition according to the mask, when heat treatment for activation is performed afterwards, , considerable horizontal spread occurs,
The source region and the drain region overlap the short gate electrode, and the threshold voltage Vth fluctuates due to the so-called short channel effect.
また、前記欠点とは別に、この種の半導体装置
に於けるシヨツトキ・ゲート電極としては、現
在、高融点金属或いはその珪化物が全盛であり、
特にW5Si3がよく用いられているが、このような
材料は抵抗値が高いので、半導体装置の高速性を
阻害することが大きな欠点となつている。 In addition to the above-mentioned drawbacks, high-melting point metals or their silicides are currently in prime use as shot gate electrodes in this type of semiconductor device.
In particular, W 5 Si 3 is often used, but since such a material has a high resistance value, a major drawback is that it impedes the high speed performance of semiconductor devices.
発明の目的
本発明は、極めて簡単な工程で、セルフ・アラ
イメント方式を適用して形成されたソース領域及
びドレイン領域とシヨツトキ・ゲート電極との間
の距離を調整することができ、また、シヨツト
キ・ゲート電極の導電性を向上することもできる
ような半導体装置の製造方法を提供する。Purpose of the Invention The present invention is capable of adjusting the distance between a shot gate electrode and a source region and a drain region formed by applying a self-alignment method using an extremely simple process. Provided is a method for manufacturing a semiconductor device that can also improve the conductivity of a gate electrode.
発明の構成
本発明に於ける半導体装置の製造方法では、化
合物半導体層上に高融点金属或いはその珪化物か
らなる膜及び該膜と反応せず高温に耐える絶縁膜
を順に形成し、次に、該絶縁膜をパターニングし
てからそれをマスクとして前記高融点金属或いは
その珪化物からなる膜をパターニングしてゲート
電極を形成し、次に、前記絶縁膜及びゲート電極
をマスクとして不純物の導入を行つて領域を形成
し、次に、前記絶縁膜をマスクとして前記ゲート
電極のサイド・エツチングを行つて該ゲート電極
と前記不純物領域との距離を調節し、次に、前記
絶縁膜を除去したところに金属膜を被着させる工
程を採つている。Structure of the Invention In the method for manufacturing a semiconductor device according to the present invention, a film made of a high melting point metal or its silicide and an insulating film that does not react with the film and can withstand high temperatures are formed in this order on a compound semiconductor layer, and then, After patterning the insulating film, using the insulating film as a mask, pattern the film made of the high melting point metal or its silicide to form a gate electrode, and then introducing impurities using the insulating film and the gate electrode as a mask. Then, using the insulating film as a mask, the gate electrode is side-etched to adjust the distance between the gate electrode and the impurity region, and then the insulating film is removed. A process is used to deposit a metal film.
これに依り、熱処理に起因する不純物領域の横
広がりがあつてもシヨート・チヤネル効果に依る
閾値電圧の変動は抑止され、また、高融点金属或
はその珪化物からなるシヨツトキ・ゲート電極の
導電性は良好になる。 As a result, even if the impurity region spreads laterally due to heat treatment, fluctuations in the threshold voltage due to the short channel effect are suppressed, and the conductivity of the short gate electrode made of a high melting point metal or its silicide is suppressed. becomes good.
発明の実施例
第１図乃至第９図は本発明一実施例を解説する
為の工程要所に於ける半導体装置の要部切断側面
図であり、以下、これ等の図を参照しつつ説明す
る。Embodiment of the Invention FIGS. 1 to 9 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention, and the following description will be made with reference to these figures. do.
第１図参照
半絶縁性GaAs基板１に例えば気相エピタキ
シヤル成長法を適用することに依り、ｎ型
GaAs活性層２を厚さ例えば1000〔Å〕程度に
成長させる。Refer to Figure 1. By applying, for example, vapor phase epitaxial growth to the semi-insulating GaAs substrate 1, n-type
The GaAs active layer 2 is grown to a thickness of, for example, about 1000 Å.
例えばスパツタ法を適用することに依り、
W5Si膜３を厚さ例えば2000〔Å〕程度に形成
し、引続いてリアクテイブ・スパツタ法を適用
することに依り、窒化アルミニウム（AlN）
膜４を厚さ例えば2000〔Å〕程度に形成する。 For example, by applying the spatuta method,
By forming a W 5 Si film 3 to a thickness of, for example, about 2000 Å, and subsequently applying a reactive sputtering method, aluminum nitride (AlN) is formed.
The film 4 is formed to have a thickness of, for example, about 2000 Å.
尚、AlN膜４はW5Si3膜３をパターニングす
る為のマスクとして用いられるだけである為、
W5Si3膜３と反応せず、高温に耐える材料であ
れば他の絶縁膜に代替することができる。 Note that since the AlN film 4 is only used as a mask for patterning the W 5 Si 3 film 3,
Any other insulating film can be used as long as it does not react with the W 5 Si 3 film 3 and can withstand high temperatures.
通常のリソグラフイ技術を適用することに依
り、AlN膜４をゲート電極形状にパターニン
グし、パターニングされたAlN膜４をマスク
としてW5Si3膜３のパターニングを行いゲート
電極を形成する。以後、W5Si3膜３をゲート電
極３と呼ぶことにする。 By applying ordinary lithography technology, the AlN film 4 is patterned into the shape of a gate electrode, and the W 5 Si 3 film 3 is patterned using the patterned AlN film 4 as a mask to form a gate electrode. Hereinafter, the W 5 Si 3 film 3 will be referred to as the gate electrode 3.
第２図参照
AlN膜４及びゲート電極３をマスクとして
シリコン（Si）イオンの注入を行う。尚、この
時のドーズ量は1.7×1013〔cm-2〕程度とする。
第３図参照
例えば化学気相堆積（chemical vapour
deposition：CVD）法を適用し、二酸化シリ
コン（SiO2）膜を形成する。Refer to FIG. 2 Silicon (Si) ions are implanted using the AlN film 4 and gate electrode 3 as masks. Note that the dose amount at this time is approximately 1.7×10 13 [cm −2 ].
See Figure 3. For example, chemical vapor deposition (chemical vapor deposition).
A silicon dioxide (SiO 2 ) film is formed by applying a deposition (CVD) method.
温度800〔℃〕、時間10〔分〕の熱処理を行つて
から前記SiO2膜を除去する。 After heat treatment is performed at a temperature of 800 [° C.] and a time of 10 [minutes], the SiO 2 film is removed.
これに依り、さきに注入されたSiイオンは活
性化されn+型ソース領域５及びn+型ドレイン
領域６が形成される。 As a result, the previously implanted Si ions are activated and an n + type source region 5 and an n + type drain region 6 are formed.
第４図参照
AlN膜４をマスクとしてW5Si3膜３のサイ
ド・エツチングを行つて、n+型ソース領域５
及びn+型ドレイン領域６とゲート電極３との
間の距離を調整する。尚、この場合に適用する
エツチング技術としては、エツチヤントに四フ
ツ化炭素（CF4）を用いたドライ・エツチング
法を挙げることができる。Refer to Figure 4. Using the AlN film 4 as a mask, the W 5 Si 3 film 3 is side-etched to form an n + type source region 5.
And the distance between the n + type drain region 6 and the gate electrode 3 is adjusted. The etching technique applied in this case is a dry etching method using carbon tetrafluoride (CF 4 ) as an etchant.
第５図参照
例えばCVD法を適用するることに依り、
SiO2膜７を形成し、その上に、例えばスピ
ン・コート法を適用することに依り、フオト・
レジスト膜８を形成する。尚、SiO2膜７は他
の絶縁膜、例えば窒化シリコン（Si3N4）膜な
どに代えても良い。See Figure 5 For example, by applying the CVD method,
By forming a SiO 2 film 7 and applying, for example, a spin coating method on it, a photo film is formed.
A resist film 8 is formed. Note that the SiO 2 film 7 may be replaced with another insulating film, such as a silicon nitride (Si 3 N 4 ) film.
第６図参照
平行平板型ドライ・エツチング装置及びエツ
チヤントとして酸素（O2）を用いた反応性イ
オン・エツチング法を適用し、フオト・レジス
ト膜８のエツチングを行い、SiO2膜７の一部
表面を露出させる。Refer to Figure 6. The photoresist film 8 is etched using a parallel plate dry etching device and a reactive ion etching method using oxygen (O 2 ) as an etchant, and a part of the surface of the SiO 2 film 7 is etched. expose.
フオト・レジスト膜８に於けるゲート電極３
及びAlN膜４の上方の部分は最も薄くなつて
いるので、前記のようなエツチングを行うこと
に依り、SiO2膜７を選択的に露出させる場合
には好都合でなる。 Gate electrode 3 in photoresist film 8
Since the upper part of the AlN film 4 is the thinnest, it is convenient to selectively expose the SiO 2 film 7 by performing the above-described etching.
第７図参照
湿性の化学的エツチング法或いはエツチヤン
トをCHF3とした反応性イオン・エツチング法
を適用することに依り、前記選択的に露出され
たSiO2膜７をエツチングし、AlN膜４の表面
を露出させる。Refer to FIG. 7. By applying a wet chemical etching method or a reactive ion etching method using CHF 3 as an etchant, the selectively exposed SiO 2 film 7 is etched, and the surface of the AlN film 4 is etched. expose.
第８図参照
例えばエツチヤントとして熱燐酸を用いた化
学エツチング法を適用することに依り、AlN
膜４のみを除去する。See Figure 8. For example, by applying a chemical etching method using hot phosphoric acid as an etchant, AlN
Only film 4 is removed.
蒸着法を適用し、一部にW5Si3からなるゲー
ト電極３の表面が露出されている状態の全面に
チタン／金（Ti／Au）膜９を厚さ例えば2000
〔Å〕程度に形成する。 By applying a vapor deposition method, a titanium/gold (Ti/Au) film 9 is deposited to a thickness of, for example, 2000 mm over the entire surface of the gate electrode 3 made of W 5 Si 3 with the surface partially exposed.
Form to about [Å].
第９図参照
フオト・レジスト膜８を溶解して除去するこ
とに依り、Ti／Au膜９についてリフト・オフ
のパターニングを行い、ゲート電極３の上に在
るTi／Au膜９のみを残留させて他を除去をす
る。Refer to Figure 9 By dissolving and removing the photoresist film 8, lift-off patterning is performed on the Ti/Au film 9, leaving only the Ti/Au film 9 on the gate electrode 3. and remove the others.
SiO2膜７を除去し、適当なマスクを形成し
てから蒸着法を適用することに依り、金・ゲル
マニウム／金（Au・Ge／Au）膜を形成し、
それををパターニングしてソース電極１０及び
ドレイン電極１１を形成する。 A gold/germanium/gold (Au/Ge/Au) film is formed by removing the SiO 2 film 7, forming a suitable mask, and applying a vapor deposition method.
It is patterned to form a source electrode 10 and a drain electrode 11.
発明の効果
本発明の半導体装置の製造方法では、化合物半
導体層上に高融点金属或いはその珪化物からなる
膜及び該膜と反応せず高温に耐える絶縁膜を順に
形成し、次に、該絶縁膜をパターニングしてから
それをマスクとして前記高融点金属或いはその珪
化物からなる膜をパターニングしてゲート電極を
形成し、次に、前記絶縁膜及びゲート電極をマス
クとして不純物のイオン注入を行つてから熱処理
を施して不純物領域を形成し、次に、前記絶縁膜
をマスクとして前記ゲート電極のサイド・エツチ
ングを行つて該ゲート電極と前記不純物領域との
距離を調節し、次に、前記絶縁膜を除去してから
前記ゲート電極上に高導電性の金属膜を被着させ
る工程が含まれている。従つて、ソース領域及び
ドレイン領域などの不純物領域はゲート電極をマ
スクとしたセルフ・アライメント方式で形成する
ことができ、しかも、そのゲート電極となるべき
高融点金属或いはその珪化物からなる膜はプロセ
スの初期段階で形成される為、半導体装置の動作
領域（チヤネル領域）が表出されて汚染されたた
り或いはダメージを受けるなどの問題が解消さ
れ、また、前記サイド・エツチングに依り、ゲー
ト電極と不純物領域との間の距離を調節すること
ができるのでシヨート・チヤネル効果に依る閾値
電圧の変動は抑止され、そして、ゲート電極のサ
イド・エツチングをする為のマスクとなる絶縁膜
は耐熱性の絶縁膜であるから後の熱処理工程に於
いてゲート電極と反応する虞はなく、更にまた、
高融点金属或いは、その珪化物からなるゲート電
極上には高導電性の金属膜が形成されているので
抵抗値は実質的に低減され、高速を維持するのに
有効である。Effects of the Invention In the method for manufacturing a semiconductor device of the present invention, a film made of a high melting point metal or its silicide and an insulating film that does not react with the film and can withstand high temperatures are formed in this order on a compound semiconductor layer, and then the insulating film is After patterning the film, the film made of the high melting point metal or its silicide is patterned using the film as a mask to form a gate electrode, and then impurity ions are implanted using the insulating film and the gate electrode as a mask. A heat treatment is performed to form an impurity region, and then the distance between the gate electrode and the impurity region is adjusted by side etching the gate electrode using the insulating film as a mask, and then the distance between the gate electrode and the impurity region is adjusted. The method includes a step of depositing a highly conductive metal film on the gate electrode after removing the gate electrode. Therefore, impurity regions such as the source region and the drain region can be formed by a self-alignment method using the gate electrode as a mask, and the film made of the high melting point metal or its silicide, which is to become the gate electrode, can be formed by the process. Since it is formed at the initial stage of the process, problems such as the operating area (channel area) of the semiconductor device being exposed and being contaminated or damaged are eliminated. Since the distance between the impurity region and the impurity region can be adjusted, fluctuations in threshold voltage due to the short channel effect can be suppressed, and the insulating film that serves as a mask for side etching the gate electrode is a heat-resistant insulating film. Since it is a film, there is no risk of it reacting with the gate electrode during the subsequent heat treatment process, and furthermore,
Since a highly conductive metal film is formed on the gate electrode made of a high melting point metal or its silicide, the resistance value is substantially reduced, which is effective in maintaining high speed.
第１図乃至第９図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部切断側面
図である。
図に於いて、１は半絶縁性GaAs基板、２はｎ
型GaAs活性層、３はW5Si3膜、４はAlN膜、５
はn+型ソース領域、６はn+型ドレイン領域、７
はSiO2膜、８はフオト・レジスト膜、９はTi／
Au膜、１０はソース電極、１１はドレイン電極
である。
1 to 9 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
type GaAs active layer, 3 is W 5 Si 3 film, 4 is AlN film, 5
is an n + type source region, 6 is an n + type drain region, and 7 is an n + type source region.
is SiO 2 film, 8 is photoresist film, 9 is Ti/
In the Au film, 10 is a source electrode, and 11 is a drain electrode.
Claims (1)
化物からなる膜及び該膜と反応せず高温に耐える
絶縁膜を順に形成し、次に、該絶縁膜をパターニ
ングしてからそれをマスクとして前記高融点金属
或いはその珪化物からなる膜をパターニングして
ゲート電極を形成し、次に、前記絶縁膜及びゲー
ト電極をマスクとして不純物のイオン注入を行つ
てから熱処理を施して不純物領域を形成し、次
に、前記絶縁膜をマスクとして前記ゲート電極の
サイド・エツチングを行つて該ゲート電極と前記
不純物領域との距離を調節し、次に、前記絶縁膜
を除去してから前記ゲート電極上に高導電性の金
属膜を被着させる工程が含まれてなることを特徴
とする半導体装置の製造方法。1. On a compound semiconductor layer, a film made of a high melting point metal or its silicide and an insulating film that does not react with the film and can withstand high temperatures are formed in this order, and then the insulating film is patterned, and then the high temperature film is patterned using it as a mask. A gate electrode is formed by patterning a film made of a melting point metal or its silicide, and then impurity ions are implanted using the insulating film and gate electrode as a mask, and then heat treatment is performed to form an impurity region. Then, the distance between the gate electrode and the impurity region is adjusted by side etching the gate electrode using the insulating film as a mask, and then, after removing the insulating film, a highly conductive layer is formed on the gate electrode. 1. A method for manufacturing a semiconductor device, comprising the step of depositing a metallic film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22208383A JPS60115268A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22208383A JPS60115268A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60115268A JPS60115268A (en) | 1985-06-21 |
| JPH0213929B2 true JPH0213929B2 (en) | 1990-04-05 |
Family
ID=16776856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22208383A Granted JPS60115268A (en) | 1983-11-28 | 1983-11-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60115268A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0810703B2 (en) * | 1986-05-06 | 1996-01-31 | 株式会社日立製作所 | Method for manufacturing field effect transistor |
| JPS647570A (en) * | 1987-01-12 | 1989-01-11 | Int Standard Electric Corp | Manufacture of self-aligning field effect transistor |
| JPH01198079A (en) * | 1988-02-02 | 1989-08-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012985A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS57152168A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS57196581A (en) * | 1981-05-27 | 1982-12-02 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-11-28 JP JP22208383A patent/JPS60115268A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012985A (en) * | 1973-06-01 | 1975-02-10 | ||
| JPS57152168A (en) * | 1981-03-13 | 1982-09-20 | Nec Corp | Manufacture of schottky barrier gate field effect transistor |
| JPS57196581A (en) * | 1981-05-27 | 1982-12-02 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60115268A (en) | 1985-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2673109B2 (en) | Method of manufacturing self-aligned T-gate gallium arsenide metal semiconductor field effect transistor | |
| JP2609267B2 (en) | Method of manufacturing self-aligned gallium arsenide device | |
| JPS5836491B2 (en) | Manufacturing method of semiconductor device | |
| US4997779A (en) | Method of making asymmetrical gate field effect transistor | |
| US5182218A (en) | Production methods for compound semiconductor device having lightly doped drain structure | |
| JPH0621099A (en) | Manufacture of gaas mesfet | |
| JPS6351550B2 (en) | ||
| JPH0213929B2 (en) | ||
| JPH0353774B2 (en) | ||
| JPS6161544B2 (en) | ||
| JPS60130862A (en) | Manufacture of semiconductor device | |
| JPS6160591B2 (en) | ||
| JP3196241B2 (en) | Method for manufacturing semiconductor device | |
| JP2893776B2 (en) | Method for manufacturing semiconductor device | |
| JP2567845B2 (en) | Method for manufacturing field effect transistor | |
| JPH01161873A (en) | Manufacture of semiconductor device | |
| JPH028454B2 (en) | ||
| JPH01251667A (en) | Manufacture of field effect transistor | |
| JPS6037173A (en) | Manufacture of field effect transistor | |
| JP2667840B2 (en) | Method for manufacturing compound semiconductor device | |
| JPH02285645A (en) | Manufacture of semiconductor device | |
| JPS6148262B2 (en) | ||
| JPH03289142A (en) | Manufacture of compound semiconductor device | |
| JPH033932B2 (en) | ||
| JPH01119071A (en) | Compound semiconductor field-effect transistor |