JPH0783026B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JPH0783026B2 JPH0783026B2 JP58146928A JP14692883A JPH0783026B2 JP H0783026 B2 JPH0783026 B2 JP H0783026B2 JP 58146928 A JP58146928 A JP 58146928A JP 14692883 A JP14692883 A JP 14692883A JP H0783026 B2 JPH0783026 B2 JP H0783026B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- layer
- source
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 24
- 230000005669 field effect Effects 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000007747 plating Methods 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 本発明は、寄生抵抗の小さな電界効果トランジスタの製
造方法に関する。The present invention relates to a method for manufacturing a field effect transistor having a small parasitic resistance.
GaAsショットキゲート電界効果トランジスタは、近年高
速ICを指向してその集積化が進められている。ここで最
近試みられている製造プロセスは、特にノーマリオフ型
において重大なソース抵抗を低減させるためのセルフア
ラインプロセスであり、これを第１図を用いて説明す
る。まず半絶縁性基板11上の能動層12上に耐熱性のゲー
ト電極13例えばＷ合金を用いたゲートを形成し（第１図
（ａ））、該ゲート電極13をマスクにし、ソースおよび
ドレイン領域にドナーイオンのイオン注入を行い、さら
にアニールを行ってn+領域14,15を形成し（第１図
（ｂ））、次いでソース電極16およびドレイン電極17を
形成する（第１図（ｃ））プロセスである。かかるプロ
セスによればソース抵抗はかなり小さくなる。しかしな
がら、ソースおよびドレイン電極は通常目合せで形成さ
れ、ゲート端つまりn+領域端に近接させることはできな
いため、素子の微細化に限度があるばかりでなく、ゲー
トが微細化されるに従ってソース抵抗は無視できない大
きさとなる。さらにこの場合、耐熱性ゲート金属、例え
ばTiWやＷシリサイドの抵抗率は比較的大きいので、ゲ
ート抵抗も大きく増大する。この点を改善したプロセス
が本出願人による特願昭56−036986,特願昭56−036983
に提案されている。例えば第２図に示すように、耐熱性
ゲート21上にAu層22が被着された電極マスクにイオン注
入を行い、アニールを行ってn+領域14,15を形成し（第
２図（ａ））、Au層22をマスクにしてソース16およびド
レイン電極17を被着形成する（第２図（ｂ））プロセス
である。なお23はAu層上に被着されたオーム性電極金属
である。該プロセスによれば確かにソース抵抗およびゲ
ート抵抗は極めて小さい値に低減できる。しかしなが
ら、該プロセスでは、耐熱性金属上にAuが被着された状
態でアニールを行うため、Auが拡散し、GaAsと反応しな
いように耐熱性金属の厚さ、およびアニール条件を最適
化する必要がある。また該プロセスにおいてＴ型ゲート
は下側の耐熱性金属のサイドエッチングによって形成す
るため、実際のゲート長がプロセス中に観測できないと
いう不都合さもある。In recent years, GaAs Schottky gate field effect transistors have been integrated toward high-speed ICs. The manufacturing process recently attempted here is a self-alignment process for reducing a significant source resistance particularly in a normally-off type, which will be described with reference to FIG. First, a heat-resistant gate electrode 13 such as a gate using a W alloy is formed on the active layer 12 on the semi-insulating substrate 11 (FIG. 1A), and the gate electrode 13 is used as a mask to form the source and drain regions. Ion implantation of donor ions is performed on the n + regions 14 and 15 to form n + regions 14 and 15 (FIG. 1B), and then a source electrode 16 and a drain electrode 17 are formed (FIG. 1C). ) Is a process. With such a process, the source resistance is considerably reduced. However, since the source and drain electrodes are usually formed by alignment and cannot be brought close to the gate end, that is, the n + region end, not only is there a limit to the miniaturization of the device, but also the source resistance as the gate is miniaturized. Is a size that cannot be ignored. Further, in this case, the resistivity of the refractory gate metal, such as TiW or W silicide, is relatively large, so that the gate resistance is also greatly increased. A process that improves this point is disclosed in Japanese Patent Application No. 56-036986 and Japanese Patent Application No. 56-036983 by the present applicant.
Has been proposed to. For example, as shown in FIG. 2, ion implantation is performed on the electrode mask in which the Au layer 22 is deposited on the heat-resistant gate 21, and annealing is performed to form n + regions 14 and 15 (see FIG. )), The source layer 16 and the drain electrode 17 are deposited by using the Au layer 22 as a mask (FIG. 2 (b)). Note that 23 is an ohmic electrode metal deposited on the Au layer. According to this process, the source resistance and the gate resistance can be reduced to extremely small values. However, in this process, since annealing is performed with Au deposited on the refractory metal, it is necessary to optimize the thickness of the refractory metal and the annealing conditions so that Au diffuses and does not react with GaAs. There is. In addition, since the T-shaped gate is formed by side etching of the lower heat-resistant metal in the process, the actual gate length cannot be observed during the process.
本発明の目的は、改善されたプロセスでの以上のような
不都合さも解消する、ソース抵抗およびゲート抵抗の極
めて小さい電界効果トランジスタの製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a field effect transistor having extremely small source resistance and gate resistance, which eliminates the above disadvantages in the improved process.
本発明によれば半絶縁性基板上に能動層を形成した後、
該能動層上にゲート電極を形成し、該げーと電極をマス
クとして、高ドープコンタクト領域を形成した後、表面
の平坦性が増すように絶縁性の樹脂層を全面に被覆し、
さらに該樹脂層を薄化し、前記ゲート電極の上面を露出
させ、該露出させたゲート電極の上面にAuあるいはAgめ
っき層を自己整合で形成して、前記樹脂層を除去した
後、前記AuあるいはAgめっき層をマスクとしてソースお
よびドレイン電極を形成することを特徴とする電界効果
トランジスタの製造方法が得られる。According to the present invention, after forming an active layer on a semi-insulating substrate,
A gate electrode is formed on the active layer, a highly doped contact region is formed using the gate and electrode as a mask, and then an insulating resin layer is entirely coated to increase the flatness of the surface,
Further, the resin layer is thinned to expose the upper surface of the gate electrode, an Au or Ag plating layer is formed on the exposed upper surface of the gate electrode by self-alignment, and the resin layer is removed. A method of manufacturing a field effect transistor, characterized by forming source and drain electrodes using an Ag plating layer as a mask.
さらに本発明によれば、動作域を兼ねる半絶縁性基板上
に絶縁膜を形成し、該絶縁膜上にゲート電極を形成し、
該ゲート電極をマスクとして高ドープコンタクト領域を
形成した後、表面の平坦性が増すように絶縁性の樹脂層
を全面に被覆し、さらに該樹脂層を薄化し、前記ゲート
電極の上面を露出させ、該露出させたゲート電極の上面
にAuあるいはAgめっき層を自己整合で形成して前記樹脂
層およびソース，ドレイン電極形成領域上の前記絶縁膜
を除去した後、前記AuあるいはAgめっき層をマスクとし
てソースおよびドレイン電極を形成することを特徴とす
る電界効果トランジスタの製造方法が得られる。Furthermore, according to the present invention, an insulating film is formed on a semi-insulating substrate that also serves as an operating region, and a gate electrode is formed on the insulating film,
After forming the highly-doped contact region using the gate electrode as a mask, the entire surface is covered with an insulating resin layer so as to increase the flatness of the surface, and the resin layer is further thinned to expose the upper surface of the gate electrode. A self-aligned Au or Ag plating layer on the exposed upper surface of the gate electrode to remove the resin layer and the insulating film on the source and drain electrode formation regions, and then mask the Au or Ag plating layer. As a result, a method for manufacturing a field effect transistor, which is characterized in that source and drain electrodes are formed, is obtained.
以下本発明についてそれぞれ一実施例をもって詳細に説
明する。Hereinafter, the present invention will be described in detail with reference to examples.
第１の発明の一実施例としてGaAsショットキゲート電界
効果トランジスタを製作した場合について第３図を用い
て説明する。まず半絶縁性GaAs基板11上に、Siイオンを
例えば注入エネルギー50keV,ドース量２×1012cm-3注入
し、800℃10分間アニールに行って、ｎ型能動層12を形
成する（第３図（ａ））。次いでゲート長0.5μｍ、厚
さ0.5μｍのTiW耐熱性ゲート13をドライエッチングによ
って形成する。（第３図（ｂ））。このTiWゲートをマ
スクとしてSiイオンを例えば注入エネルギー100keV,ド
ース量１×1014cm-3でもってゲートの両側に注入し、95
0℃２秒間短時間アニールを行ってn+コンタクト領域14,
15を形成する（第３図（ｃ））。次に表面が平坦になり
やすい樹脂層例えばホトレジスト層31で全面を被覆する
（第３図（ｄ））。すなわちゲート部分ではホトレジス
ト層が他より薄くなるようにする。これは例えば１μｍ
の厚さにポジ型ホトレジストを塗布し、高温でベーキン
グを行って流動化させることによって容易に実現でき
る。次いで、酸素の反応性イオンエッチングにより上方
よりレジストを一様に薄化し、TiWゲートの上面のみ露
出させる（第３図（ｅ））。露出したゲート上面に0.4
μｍの厚さにAuめっき層32を形成する（第３図
（ｆ））。この時ゲート上面のみ露出しているので、新
たなマスクを必要とせず自己整合でめっき層が生長し、
横方向へも厚さと同程度めっき層が生長する結果、Ｔ型
電極が形成される。さらにホトレジスト層除去後該Auめ
っき層32をマスクにして、上方よりオーミック金属のAu
GeNi23を蒸着し、熱処理を行ってソース電極16およびド
レイン電極17を形成すれば電界効果トランジスタが完成
する。（第３図（ｇ））。A case of manufacturing a GaAs Schottky gate field effect transistor as one embodiment of the first invention will be described with reference to FIG. First, Si ions are implanted on the semi-insulating GaAs substrate 11, for example, with an implantation energy of 50 keV and a dose of 2 × 10 12 cm −3, and annealed at 800 ° C. for 10 minutes to form the n-type active layer 12 (third embodiment). Figure (a)). Next, a TiW heat resistant gate 13 having a gate length of 0.5 μm and a thickness of 0.5 μm is formed by dry etching. (FIG. 3 (b)). Using this TiW gate as a mask, Si ions are implanted on both sides of the gate with an implantation energy of 100 keV and a dose of 1 × 10 14 cm -3 , for example.
Annealed for a short time at 0 ℃ for 2 seconds to n + contact region 14,
15 is formed (FIG. 3 (c)). Next, the entire surface is covered with a resin layer such as a photoresist layer 31 whose surface is likely to be flat (FIG. 3 (d)). That is, the photoresist layer is made thinner than the others in the gate portion. This is, for example, 1 μm
It can be easily realized by applying a positive type photoresist to the above thickness and baking at high temperature to fluidize. Then, the resist is uniformly thinned from above by reactive ion etching of oxygen to expose only the upper surface of the TiW gate (FIG. 3 (e)). 0.4 on exposed gate top
The Au plating layer 32 is formed to a thickness of μm (FIG. 3 (f)). At this time, only the top surface of the gate is exposed, so a new mask is not required and the plating layer grows in a self-aligned manner.
As a result of the growth of the plating layer in the lateral direction to the same extent as the thickness, a T-type electrode is formed. Further, after removing the photoresist layer, the Au plating layer 32 is used as a mask and Au of the ohmic metal is applied from above.
The field effect transistor is completed by depositing GeNi23 and performing heat treatment to form the source electrode 16 and the drain electrode 17. (Fig. 3 (g)).
以上より明らかなように、本発明による製造方法では、
リングラフィ技術を用いた微細加工はゲート電極形成の
１回行うだけであり、しかもこのときは精密な位置合せ
は不要であり、他の工程は極めて簡単なセルフアシライ
ンプロセスで寄生抵抗の小さな微細構造の電界効果トラ
ンジスタを製造できる。すなわち上記例では、ゲート長
0.5μｍに対して、実際のゲート電極の配線部分は、抵
抗率の小さいAuの1.3μｍ長の電極が使え、ゲート抵抗
は極めて小さくなる。さらにソース−ゲート間隔が0.4
μｍと短く、ソース抵抗も極めて小さい。なお、ソース
−ゲート間隔はAuめっきの生長量によって制御できる。
さらに本発明の製法においては、Au層の形成前にアニー
ル工程を行うことができるので、アニールの許容温度範
囲および時間範囲を広くとることができる。なお、上記
工程において、TiWゲートを改良するものとして、TiWの
上によりAuめっきの付着性のよいNi等の薄層を被着した
ものを用いてもよい。As is clear from the above, in the manufacturing method according to the present invention,
The fine processing using the lingraphy technique is performed only once for forming the gate electrode, and at this time, precise alignment is not required, and the other steps are extremely simple self-alignment processes, and fine parasitic resistance is small. A field effect transistor having a structure can be manufactured. That is, in the above example, the gate length
In contrast to 0.5 μm, an actual 1.3 μm long Au electrode having a low resistivity can be used for the wiring portion of the gate electrode, and the gate resistance is extremely small. Furthermore, the source-gate spacing is 0.4
It is as short as μm and the source resistance is extremely small. The source-gate spacing can be controlled by the growth amount of Au plating.
Further, in the manufacturing method of the present invention, since the annealing step can be performed before the formation of the Au layer, the allowable temperature range and time range of annealing can be widened. In the above process, a TiW gate may be improved by depositing a thin layer of Ni or the like, which has good adhesiveness for Au plating, on TiW.
ここではAuめっきの方法としては、当然のことながら無
電界めっきおよび電界めっきのどちらの方法を用いても
良い。電界めっきの場合は、電流供給路は、第３図
（ｆ）において紙面に垂直方向にとることができる。す
なわち電界効果トランジスタの素子領域外にもTiW膜を
残置させておいて、それを電流供給路としてAuめっきを
行い、ホトレジスト層31除去後素子領域外の不要のTiW
膜を除去すれば良い。Here, as a method of Au plating, of course, either electroless plating or electrolytic plating may be used. In the case of electroplating, the current supply path can be taken in the direction perpendicular to the paper surface in FIG. 3 (f). That is, the TiW film is left outside the element region of the field effect transistor, and Au plating is performed using it as a current supply path. After removing the photoresist layer 31, unnecessary TiW film outside the element region is removed.
The film may be removed.
以上ではイオン注入によるn+コンタクト領域を形成した
場合について説明したが、コンタクト領域用のイオン注
入およびアニールを行わなければ、通常の構造ではある
がソース−ゲート間およびゲート−ドレイン間の短いシ
ョットキゲート電界効果トランジスタがセルフアライン
プロセスで容易に製作できる。この場合にも以上で説明
した寄生抵抗の小さい効果は発揮できる。Although the case where the n + contact region is formed by ion implantation has been described above, the short Schottky gate between the source-gate and the gate-drain is a normal structure if ion implantation and annealing for the contact region are not performed. The field effect transistor can be easily manufactured by the self-alignment process. Even in this case, the effect of reducing the parasitic resistance described above can be exerted.
本発明の第２の発明の一実施例としてエンハンスメント
型InP絶縁ゲート電界効果トランジスタを製作した場合
について第４図を用いて説明する。まず動作域を兼ねる
半絶縁性InP基板41上に、ゲート絶縁膜としてCVD SiO2
膜42を600Åの厚さに被着し、さらにゲート長１μｍ、
厚さ0.5μｍのMoのゲート電極13を形成し、ゲート電極
をマスクにしてSiイオンを注入し、アニールを行ってn+
コンタクト領域14,15を形成する（第４図（ａ））。以
下第１の実施例と同じく、ホトレジスト層31被覆，平坦
化，ゲート電極上面の露出、Auめっき層32形成を行う
（第４図（ｂ））。さらにAuめっき層32をマスクにし
て、反応性イオンエッチングによってSiO2膜を除去し、
オーミック金属のAuGeNi23を蒸着し、熱処理を行ってソ
ース電極16およびドレイン電極17を形成すれば（第４図
（ｃ））、寄生抵抗の小さな高性能絶縁ゲート電界効果
トランジスタが完成する。なお本工程において、基板41
の代わりに半絶縁性GaAs基板上に高純度GaAsを生長させ
たものを、さらにゲート絶縁膜42の代わりに該高純度Ga
As層上に連続成長させたｎ型GaAlAs層を用いれば、ｎ型
GaAlAsと高純度GaAsとのヘテロ接合のGaAs側に蓄積され
る２次元電子層のキャリア数をゲート13で制御する電界
効果トランジスタとなる。As an example of the second aspect of the present invention, a case of manufacturing an enhancement type InP insulated gate field effect transistor will be described with reference to FIG. First, CVD SiO 2 is used as a gate insulating film on the semi-insulating InP substrate 41 that also serves as the operating region.
The film 42 is deposited to a thickness of 600Å, and the gate length is 1 μm.
A 0.5 μm thick Mo gate electrode 13 is formed, Si ions are implanted using the gate electrode as a mask, and annealing is performed to n +.
Contact regions 14 and 15 are formed (FIG. 4 (a)). Thereafter, as in the first embodiment, coating of the photoresist layer 31, planarization, exposure of the upper surface of the gate electrode, and formation of the Au plating layer 32 are performed (FIG. 4 (b)). Further, using the Au plating layer 32 as a mask, the SiO 2 film is removed by reactive ion etching,
By depositing AuGeNi23, which is an ohmic metal, and performing heat treatment to form the source electrode 16 and the drain electrode 17 (FIG. 4 (c)), a high-performance insulated gate field effect transistor with a small parasitic resistance is completed. In this step, the substrate 41
Instead of, a high-purity GaAs grown on a semi-insulating GaAs substrate is used instead of the high-purity GaAs instead of the gate insulating film 42.
If an n-type GaAlAs layer continuously grown on the As layer is used,
It becomes a field effect transistor in which the number of carriers in the two-dimensional electron layer accumulated on the GaAs side of the heterojunction of GaAlAs and high-purity GaAs is controlled by the gate 13.
なお、第３図（ａ）から（ｆ）および第４図（ａ）、
（ｂ）で示す工程により、すべて自己整合でn+ソース、
ドレイン、コンタクト領域14,15およびゲート電極13の
上面にAuめっき層32を有するＴ型電極が形成できること
から、第３図（ｇ）および第４図（ｃ）で示すAuめっき
層32をマスクにしてソース、ドレインオーム性金属電極
16,17を形成する方法を採らず通常の位置合わせでソー
ス、ドレイン金属電極を形成する方法を用いてもゲート
抵抗およびソース、ドレイン抵抗の小さい電界効果トラ
ンジスタを製作できる。3 (a) to (f) and FIG. 4 (a),
By the process shown in (b), n + source is self-aligned,
Since the T-type electrode having the Au plating layer 32 can be formed on the upper surfaces of the drain, the contact regions 14 and 15 and the gate electrode 13, the Au plating layer 32 shown in FIGS. 3 (g) and 4 (c) is used as a mask. Source and drain ohmic metal electrode
A field effect transistor having a small gate resistance and a low source / drain resistance can be manufactured by using a method of forming a source / drain metal electrode by a normal alignment without using the method of forming 16, 17.
また以上の各実施例ではAuめっき層を用いたが、同じく
抵抗率の小さいAgめっき層も用いることができる。Further, although the Au plating layer is used in each of the above examples, an Ag plating layer having a similar low resistivity can also be used.
第１図（ａ）〜（ｃ）および第２図（ａ）（ｂ）は従来
の電界効果トランジスタのセルフアラインプロセスの工
程を説明するための図である。第３図（ａ）〜（ｇ）お
よび第４図（ａ）〜（ｃ）は本発明による第１および第
２の発明の各一実施例の工程を説明するための図であ
る。ここで11:半絶縁性基板、12:能動層、13:ゲート電
極、14および15:n+コンタクト領域、16:ソース電極、1
7:ドレイン電極、21:耐熱性ゲート、22:Au層、23:オー
ム性電極金属、31:樹脂層、32:Auめっき層、41:動作域
を兼ねる半絶縁性基板、42:ゲート絶縁膜である。1 (a) to 1 (c) and 2 (a) and 2 (b) are views for explaining steps of a conventional field effect transistor self-alignment process. FIGS. 3 (a) to (g) and FIGS. 4 (a) to (c) are views for explaining the process of each embodiment of the first and second inventions according to the present invention. Where 11: semi-insulating substrate, 12: active layer, 13: gate electrode, 14 and 15: n + contact region, 16: source electrode, 1
7: Drain electrode, 21: Heat resistant gate, 22: Au layer, 23: Ohmic electrode metal, 31: Resin layer, 32: Au plating layer, 41: Semi-insulating substrate that also serves as operating area, 42: Gate insulating film Is.
Claims (2)
能動層上にゲート電極を形成し、該ゲート電極をマスク
として高ドープコンタクト領域を形成した後、表面の平
坦性が増すように絶縁性の樹脂層を全面に被覆し、さら
に該樹脂層を薄化し、前記ゲート電極の上面を露出さ
せ、該露出させたゲート電極の上面にAuあるいはAgめっ
き層を自己整合で形成して、前記樹脂層を除去した後、
前記AuあるいはAgめっき層をマスクとしてソースおよび
ドレイン電極を形成することを特徴とする電界効果トラ
ンジスタの製造方法。1. A flatness of a surface is increased after forming an active layer on a semi-insulating substrate, forming a gate electrode on the active layer, and forming a highly doped contact region using the gate electrode as a mask. So that the entire surface is covered with an insulating resin layer, the resin layer is further thinned, the upper surface of the gate electrode is exposed, and an Au or Ag plating layer is formed on the exposed upper surface of the gate electrode by self-alignment. Then, after removing the resin layer,
A method of manufacturing a field effect transistor, characterized in that source and drain electrodes are formed using the Au or Ag plating layer as a mask.
形成し、該絶縁膜上にゲート電極を形成し、該ゲート電
極をマスクとして高ドープコンタクト領域を形成した
後、表面の平坦性が増すように絶縁性の樹脂層を全面に
被覆し、さらに該樹脂層を薄化し、前記ゲート電極の上
面を露出させ、該露出させたゲート電極の上面にAuある
いはAgめっき層を自己整合で形成して前記樹脂層および
ソース、ドレイン電極形成領域上の前記絶縁膜を除去し
た後、前記AuあるいはAgめっき層をマスクとしてソース
およびドレイン電極を形成することを特徴とする電界効
果トランジスタの製造方法。2. An insulating film is formed on a semi-insulating substrate which also serves as an operating region, a gate electrode is formed on the insulating film, a highly doped contact region is formed using the gate electrode as a mask, and then the surface is flattened. To cover the entire surface with an insulating resin layer, further thin the resin layer to expose the upper surface of the gate electrode, and self-align an Au or Ag plating layer on the exposed upper surface of the gate electrode. And removing the insulating film on the resin layer and the source and drain electrode forming regions, and then forming the source and drain electrodes using the Au or Ag plating layer as a mask. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146928A JPH0783026B2 (en) | 1983-08-11 | 1983-08-11 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146928A JPH0783026B2 (en) | 1983-08-11 | 1983-08-11 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6038884A JPS6038884A (en) | 1985-02-28 |
| JPH0783026B2 true JPH0783026B2 (en) | 1995-09-06 |
Family
ID=15418739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58146928A Expired - Lifetime JPH0783026B2 (en) | 1983-08-11 | 1983-08-11 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783026B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6167272A (en) * | 1984-09-10 | 1986-04-07 | Matsushita Electronics Corp | Manufacture of field effect transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5933882A (en) * | 1982-08-19 | 1984-02-23 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
-
1983
- 1983-08-11 JP JP58146928A patent/JPH0783026B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6038884A (en) | 1985-02-28 |
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