JPH1116925A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a perfect rectangular section in a fine gate electrode having a large aspect ratio for lessening the gate resistance by a method where in the second metallic film is grown in an aperture part from the removed section of the first metallic film and after removing a resist film, the first residual metallic film on a semiconductor substrate is selectively removed. SOLUTION: The first metallic film (Ti film) 2 is formed on a semi-insulating substrate 1 further to form an aperture part 4 of a resist film 3 reaching the Ti film 2. Next, another aperture part 5 is formed by etching away the Ti film 2 exposed in the bottom face of the aperture part 4. Next, a WNi film 6 is grown on the bottom faces of the aperture parts 4, 5 to be buried therein for increasing the thickness of the WNi film 6. Next, the whole body is immersed in Au plating solution so as to grow the second metallic film (Au film) 7 in high electric conductivity on the WNi film 6 assuming the Ti film 2 and the WNi film 6 respectively as a positive electrode and a negative electrode. Finally, the resist film 3 is removed to selectively remove the Ti film 2 only thereby enabling a T type gate to be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing electrodes and wiring of a semiconductor device.

[0002]

2. Description of the Related Art A conventional MESFET (metal-semiconductor junction type field effect transistor: Metal-Semicondu
In order to improve the performance of the gate electrode of the ctor field effect transistor), a method of reducing the gate length as much as possible has been adopted. However, when the gate length is reduced, the cross-sectional area perpendicular to the longitudinal direction of the gate electrode is reduced. Therefore, when a high-frequency signal is input to the gate electrode, the longitudinal resistance (hereinafter referred to as gate resistance) of the gate electrode is large. And ME
This has been a cause of lowering the high frequency limit of the SFET.

In order to improve this, a metal such as Al having excellent electrical conductivity is used as a gate electrode material, and the gate length is reduced to a submicron region using a lift-off process. By increasing the height, a method of securing a cross-sectional area perpendicular to the longitudinal direction of the gate electrode and suppressing an increase in gate resistance due to a reduction in gate length has been taken.

Usually, in the lift-off step, a side wall of an opening of a resist or the like used for patterning is formed in an overhang shape, and a metal film is deposited thereon by depositing or sputtering a metal material. A fine metal pattern is formed on the semiconductor substrate by causing the metal film to be stepped in the side wall portion and then removing the unnecessary metal film deposited on the resist together with the resist.

However, in the vapor deposition or sputtering step, when metal atoms enter the surface of the semiconductor substrate from the overhang-shaped opening, it is inevitable that the metal atoms wrap around to a certain extent. The cross-sectional shape is close to a triangle with a skirt spread on the contact surface side with the substrate. Therefore, simply increasing the thickness of the deposited metal film cannot simultaneously achieve the objects of shortening the gate length and reducing the gate resistance. In order to solve this problem, a structure of a mushroom-shaped gate electrode having a T-shaped cross section (hereinafter, simply referred to as a T-shaped gate) has been proposed.

A conventional method of forming a T-type gate using a vapor deposition method or a sputtering method and its problems will be described with reference to FIGS. As shown in FIG. 5A, the semiconductor substrate 1
In a predetermined position, for example, CVD (Chemical Vapor Deposition: Chem)
An SiO ₂ film 9 is formed by using a method of forming an SiO ₂ film 9 using a first resist film 10 to form an opening 11 reaching the SiO ₂ film 9 in a T-type gate forming region of a semiconductor substrate.
Is provided. Next, as shown by an arrow in FIG. 3B, normal RIE (Reactive Ion Etching) is performed.
g) An opening 12 is formed in the SiO ₂ film 9 by using the first resist film 10 as a mask by a method.

Next, as shown in FIG. 3C, after removing the first resist film 10, a second resist film (image reverse resist film: I / R Resist) for a lift-off process is used.
13 is used to align with the opening 12 of the SiO ₂ film 9 to form an opening 14 having an overhang-type cross-sectional shape. Thereafter, a metal material used for forming a T-type gate is deposited by an evaporation method or a sputtering method as shown by an arrow in FIG.

In this manner, the metal film 15 deposited on the T-type gate forming region and the metal film 16 deposited on the second resist film 13 are cut by the step of the overhang type opening 14. Further, if the image reverse resist film is used, the resist stripping solution easily permeates from the interface between the SiO ₂ film 9 and the resist film 13, and the metal film 16 on the resist film 13 can be easily removed together with the resist film later. There are advantages.

In the deposition of the metal material in the T-type gate formation region, the incident angle of the metal vapor or metal ion beam has a certain spread in the vertical direction of the substrate, and the deposition angle is formed at the corner of the bottom of the opening 12. 5 (c).
The thickness increases while maintaining the cross-sectional shape shown in FIG.

If the thickness of the metal film 15 exceeds the thickness of the SiO ₂ film 9 as shown in FIG.
The mushroom-shaped cross section is formed on the O ₂ film 9, which contributes to the reduction of the gate resistance. At this time, due to the non-uniformity of the deposition rate in the opening 12, the T-type gate 15 shown in FIG. ) 17 as shown in FIG. "S" 17 may increase the gate resistance and at the same time take in the plating solution into the inside thereof, causing corrosion and lowering the reliability of the semiconductor device.

In the above step, the opening 12 of the SiO ₂ film defining the T-type gate formation region on the semiconductor substrate is formed.
And the overhang-type opening 14 for the lift-off process used for forming the T-type gate are aligned by mask alignment. However, at this time, a certain amount of misalignment cannot be avoided. As shown in FIG. 4 (e), the cross-sectional shape of the T-shaped eaves is asymmetric, which has an adverse effect on the design of the semiconductor device. FIG. 4 (f)
FIG. 5 shows the finished state of the T-type gate 15 after the unnecessary metal film 16 has been removed together with the second resist film 13 by a lift-off process.

[0012]

As described above, in the conventional method of manufacturing a semiconductor device, when forming a fine gate electrode, the height of the gate electrode is increased with respect to the gate length (hereinafter referred to as gate electrode). If the gate resistance is reduced, the cross-section of the gate electrode becomes triangular due to wraparound during vapor deposition or sputtering, and the gate length is also increased at the same time.

A similar problem occurs not only in the case of the gate electrode but also in the case of forming an emitter electrode and a base electrode of a bipolar transistor, and in general, a fine wiring having a large aspect ratio for the purpose of reducing the wiring resistance of an integrated circuit. Was.

In the case of a gate electrode, in order to reduce the gate resistance by using a T-type gate structure, it is necessary to completely bury the gate metal in a fine gate electrode forming opening provided in an insulating film on a semiconductor substrate. However, there is a problem that the semiconductor is not designed as expected because "su" is taken into the inside thereof and the eaves of the T-type gate are asymmetric due to misalignment of the resist pattern for the lift-off process. .

The present invention has been made in order to solve the above-mentioned problems. By using a method of embedding a gate metal in the gate electrode forming opening by plating, a fine gate electrode having a large aspect ratio can be obtained. To maintain a perfect rectangular cross section and reduce gate resistance.
Another object of the present invention is to apply a similar method to an emitter electrode and a base electrode of a bipolar transistor and fine wiring having a large aspect ratio.

[0016] In addition, the generation of "su" in the T-type gate structure is eliminated, and a mushroom-shaped T-type gate having excellent symmetry in cross section is formed at a high yield, which greatly contributes to a reduction in gate resistance. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

[0017]

According to a method of manufacturing a semiconductor device of the present invention, a first metal film is formed on a semiconductor substrate, a resist film is formed on the first metal film, and a mask pattern is used. An opening reaching the first metal film is formed in the resist film by using the resist film as a mask, the first metal film forming the bottom surface of the opening is removed, and the removed cross section of the first metal film is plated. A second metal film is grown in the opening by a method, and after removing the resist film, the first metal film remaining on the semiconductor substrate is selectively removed.

The second metal film is grown so as to bury the removed portion of the first metal film on the bottom surface of the opening formed in the resist film and the inside of the opening. Is characterized in that the growth thickness of the metal film does not exceed the sum of the thickness of the first metal film and the thickness of the resist film.

In this way, a thin metal wire having a rectangular cross-sectional shape is formed on a semiconductor substrate regardless of the size of the aspect ratio and is used to form a gate electrode, an emitter electrode, a base electrode, and a fine semiconductor device. The resistance of the wiring can be reduced.

Preferably, the growth thickness of the second metal film exceeds the sum of the thickness of the first metal film and the thickness of the resist film, and the second metal film grown beyond the sum A film is formed in a mushroom shape from the opening on the resist film.

The semiconductor substrate is made of GaAs or another compound semiconductor, and the second metal film is made of a heat-resistant metal that can be grown by plating in addition to WNi.

The semiconductor substrate has an insulating film (including a gate insulating film) formed on the surface of silicon, and the second metal film can be grown by plating, in addition to Au, Cu and Ni. And made of a metal having excellent electric conductivity.

According to the method of manufacturing a semiconductor device of the present invention, a first metal film is formed on a semiconductor substrate, a resist film is formed on the first metal film, and the first film is formed on the resist film by using a mask pattern. An opening reaching the metal film is formed, the first metal film forming the bottom surface of the opening is removed using the resist film as a mask, and a second section is formed in the opening by plating from the removed cross section of the first metal film. Growing a metal film, growing a third metal film on the second metal film by plating, and selectively removing the first metal film remaining on the semiconductor substrate after removing the resist film; It is characterized by.

The second and third metal films are grown so as to bury the removed portion of the first metal film on the bottom surface of the opening formed in the resist film and the inside of the opening. The sum of the growth thicknesses of the first, second and third metal films is equal to the first thickness.
And a thickness not exceeding the sum of the thickness of the metal film and the thickness of the resist film.

According to this method, a thin line made of two layers of metal having a rectangular cross-sectional shape is formed on the semiconductor substrate regardless of the aspect ratio, and is used to form a gate electrode, an emitter electrode, a base electrode and a thin film. The resistance of the fine wiring of the semiconductor device can be reduced.

Preferably, the second and third metal films are grown so as to fill the openings formed in the resist film, and have a growth thickness of the second and third metal films. The sum exceeds the sum of the thickness of the first metal film and the thickness of the resist film, and the third metal film that has grown beyond the sum is mushroom-shaped on the resist film from the opening. It is characterized by being formed in.

The semiconductor substrate is made of GaAs, another compound semiconductor, or silicon having a surface on which an insulating film (including a gate insulating film) is formed. The second metal film is made of WNi or a plating method. The third metal film is made of Au, Cu, Ni
In addition, it is characterized by being made of a metal that can be grown by plating and has higher electrical conductivity than the heat-resistant metal.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1A, an N-type channel region 1a is formed on the surface by ion implantation of, for example, Si.
A first metal film 2 made of, for example, Ti is formed on a semi-insulating GaAs substrate 1 provided with An opening 4 of the resist film reaching the first metal film 2 is formed thereon.

Next, the Ti film 2 exposed at the bottom of the opening 4 of the resist film is removed by RIE using CF ₄ or a mixed gas of CF ₄ and SF ₆ until the channel region 1a on the GaAs substrate is reached. The opening 5 is formed by etching and removing.

Subsequently, as shown in FIG.
The aAs substrate 1 is immersed in a mixed solution of nickel sulfate, sodium tungstate, and sodium citrate, the pH of which is adjusted, for example, with ammonia water, and the Ti plate or carbon plate is used as a positive electrode, and the cross section 5 where the Ti film is removed is used as a negative electrode. WN is formed on the channel region 1a exposed on the bottoms of the openings 4 and 5.
An i film 6 is grown. At this time, the thickness of the WNi film is Ti film 2
And the thickness of the resist film 3.

In this manner, first, a WNi film grows thinly along the surface of the channel region 1a exposed at the bottoms of the openings 4, 5, and after the entire surface is covered with the WNi film,
The thickness of the WNi film is increased so that the openings 4 and 5 are completely buried. Before the thickness of the WNi film reaches the sum of the thicknesses of the Ti film 2 and the resist film 3, the growth of the WNi film is interrupted, and then an Au plating solution comprising a cyanide complex of Au and a sulfurous acid complex (Tanaka as a commercial product) Precious metal, Au-10
0, microfab, or N-Chemcat ECF series), and the Ti plate was used as a positive electrode.
An Au film 7 having high electric conductivity is grown on the WNi film 6 using the film 6 as a negative electrode.

As shown in FIG. 1C, the WNi film 6 and A
If the sum of the thicknesses of the u films 7 exceeds the sum of the thicknesses of the Ti film 2 and the resist film 3, the Au film 7 exceeding the sum of the thicknesses may be used.
Grows in a mushroom shape on the resist film 3. Next, the resist film 3 is removed as shown in FIG.
(E), the first using e.g. NH ₄ F solution
Only the metal film Ti is selectively removed by wet etching. Thus, at a predetermined position on the GaAs substrate,
A T-type gate made of a two-layer metal of WNi and Au can be formed.

The T-type gate thus formed is
As compared with the conventional T-type gate, the symmetry of the cross-sectional shape is higher and the size of the eaves can be controlled accurately. Therefore, as shown by an arrow in FIG.
It can be used as a mask when the source / drain region 1b of the aAs-MESFET is formed in a self-aligned manner.

At this time, the channel portion 1c between the channel region below the gate metal 6 and the ion-implanted source / drain region 1b becomes a series resistance between the source and drain, thereby deteriorating the performance of the GaAs-MESFET. . To avoid this, if the wafer is tilted during the ion implantation and the planetary motion is performed, an inclination angle is generated in the ion implantation, and the channel portion 1c can be minimized.

In addition, a Ga nitride film or the like
Even better results can be obtained by covering the surface of the As substrate and performing ion implantation through the nitride film, and further using the lateral diffusion in the activation heat treatment of impurity ions. An ohmic electrode made of Au / Ge is deposited on the source / drain diffusion region 1b formed as described above, and a heat treatment is performed to complete the GaAs-MESFET.

Here, the role of WNi and Au as the gate metal of the GaAs-MESFET will be described. WN
i is one of the refractory metals, and between GaAs and
It is a material exhibiting good Schottky characteristics necessary for the gate of MESFET. Therefore, the Schottky characteristics are not deteriorated by the impurity ion activation heat treatment performed at about 800 ° C. However, the electric conductivity is smaller than that of a metal such as Au which is usually used as a wiring material.

On the other hand, it is known that, for example, Au has a high electric conductivity but reacts with GaAs, and at the activation heat treatment temperature, not only Schottky characteristics but also alloying progresses and material characteristics are greatly deteriorated.

As shown in FIG. 2E, Au and GaAs
By interposing WNi between the substrate and the substrate, WNi functions as a barrier metal that prevents an alloying reaction between Au and GaAs, and at the same time, a good Schottky characteristic as a GaAs-MESFET is guaranteed. In addition, the gate resistance of the MESFET is greatly reduced by Au formed in a mushroom shape.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a GaAs-MESFET.
2 shows a method of increasing the aspect ratio of a WNi gate electrode without laminating Au on WNi in the manufacturing process, thereby increasing the cross-sectional area of the gate electrode and reducing the gate resistance.

A Ti film 2 is formed on a semi-insulating GaAs substrate 1 having an N-type channel region 1a on the surface by vapor deposition or sputtering, and a thick resist film 3 is coated and patterned. T on the gate electrode formation area
An opening 4 of the resist film 3 having a high aspect ratio reaching the i-film 2 is formed.

Next, the opening 4 of the resist film is formed by RIE until the channel region 1a on the GaAs substrate is reached.
The opening 5 is formed by etching and removing the Ti film 2 at the bottom of FIG.

In the same manner as in the first embodiment, Ti
The WNi film 6 is grown on the channel region 1a exposed from the bottom surface of the openings 4 and 5 from the cross section 5 where the film 2 is removed. At this time, the thickness of the WNi film does not exceed the sum of the thicknesses of the Ti film 2 and the resist film 3. Thus, as shown in FIG. 3A, the openings 4 and 5 having a high aspect ratio are completely filled with the WNi film.

As shown in FIG. 3B, if the resist film 3 and the Ti film 2 are removed, ions are implanted from above using a usual method, and heat treatment is performed, thereby forming a source / drain diffusion layer 1b. If the gate electrode having a high aspect ratio is formed without providing the eaves as described above, the channel portion 1c that becomes the series resistance described with reference to FIG. -MESF
It can be used to form ET. At this time, if sidewalls are provided on the WNi gate, L
It is also possible to adopt a DD (Lightly Doped Drain) structure.

The gate width of GaAs-MESFETs differs greatly depending on the application. The gate width is very large in a single unit or an analog device having a small degree of integration, and the T-type gate structure described in the first embodiment plays an important role. In the device (1), since the gate width is small, even if the gate is not necessarily a T-type gate, the gate resistance value which is practically sufficiently low by using WNi having a single-layer structure having a high aspect ratio as shown in FIG. can get.

As a modification of the second embodiment, WN
When an Au film is laminated on the i film so that the sum of the thicknesses of the WNi film and the Au film does not exceed the sum of the thicknesses of the Ti film 2 and the resist film 3, compared to a single WNi film, Needless to say, the gate resistance is further reduced.

The method of forming a gate electrode having a high aspect ratio according to the above-described second embodiment is not limited to the MESFET, and can be used as a method of forming an emitter and a base electrode of a bipolar transistor made of a compound semiconductor or silicon. . Furthermore, the present invention can also be applied to the case where fine wiring is directly formed on a semi-insulating compound semiconductor substrate.

In addition, as an important application field of the second embodiment, silicon MOS (metal / oxide / semiconductor:
Metal-Oxide-Semiconductor) and compound semiconductor MIS
(Metal / Insulator / Semiconductor: Metal-Insulator-Semicondu
ctor) There is an application to the structure. At this time, since an insulating film exists between the metal electrode and the semiconductor substrate, an alloying reaction between the metal electrode and the semiconductor substrate is avoided, and a material that can be plated such as Au, Cu, or Ni is used as an electrode material. If so, a gate electrode having a single-layer or high-layer structure with a high aspect ratio can be used regardless of reactivity with the base semiconductor substrate.
Needless to say, these are useful not only as gate electrodes of MOS or MIS transistors, but also as fine wiring techniques generally having low wiring resistance.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 4, a silicon substrate on which a gate insulating film is formed is used as a semiconductor substrate. A Ti film 2 is formed on a silicon substrate 1 s having a SiO ₂ film 8 on its surface by vapor deposition or sputtering, and is coated with a resist film 3 and patterned to form a Ti film 2 on a gate electrode formation region. The opening 4 of the resist film 3 which reaches is formed.

Next, by using the RIE method, the Ti film 2 at the bottom of the opening 4 of the resist film is removed by etching until the SiO ₂ film 8 is reached, thereby forming the opening 5 of the Ti film. An Au film 7 is grown on the SiO ₂ film 8 exposed from the bottom surface of the openings 4 and 5 from the cross section 5 where the Ti film 2 has been removed. A
If the sum of the thicknesses of the u films 7 exceeds the sum of the thicknesses of the Ti film 2 and the resist film 3, the Au film 7 exceeding the sum of the thicknesses may be used.
Grows in a mushroom shape on the resist film 3.

In this way, a T-type gate made of a single-layer Au having extremely low gate resistance can be formed on the SiO ₂ film 8 covering the silicon substrate 1s.
At this time, if an intervening heat-resistant metal such as WNi between the SiO ₂ film and the Au, the adhesion is enhanced reliability and SiO ₂ film and Au can be improved.

In the above description, silicon is used as the semiconductor substrate 1s and a SiO ₂ film is used as the insulating film. However, a compound semiconductor substrate is used instead of silicon, and another insulating film such as a SiN film is used instead of the SiO ₂ film. Can be used.

The present invention is not limited to the above embodiment. In the above embodiment, Ti was used as the first metal, but any conductive film suitable as a growth nucleus for the second metal from the plating solution can be used as the first metal in the same manner. . Although the case of electrolytic plating has been described as an example, the second metal can be selectively grown in the opening of the resist by using an electroless plating solution having the first metal as a growth nucleus.

The case where WNi is used as the second metal and Au is used as the third metal has been described. In addition, if plating is possible and selective etching with the first metal is possible, other methods may be used. High melting point metal or metal having high electric conductivity can be used as the second and third metals. In addition, various modifications can be made without departing from the scope of the present invention.

[0055]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the opening formed in the resist film is buried by using the plating method, so that the “semiconductor” in the T-type gate, which has been a problem in the prior art, is formed. "Can be prevented. Also,
Since a T-type gate can be formed in a single photoresist process, the T
Asymmetrical formation of the eaves of the mold gate can be avoided.

Further, if this method is used, plating is performed according to the dimensions of the bottom of the opening that defines the gate length.
The rectangular cross-sectional shape is maintained irrespective of the aspect ratio of the opening, and the gate resistance can be significantly reduced even when the gate is not necessarily a T-shaped gate.

The method of the present invention is not limited to the formation of the gate electrode of the MESFET, but also the formation of the MOS type and the MIS type gate electrodes, the formation of the emitter and base electrodes of the bipolar transistor, the formation of fine wiring on the insulating compound semiconductor, Further, it can be widely used as a fine wiring method of a semiconductor device on an insulating film.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a continuation of the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 5 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a process sectional view showing a continuation of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate 1a ... Channel layer 1b ... Source / drain diffusion layer 1c ... Channel part which becomes a series resistance 1s ... Silicon substrate 2 ... First metal film Ti 3 ... Resist film 4 ... Resist film opening 5 ... removal section 6 ... of the second metal film WNi 7 ... mushroom to the third metal film Au 8, 9 grown ... SiO ₂ film 10 ... first resist film 11 ... first the first metal film Ti Opening of resist film 12 Opening of SiO ₂ film 13 Second resist film 14 Overhanging opening of second resist film 15 Gate metal 16 Gate metal on second resist film 17 … “Su” taken into the gate metal

Claims (10)

[Claims] A first metal film formed on the semiconductor substrate; a resist film formed on the first metal film; and an opening reaching the first metal film in the resist film using a mask pattern. Forming a portion, removing the first metal film forming the bottom surface of the opening using the resist film as a mask, and forming a second metal in the opening by plating from the removed cross section of the first metal film. A method of manufacturing a semiconductor device, comprising: growing a film; removing the resist film; and selectively removing the first metal film remaining on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the second metal film is grown to fill a portion of the bottom surface of the opening formed in the resist film where the first metal film is removed and the inside of the opening. 2. The semiconductor device according to claim 1, wherein a growth thickness of said second metal film does not exceed a sum of a thickness of said first metal film and a thickness of a resist film. Production method. 3. The second metal film is grown so as to fill a portion of the bottom surface of the opening formed in the resist film where the first metal film is removed and the inside of the opening. The growth thickness of the second metal film exceeds the sum of the thickness of the first metal film and the thickness of the resist film, and the second metal film grown over the sum is: 2. The method according to claim 1, wherein a mushroom is formed on the resist film from the opening. 4. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a compound semiconductor containing GaAs, and the second metal film is made of a heat-resistant metal containing WNi that can be grown by a plating method. 3. The method for manufacturing a semiconductor device according to any one of 3. 5. The semiconductor substrate according to claim 1, wherein an insulating film is formed on a surface of silicon, and the second metal film is
4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is made of a metal having excellent electrical conductivity including Au, Cu, and Ni which can be grown by plating. 6. A first metal film is formed on a semiconductor substrate, a resist film is formed on the first metal film, and an opening reaching the first metal film is formed in the resist film by using a mask pattern. Forming a portion, removing the first metal film forming the bottom surface of the opening using the resist film as a mask, and forming a second metal in the opening by plating from the removed cross section of the first metal film. Growing a film, growing a third metal film on the second metal film by plating, and selectively removing the first metal film remaining on the semiconductor substrate after removing the resist film. A method of manufacturing a semiconductor device. 7. The second and third metal films are grown so as to fill a portion of the bottom surface of the opening formed in the resist film where the first metal film is removed and the inside of the opening. And the sum of the growth thicknesses of the second and third metal films does not exceed the sum of the thickness of the first metal film and the thickness of the resist film. 7. The method for manufacturing a semiconductor device according to claim 6, wherein 8. The second and third metal films are grown so as to bury the removed portion of the first metal film on the bottom surface of the opening and the inside of the opening formed in the resist film. Wherein the sum of the growth thicknesses of the second and third metal films exceeds the sum of the thickness of the first metal film and the thickness of the resist film. 7. The method according to claim 6, wherein the third metal film that has grown beyond the opening is formed in a mushroom shape on the resist film from the opening. 9. The semiconductor substrate is made of a compound semiconductor containing GaAs, the second metal film is made of a heat-resistant metal containing WNi that can be grown by a plating method, and
Au, Cu, N that can be grown by plating
9. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is made of a metal having higher electrical conductivity than the heat-resistant metal containing i. 10. The semiconductor substrate according to claim 1, wherein an insulating film is formed on a surface of silicon, and the second metal film is formed of WN.
i is a metal having excellent adhesion to the insulating film containing i, and the third metal is Au, C which can be grown by plating.
9. The semiconductor device according to claim 7, comprising a metal having higher electrical conductivity than the heat-resistant metal containing u and Ni.
5. A method for manufacturing a semiconductor device according to any one of the above.