JPS61144880A - Production of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the source and gate resistance by a method wherein an active layer and a gate electrode on a semiconductor substrate, and a contact region is formed with the electrode used as a mask, the whole surface is coated with a metallic film, Au is plated on the gate electrode which has been coated with resin and made to a film and exposed, and then unnecessary metallic film is removed. CONSTITUTION:Si ion is injected onto a GaAs substrate 11 to form an N-type active layer 12, the WSi gate 13 is formed. Si ion is injected with the gate 13 used as a mask to form a n<+> contact regions 14 and 15. A Ni film 20 is evaporated on the whole surface. The hole surface is coated with a photo-resist layer 21, and the layer is uniformly thinned to expose the upper surface of the gate 13. An Au plating layer 22 is formed on the upper surface, and then, the photo-resist layer 21 and the Ni film 20 outside of the gate 13 are removed to complete the gate electrode. An AuGeNi 19 is evaporated with the layer 22 used as a mask to form a source electrode 16, drain electrode 17, thereby completing an FET.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a field effect transistor with low parasitic resistance. (Prior art and its problems) GaAs Schottky gate field effect transistors have been increasingly integrated in recent years with the aim of producing high-speed ICs. This is a self-line process for reducing the source resistance, which is important in the process, and this will be explained using FIG. To form a gate using an alloy, donor ions are implanted into the source and drain regions using the gate electrode 13 as a mask, and annealing is performed to form the n-middle region 1.
Then, a source electrode 16 and a drain electrode 17 are formed (see FIG. 3(b)).
C)) process. According to such a process, the source resistance can be significantly reduced. However, the source and drain electrodes are usually formed with metal fittings, and the gate end
) Since it cannot be brought close to the edge of the n0 region, there is no limit to the miniaturization of the element, and as the gate is miniaturized, the source resistance increases to a size that cannot be ignored. Furthermore, in this case a refractory gate metal, for example TiW-? W
Since the resistivity of silicide is relatively high, the gate resistance also increases significantly. A process that improved this point was published by the applicant in JP-A-57-152168-JP-A-FM357-1.
52166. For example, as shown in FIG. 4, ions are implanted using the electrode on which the Au layer 18 is deposited on the heat-resistant gate 13 as a mask, and annealing is performed to form an n+ region 14t15 (FIG. 4(a)). This is a process in which the source 16 and drain electrodes 17 are deposited and formed using the AU layer 18 as a mask (FIG. 4(b)). Note that 19 is an ohmic electrode metal deposited on the AU layer. According to this process, the source resistance and gate resistance can certainly be reduced to extremely low values. However, in this process, since annealing is performed with Au deposited on the heat-resistant metal, the thickness of the heat-resistant metal and the annealing conditions must be optimized to prevent Au from diffusing and reacting with GaAs. There is a need.

Furthermore, since the TfiSi gate is formed by side etching of a heat-resistant metal on the side of the TfiSi gate in this process, there is also the disadvantage that the actual gate length cannot be observed during the process.

(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a field effect transistor with extremely low source resistance and gate resistance, which eliminates the above-mentioned disadvantages with an improved process.

(Structure of the Invention) According to the present invention, after forming an active layer on a semi-insulating substrate,
After forming a gate electrode on the active layer and forming a highly doped contact region using the gate electrode as a mask if necessary, a metal film for power supply is deposited on the entire surface, and then the surface flatness is increased. The entire surface is covered with an insulating resin layer, the resin layer is further thinned, the upper surface of the gate electrode is exposed, and the exposed upper surface of the gate electrode is coated with Au or Ag.
A method for manufacturing a field effect transistor is obtained, which comprises removing the resin layer and the metal film outside the gate after forming the plating layer.

Furthermore, according to the present invention, an insulating film is formed on a semi-insulating substrate that also serves as an operating region, a gate electrode is formed on the insulating film,
After forming a highly doped contact region using the gate electrode as a mask, a metal film for power supply is deposited on the entire surface, then an insulating resin layer is coated on the entire surface to increase the flatness of the surface, and then the resin layer is coated on the entire surface. After thinning the layer to expose the upper surface of the gate electrode, and forming a layer containing U or Ag on the exposed upper surface of the gate electrode, removing the resin layer and the metal film outside the gate. A method for manufacturing a field effect transistor is obtained.

(Detailed Description of Configuration) The present invention will be described in detail below with reference to one embodiment.

As an embodiment of the first invention, a case where a GaAs gate field effect transistor is fabricated will be described with reference to FIG. First, on a semi-insulating GaAs substrate
83 ions with an implantation energy of 50 keVp, for example.
)' -5fj/(2X 10"an-" injection L, s
o.

C. for 10 minutes to form an n-type active layer 12 (FIG. 1(2)). Next, a WS i heat-resistant film 13 having a gate length of 0.5 μm and a thickness of 0.6 μm is formed by dry etching. (Figure 1 (b). This WS
Using the i gate as a mask, implant Si ions at, for example, an energy of 100 keV and a dose of I
m-3 on both sides of the gate and briefly annealed at 950°C for 2 seconds to form n+ contact regions 14115.
(Fig. 4(C)). Next, a Ni film 20 having a thickness of 0.1 μm is deposited on the entire surface of the wafer as the amount of power supplied during plating (FIG. 1(d)). Next, the entire surface is covered with a resin layer, such as a photoresist layer 31, which has a flat surface and is easy to remove (FIG. 1(e)). In other words, the photoresist layer is made thinner in the gate area than in other areas.

This can be easily achieved, for example, by applying a positive photoresist to a thickness of 1 μm and baking it at a high temperature to make it fluid. Next, the resist is uniformly thinned from above by oxygen reactive ion etching to expose only the upper surface of the W8 i gate on which Ni is deposited (FIG. 1(f)). An Au plated layer 22 is formed to a thickness of 0.4 μm on the exposed upper surface of the gate (ω in FIG. 1). Here, the Ni film 20 serves as a current supply path during plating and also serves as a WS
It also has the effect of improving the adhesion of plating onto i. At this time, as a result of the plating layer growing laterally to the same extent as the thickness, T
A mold electrode is formed. Next, by removing the photoresist layer and the Ni film 20 outside the gate, the gate electrode is completed (
Figure 1 (h)). Furthermore, using the Au plating layer 22 as a mask, geomic metal AuGeNi is applied from above.
A field effect transistor is completed by vapor depositing 9 and performing heat treatment to form a source electrode 16 and a drain pole 17. (Figure 1(i)).

As is clear from the above, in the manufacturing method according to the present invention,
Microfabrication using lithography technology only needs to be performed once to form the gate electrode, and precise alignment may not be necessary at this time. Field effect transistors with small microstructures can be manufactured. In other words, in the above example, the gate length is 0
．． In contrast to 5 μm, for the actual wiring portion of the gate electrode, a 1.3 μm long electrode made of Au having low resistivity can be used, and the gate resistance becomes extremely small. Furthermore, the source-gate distance is as short as 0.4 μm, and the source resistance is also extremely low.

Note that the source-gate distance can be controlled by the amount of Au plating grown. Furthermore, in the manufacturing method of the present invention, since the annealing step can be performed before forming the Au layer, the permissible temperature range and time range for annealing can be widened.

The case where the n+ contact region is formed by ion implantation has been described above, but it is also possible to use a low+ contact layer by epitaxial growth, or if the n+ contact region is not formed, the normal structure is obtained, but the source-
Field-effect transistors with short Schottky gates between gates and between gates and drains can be easily manufactured using a self-line process. In this case as well, the effect of reducing parasitic resistance as described above can be achieved. Further, it goes without saying that the source and drain electrodes 16y17 can be formed by a normal alignment method.

A case where an enhancement type InP insulated gate field effect transistor is fabricated as an embodiment of the second aspect of the present invention will be described with reference to FIG.

First, on a semi-insulating InP substrate 23 which also serves as an operating region, a CVD Sin film 24 as a gate insulating film is deposited to a thickness of 600×, and the gate length is 1 μm and the thickness is 0.5 μm.
A single pole 13 of W of m is formed, SN ions are implanted using the gate electrode as a mask, and annealing is performed to form an n+ contact region 14y15 (FIG. 2(a)).

Thereafter, in the same manner as in the first embodiment, a Ti film 20 with a thickness of 500X is deposited for power supply, a photoresist layer 21 is coated, planarized, the upper surface of the gate electrode is exposed, and a human U-cutting layer 22 is formed (second Figure (b)).

Next, the photoresist layer 21 and Ti[20
By removing , the gate electrode is completed. (Figure 2 (C))
. Furthermore, if the 8i0z film is removed by a normal resist process and the ohmic metal uGeNi is deposited, and then heat treated to form the source electrode 16 and drain electrode 17 (Fig. 2(d)), high performance with low parasitic resistance can be achieved. An insulated gate field effect transistor is completed. Although the enhancement-type transistor has been described above, the depletion-type insulated gate field effect transistor has an n-type InP active layer formed on a semi-insulating InP substrate and a gate electrode formed on top of the n-type InP active layer via a gate insulating film. It is clear that this method is also effective in manufacturing transistors. ,! In this step, high-purity GaAs was grown on a semi-insulating GaAs substrate in place of the substrate 23, and further, in place of the gate insulating film 42, high-purity GaAs was grown on the high-purity GaAs layer. If a continuously grown n-type or undoped GaAIAs layer is used, the number of carriers in the two-dimensional electron layer accumulated on the GaAs side of the heterojunction between GaAlAs and high-purity GaAs can be controlled by the gate 13. It is expressed as a field effect transistor.

Furthermore, although an Au plating layer was used in each of the above embodiments, an Ag plating layer having a low resistivity may also be used.

(Effects of the Invention) As described above, according to the present invention, a field effect transistor with low parasitic resistance can be manufactured, and it is possible to promote high performance of microwave low noise and high output devices. Furthermore, the manufacturing method of the present invention is effective for reducing the resistance of the electrodes of semiconductor devices, not just the gate electrodes of field effect transistors.

[Brief explanation of drawings]

FIGS. 3(,) to (C) and FIGS. 4(,)(b) are diagrams for explaining the steps of the conventional self-line process for field effect transistors. FIGS. 1(a)-(i) and FIGS. 2(a)-(d) are diagrams for explaining the steps of each embodiment of the first and second inventions according to the present invention. Here, 1 is a semi-insulating substrate, 12: active layer, 13: gate electrode, 14 and 15: n + contact region, 16: source electrode, 17: drain electrode, 18: Au layer,
19: Ohmic electrode metal, 20: Power supply metal film, 21:
Resin layer, 22: Au plated layer, 23: Semi-insulating substrate which also serves as an operating region, 24: Gate insulating film. Figure 1 (e) Figure 1 Figure 2 Figure 3 (a) (b) (C) Figure 4 (a) (b)

Claims (1)

[Claims] 1. After forming an active layer on a semi-insulating substrate, forming a gate electrode on the active layer, and forming a highly doped contact region using the gate electrode as a mask if necessary. , depositing a metal film for power supply over the entire surface, then covering the entire surface with an insulating resin layer to increase the flatness of the surface, and further thinning the resin layer to expose the upper surface of the gate electrode, A method for manufacturing a field effect transistor, comprising forming an Au or Ag plating layer on the exposed upper surface of the gate electrode, and then removing the resin layer and the metal film outside the gate. 2. Form an insulating film on a semi-insulating substrate that also serves as the operating area,
After forming a gate electrode on the insulating film and forming a highly doped contact region using the gate electrode as a mask, a metal film for power supply is deposited on the entire surface, and then an insulating film is formed to increase the flatness of the surface. After covering the entire surface with a resin layer, thinning the resin layer to expose the upper surface of the gate electrode, and forming an Au or Ag plating layer on the exposed upper surface of the gate electrode, the resin layer and the outside of the gate are coated. A method for manufacturing a field effect transistor, comprising removing a metal film.