JPS62185377A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET which improves a gate withstanding voltage by forming N<+> type layers for source/drain by twice with respect to a gate elec trode in a self-alignment. CONSTITUTION:An N-type active layer 2 is formed by ion implanting on a semi-insulating GaAs substrate 1, and a gate electrode 3 of refractory metal such as TiW is formed. It is covered with a CVD-SiO2 film 4A of approx. 150Angstrom thick, and ion implanted to form N<+> type source/drain layer 5A. It is again covered with a CVD-SiO2 film 4B, films 4B, 4A are allowed to remain on the side of the electrode 3 by RIE, and ion implanted to form an N<+> type layer 5B on the electrode 3 in a self-alignment. Source/drain electrodes are attached by heat treating to complete a transistor. Since the impurity density of the layer 5A is lower than that of the layer 5B, a gate withstanding voltage is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a field effect transistor.

[Conventional technology]

Field-effect transistors (hereinafter referred to as GaAs-FET) that use gallium arsenide as a semiconductor material have recently been developed with various device structures, with the aim of achieving higher performance and higher uniformity.
A manufacturing method is proposed. They are mainly being considered as elements for integrated circuits, and among them, ion implantation technology and manufacturing methods using heat-resistant gate metals are also important technologies.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a field effect transistor.

First, as shown in FIG. 2(a), an n-type impurity is ion-implanted onto a semi-insulating GaAs substrate 1 to form an active layer 2.Next, as shown in FIG. 2(b), an active layer 2 is formed on the entire surface. 1'iW,
After depositing Wsi, etc., the gate electrode 3 is formed by patterning.Next, as shown in FIG. - Dray> - Form an n'-type impurity layer 5 that will become an electrode.

This n+ type impurity layer 5 is formed in self-alignment with the D1- electrode 3.

[The problem that the invention attempts to solve]

The above-mentioned method for manufacturing GaAs-F F, T is a very effective manufacturing method that has simple steps and can reduce source resistance. However, the biggest drawback is that the source/drain region and the gate electrode [i3 are very close to each other, resulting in a low gate breakdown voltage.

Usually 1. With the manufacturing method described in L, the gate breakdown voltage is only about 5 to 6 cm. Therefore, the gate breakdown voltage and the source
Although this manufacturing method is excellent for devices that do not require a drain breakdown voltage, this manufacturing method cannot be used for devices that require a breakdown voltage of at least 15 to 20 V, such as high-power FETs.

An object of the present invention is to provide a method for manufacturing a field effect transistor with improved gate breakdown voltage.

Means for Solving Problems] The method for manufacturing a field effect transistor of the present invention provides
A step of forming a gate electrode on the semi-insulating semiconductor lambda plate on which a type active layer is formed, and forming a first insulating film on the entire surface including the electrode. forming a first n-type impurity layer on the semiconductor substrate including the active layer by ion-implanting n-type impurities using a mask, and forming a second insulating film on the first insulating film; A step of leaving first and second insulating films only on the side surfaces of the gate electrode by a positional etching method, and ion implantation of n-type impurities using the gate electrode and the first and second insulating films on the side surfaces as masks. and deposit a second n+ layer on the semiconductor substrate including the active layer.
It is constructed in conjunction with the step of forming a type impurity layer.

〔Example〕

Next, embodiments of the present invention will be described in detail using the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), an n-type impurity is ion-implanted onto a semi-insulating GaAs substrate 1 to selectively form an active layer 2. As shown in FIG. Subsequently, a heat-resistant metal such as TiW or WSi is deposited and patterned to form the gate electrode 3.

Next, as shown in FIG. 1(b), a first insulating film 4A made of a 5i02 film formed by CVD and having a thickness of about 1,500 layers is formed.
is formed on the entire surface. Next, an n-type impurity layer 5 is ion-implanted to form a first n+-type impurity layer 5 that will become the source/drain region.
Form A. In this case, game? The -electrode 3 serves as a mask, and the n+ type impurity layer 5A is formed in self-alignment with the gate electrode 3.

Next, as shown in FIG. 1(c), after forming a second insulating film 4B made of a SiO□ film by CVD method or the like, anisotropic etching/soching is performed by reactive ion etching method to form a second insulating film 4B. 1. The second insulating film is removed.

At this time, the first and second insulating films 4A and 4B remain on the side surfaces of the electrodes 1 to 3. In this state, n-type impurity ions are implanted to form a second n+-type impurity /fi5B.

In this case as well, the second n+ type impurity layer 5B is the gate electrode 3.
is formed by self-alignment.

Thereafter, heat treatment is performed to form source/drain ohmic electrodes, wiring electrodes, etc., thereby completing the field effect transistor.

In the field effect transistor formed in this way, the first n+ type impurity layer 5 adjacent to the gate electrode 3
Since the impurity concentration of A is lower than the concentration of the second n-type impurity layer 5B, the gate breakdown voltage is improved.

〔Effect of the invention〕

As explained above, in the present invention, the n-type impurity layer, which becomes the source/drain region, is self-aligned with the gate electrode.
By forming the layers in multiple steps, there is an effect that a field effect I transistor with improved gate breakdown voltage can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) illustrate an embodiment of the present invention.
), sectional view of the semiconductor chip shown in Section 5 IIIα, 2nd
Figures (a) to (c) are cross-sectional views of a semiconductor chip shown in step J for explaining a conventional method of manufacturing a field effect transistor. 1... Semi-insulating GaAs substrate, 2... Active layer, 3...
・Gate electrode, =l A...first insulating film, 4B...
-Second insulating film, 5...n+ type impurity layer, 5A...
First n+ type impurity layer, 5B... second n+ type impurity layer. Figure f

Claims (1)

[Claims] A step of forming a gate electrode on a semi-insulating semiconductor substrate with an n-type active layer formed on the surface, and after forming a first insulating film on the entire surface including the gate electrode, using the gate electrode as a mask, n-type impurity is added. forming a first n^+ type impurity layer on the semiconductor substrate including the active layer by ion-implanting; and anisotropic etching after forming a second insulating film on the first insulating film. a step of leaving first and second insulating films only on the side surfaces of the gate electrode by a method; and a step of ion-implanting n-type impurities using the gate electrode and the first and second insulating films on the side surfaces as masks to remove the active material. A second n^ on a semiconductor substrate containing a layer
1. A method for manufacturing a field effect transistor, comprising the step of forming a +-type impurity layer.