JPH0281439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the degradation of a transconductance by a method wherein polycrystalline silicon, high melting point metal or its silicide is used as the material of a member on the side wall of a gate electrode which is a part of an ion implantation mask for obtaining an LDD structure and, further, the material is left on the side wall of the gate electrode. CONSTITUTION:After a field oxide film 2 is selectively formed on the main surface of a p-type silicon substrate 1, a gate electrode 3 is formed. After an insulating film 5 is formed on the surfaces of the gate electrode 3 and the substrate 1, a polycrystalline silicon film 6 is formed on it so as to cover the whole surface of the substrate 1. The polycrystalline silicon film 6 is so removed as to be left on the side wall of the gate electrode 3 by anisotropic etching. Arsenic or phosphorus ions are implanted with a relatively high concentration by using the gate electrode 3 and the remaining part of the polycrystalline silicon film as a mask. Even if hot carriers are injected into the gate side wall part on the drain side, they can be drained out of a drain electrode.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing an insulated gate (MOS) field effect semiconductor device having a doped drain (hereinafter referred to as LDD) structure.

[Conventional technology]

FIG. 2 (al to (fl) are cross-sectional views showing the manufacturing process of a conventional semiconductor device. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is a gate insulating film, 5 is an insulating film, 6.6a is a polycrystalline silicon film, 7.7a is a thermal oxide film, 8a is an n-type source region, 8
b is an n° type source region, 9a is an n- type drain region, 9
b is an n-type drain region 10 is a CVD oxide film, 11a
, 11b are contact holes, and 12 is an aluminum wiring layer.

Next, the manufacturing method will be explained.

After selectively forming a field oxide film 2 on the main surface of the p-type silicon substrate 1, an oxide film to be a gate insulating film is deposited in a region surrounded by the field oxide film 2, and a gate electrode is formed on it. The desired polycrystalline silicon is deposited and patterned to form the gate electrode 3. Next, using the gate electrode 3 as a mask, excess oxide film is removed to form a gate insulating film 4. Then, using the gate electrode 3 and gate insulating film 4 as masks, a relatively low concentration (1016 to 10"cm-
') ion implantation of arsenic or phosphorus (Figure 2(a)
).

Next, an insulating film 5 with a thickness of 400 μm is formed on the gate electrode 3 and the surface of the substrate 1, and a polycrystalline silicon film 6 with a thickness of 0.5 μm is formed thereon so as to cover the entire substrate. The thickness of this polycrystalline silicon film 6 is n
This is an important factor that determines the width of the −61 regions 8a and 9a.

Since the polycrystalline silicon film 6 has good step coverage with respect to the shape of the gate electrode 3, a virtually vertical wall can be obtained.A zero-order thermal oxide film 7 is formed on the polycrystalline silicon film 6 to a thickness of 500 nm. do. This oxide film 7 is also
This is an important factor that determines the width of the source/drain n-1f, 5 regions 8a, 9a (FIG. 2(b)).

Next, the thermal oxide film 7 is removed by anisotropic etching so that it remains only on the sidewalls of the polycrystalline silicon film 6 corresponding to the shape of the gate electrode 3 (FIG. 2(C)).

Next, using the remaining portion 7a of the thermal oxide film as a mask, the polycrystalline silicon film 6 is anisotropically etched so that it remains only on the side walls of the gate electrode 3. At this time, thermal oxidation 1! Since J7a prevents side etching of the polycrystalline silicon film 6, the width of the remaining portion 6a of the polycrystalline silicon film is actually approximately the same as the thickness of the polycrystalline silicon film 6. Using the gate electrode 3 and the polycrystalline silicon film 6a as a mask, arsenic or phosphorus ions are implanted at a relatively high intensity (10'' to 10''am-') (FIG. 2(d)).

Next, the polycrystalline silicon film 6a is removed by isotropic etching using a furosan-based gas, a halogen-based gas, or an alkaline solution (eg, KOH). At this time, the thermal oxide film 7a is also lifted off. Thereafter, the layer produced by the two ion implantations is activated by heat treatment. That is, an n-type source region 8a and an adjacent n-type source region 8b, n
A - type drain region 9a and an adjacent n-type drain region 9b are formed (FIG. 4(e)).

Finally, a CVD oxide film 10 is deposited over the entire surface of the substrate, contact holes Ila and llb are opened, and after aluminum is deposited over the entire surface, an aluminum wiring layer 12 is formed using, for example, photoresist. As described above, an MO3 semiconductor device having an LDD structure is completed (FIG. 2(f)).

[Problem to be solved by the invention]

In conventional semiconductor device manufacturing methods, the polycrystalline silicon film formed on the gate sidewalls is removed as a mask for ion implantation to obtain the LDD structure, so when the device is completed, the gate sidewalls are only an insulating film. It is formed of. For this reason, during MO3FET operation, hot carriers are injected into the insulating film on the sidewall of the gate on the drain side, which depletes the low concentration n-type (n-type) region, increases the resistance of this n-type region, and increases the resistance of the MOSFET. There was a problem that the transconductance deteriorated.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a manufacturing method for obtaining an MO3 field effect semiconductor device in which the transconductance does not decrease even when real carriers are injected into the gate sidewall. purpose.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, polycrystalline silicon, a high melting point metal, or a silicide thereof is used as a member of the side wall of the gate electrode, which is a part of an ion implantation mask for obtaining an LDD structure, and this is further applied to the gate electrode. It was left on the side wall.

[Effect]

In this invention, since polycrystalline silicon, high melting point metal, or its silicide is left on the sidewall of the gate, even if true carriers are injected during operation of the MOSFET, they can be extracted from the drain electrode. A decrease in transconductance can be prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 (a), (b), (C1, (d), (e)
1(d) is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 1(d) is a top plan view of the device of FIG. 1+d). In the figure, the same reference numerals as in FIG. 2 indicate the same parts, and 13 is a photoresist.

Next, the manufacturing method will be explained.

After selectively forming a field oxide film 2 on the main surface of a p-type silicon substrate 1, an oxide film to become a gate insulating film is formed in a region surrounded by the field oxide film, and an oxide film to become a gate electrode is formed thereon. A gate electrode 3 is formed by depositing polycrystalline silicon and patterning it. Excess oxide film is removed using gate electrode 3 as a mask, and gate insulating film 4 is formed.

Then, using the gate electrode 3 and gate insulating film 4 as masks, arsenic or phosphorus ions at a relatively low concentration (10" to 10"cm-") are implanted (FIG. 1(a)).

Next, an insulating film 5 with a thickness of 400 μm is formed on the gate electrode 3 and the surface of the substrate 1, and a polycrystalline silicon film 6 with a thickness of 0.5 μm is formed thereon so as to cover the entire substrate. The thickness of this polycrystalline silicon film 6 is n
This is an important factor that determines the width of −jI regions 8a and 9a. Since the polycrystalline silicon film 6 has good step coverage with respect to the shape of the gate electrode 3, virtually vertical walls are obtained (FIG. 1(b)).

Next, polycrystalline silicon film 6 is removed by anisotropic etching so that it remains only on the side walls of gate electrode 3. Using the gate electrode 3 and the remaining portion 6a of the polycrystalline silicon film as a mask, a relatively high concentration (lO"~10"am-
') ion implantation of arsenic or phosphorus. Next, using the photoresist 13 as a mask to prevent short circuits between the source and drain, polycrystalline silicon film 6a on the side wall of the gate electrode on the field oxide film 2 except over the source and drain regions (see FIG. 1(d), shaded) part) is removed by isotropic etching using a fluorine gas, a halogen gas, or an alkaline solution (eg KOH).

Thereafter, the layers produced by the two ion implantations are activated by heat treatment to form an n-type source region 8a, an n° source region 8b, an n-type drain region 9a, and an n° todrain region 9b. Next, a CVD oxide film 10 is deposited on the entire surface of the substrate, and contact holes 11a and 11b are opened, which share the polycrystalline silicon film 6a on the gate sidewall, the n9 type source region 8b, and the n' type drain region 9b. Aluminum is deposited thereon, and an aluminum wiring layer 12 is formed using photoresist (FIG. 1(e)). In this way, an MO3 type semiconductor device having an LDD structure is completed.

In this way, in this example, the polycrystalline silicon film 6a formed on the sidewalls of the gate electrode 3 is left on the source/drain regions as a mask for ion implantation to obtain the LDD structure. Even if hot carriers are injected into the gate sidewall on the drain side, they can be extracted from the drain electrode, so the resistance of the n-type region does not increase, and deterioration of transconductance can be prevented.

In the above embodiment, polycrystalline silicon is used for the member 6a left on the gate side wall portion and the gate electrode 3, but a conductive layer made of a high melting point metal or its silicide may also be used.

〔Effect of the invention〕

As described above, according to the present invention, by using the polycrystalline silicon film on the side wall of the gate electrode, which is a mask for ion implantation for forming an LDD structure, as the drain electrode, hot carriers can be injected into the side wall of the gate electrode. This can be extracted, which has the effect of preventing deterioration of the transconductance of the MOSFET.

[Brief explanation of the drawing]

Figure 1 (al, (b), (C1, (dl, +e)
1(d) is a plan view of the device in FIG. 1(dl) viewed from above, and FIG. 2(al to (f) is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, l is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is a gate insulating film, 5 is a thermal oxide film, 6, 6a is a polycrystalline silicon film, 7 and 7a are thermal oxide films, 8a is an n-type source region, 8b is an n-type source region, 9a is an n-type drain region, 9b is an n°-type drain region 1O is CVD oxidation The films, lla and llb are contact holes (shared contacts) 12 are aluminum wiring,
13 is a photoresist. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A first step of forming a gate electrode made of a first insulating film and a first conductive layer on a first conductivity type semiconductor substrate, and using the gate electrode as a mask, forming a second gate electrode in the semiconductor substrate.
a second step of forming a conductive type lightly doped region; a third step of forming a second insulating film on the gate electrode and the impurity doped region; and forming a second conductive layer on the entire surface. and a fourth step of leaving the second conductive layer only on the side walls of the gate electrode and removing the other portions by anisotropic etching, and using the gate electrode and the second conductive layer as a mask, a fifth step of forming a second conductive type heavily doped region in the semiconductor substrate; and a sixth step of selectively removing a portion of the second conductive layer.
a seventh step of forming a third insulating film on the entire surface and opening a contact hole penetrating the insulating film and having the impurity doped region and the second conductive layer in common; A method for manufacturing a semiconductor device, comprising an eighth step of forming a metal film and forming source/drain wiring by patterning.