KR0175366B1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- KR0175366B1 KR0175366B1 KR1019950035205A KR19950035205A KR0175366B1 KR 0175366 B1 KR0175366 B1 KR 0175366B1 KR 1019950035205 A KR1019950035205 A KR 1019950035205A KR 19950035205 A KR19950035205 A KR 19950035205A KR 0175366 B1 KR0175366 B1 KR 0175366B1
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- oxide film
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- oxide
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- polysilicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 43
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000005192 partition Methods 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- BSJZCDKNFVVVBW-UHFFFAOYSA-N hydrobromide hydrofluoride Chemical compound F.Br BSJZCDKNFVVVBW-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
본 발명은 반도체 장치 및 그 제조 방법에 관한 것으로서, 폴리실리콘을 두 단계로 나누어서 적층하여 패터닝하는 방법으로 하여 역 'T'자 형의 게이트를 형성함으로써, 게이트의 전기장에 의하여 핫 캐리어 현상이 감소하고, 소스-드레인 영역과 게이트 산화막과의 계면 사이에 전자가 모이게 되어, 소스 저항과 드레인 저항을 감소하도록 하는 효과를 가지는 반도체 장치 및 그 제조 방법이다. 또한 질화막 패턴을 이용하여 선택적으로 채널 이온 주입을 하여 전자의 이동도를 높이고, 포겟 이온주입으로 쇼트 채널 효과를 방지하는 효과가 있으며, 한편으로는, 역 'T'자 형의 게이트를 형성하는 데에, 종래의 폴리실리콘격벽을 이용하지 않고, 폴리실리콘층을 형성하고, 질화막을 제거할 때 함께 식각하여 패터닝함으로써, 공정을 단순화하는 효과가 있는 반도체 장치 및 그 제조 방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, wherein a poly-silicon layer is formed by dividing and patterning the polysilicon in two steps to form an inverted 'T' type gate, thereby reducing the hot carrier phenomenon by the electric field of the gate. And a semiconductor device having an effect of collecting electrons between an interface between a source-drain region and a gate oxide film to reduce source resistance and drain resistance. In addition, channel ion implantation is selectively performed using a nitride film pattern to increase electron mobility and to prevent short channel effect by forge ion implantation. On the other hand, in order to form an inverted 'T' type gate, There is provided a semiconductor device having an effect of simplifying the process by forming a polysilicon layer without using a conventional polysilicon barrier and etching and patterning together when removing the nitride film.
Description
제1도는 종래의 반도체 장치의 구조를 도시한 단면도이고,1 is a cross-sectional view showing the structure of a conventional semiconductor device,
제2도 내지 제4도는 종래의 반도체 장치의 제조 방법을 그 공정 순서에 따라 도시한 단면도이고,2 to 4 are cross-sectional views showing a conventional method for manufacturing a semiconductor device, in accordance with the process order thereof,
제5도는 본 발명에 의한 반도체 장치의 단면도이고,5 is a cross-sectional view of a semiconductor device according to the present invention,
제6도 내지 제11도는 본 발명에 의한 반도체 장치의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.6 to 11 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention in accordance with the process procedure.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : P형 반도체 기판(또는 P형 우물) 12 : 저농도 영역(LDD)10: P-type semiconductor substrate (or P-type well) 12: low concentration region (LDD)
14 : 소스-드레인 영역 20 : 게이트 산화막14 source-drain region 20 gate oxide film
30 : 폴리실리콘층 40 : 질화막30 polysilicon layer 40 nitride film
50,80 : 산화막 격벽 60 : 게이트 패턴50,80 oxide film partition wall 60 gate pattern
70 : 산화막 90 : 절연막70 oxide film 90 insulating film
95 : 금속 전극95: metal electrode
본 발명은 반도체 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는, 역 티자형 저농도 확산 영역(ITLDD : inverse-T type lightly doped drain)을 2포함하는 반도체 장치 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor and a method of manufacturing the same, and more particularly, to a semiconductor device including an inverse-T type lightly doped drain (ITLDD) and a method of manufacturing the same.
일반적으로 반도체 장치의 규모가 미세화됨에 따라 회로의 동작 속도등의 소자 성능은 향상된다. 그러나, 동시에 핫 캐리어(hot carrier)현상과 같은 문제점이 발생하게 된다. 또한 웨이퍼 전면에 실시하는 채널 이온 주입은 채널 영역 뿐만 아니라 저농도 영역, 소스-드레인 영역에까지 이온 주입되어 전자의 이동도를 떨어뜨리게 되는데, 이러한 현상들은 모스(MOS) 트랜지스터의 규모가 초미세하게 될수록 심화된다. 그리고 초미세한 모스 트랜지스터에서는 짧은 채널 효과(short channel effect)의 문제점도 가지고 있다.In general, as the size of a semiconductor device becomes smaller, device performance such as an operation speed of a circuit is improved. At the same time, however, a problem such as a hot carrier phenomenon occurs. In addition, the channel ion implantation on the front surface of the wafer reduces the mobility of electrons by ion implantation not only in the channel region but also in the low concentration region and the source-drain region. do. In addition, the ultra-fine MOS transistor has a problem of a short channel effect.
핫 캐리어 현상을 줄이기 위한 구조로 LDD 구조가 제안되었고, 이 구조에서 변형된 구조로 ITLDD 구조가 연구되어 왔다.The LDD structure has been proposed as a structure to reduce the hot carrier phenomenon, and the ITLDD structure has been studied as a modified structure in this structure.
그러면, 첨부한 도면을 참고로 하여 종래의 반도체 장치에 대하여 더욱 상세하게 설명한다.Next, a conventional semiconductor device will be described in more detail with reference to the accompanying drawings.
제1도는 종래의 반도체 장치의 구조를 도시한 단면도이다.1 is a cross-sectional view showing the structure of a conventional semiconductor device.
제1도에 도시한 바와 같이, 종래의 반도체 장치에는 반도체 기판(110)에 N-형의 저농도 영역(LDD)(112)이 서로 간격을 두고 형성되어 있고, 그 안에 N+형의 소스-드레인 영역(114)이 형성되어 있다. 소스-드레인 영역(114)의 표면의 일부와 저농도 영역(112)의 표면, 저농도 영역(112) 사이의 반도체 기판(110)의 표면에는 게이트 산화막(120)이 형성되어 있고, 소스-드레인 영역(114)의 표면에는 실리사이드막(150)이 형성되어 있다. 이 때의 실리사이드막(150)은 측면이 게이트 산화막(120)의 측면과 부착되어 있다.As shown in FIG. 1, in a conventional semiconductor device, N − type low concentration region (LDD) 112 is formed on a semiconductor substrate 110 at intervals from each other, and an N + type source-drain is formed therein. Region 114 is formed. A gate oxide film 120 is formed on a portion of the surface of the source-drain region 114, the surface of the low concentration region 112, and the surface of the semiconductor substrate 110 between the low concentration region 112, and the source-drain region ( The silicide film 150 is formed on the surface of 114. At this time, the side surface of the silicide film 150 is attached to the side surface of the gate oxide film 120.
게이트 산화막(120) 위의 중앙 부분의 일부에는 게이트 패턴(130)이 형성되어 있으며, 게이트 패턴(130)의 표면에는 얇은 산화막(122)이 형성되어 있다. 게이트 패턴(130) 측면의 산화막(122) 옆에는 폴리실리콘 격벽(134)이 부착되어 있고, 폴리실리콘 격벽(134)의 옆면은 반도체 기판(110) 표면과 수직으로 형성되어 단차를 이루고 있으며, 밑면은 저농도 영역(112)의 표면까지 이어져 저농도 영역(112) 위의 게이트 산화막(120)에 부착되어 있다. 폴리실리콘 격벽(134)의 표면은 다시 산화막(124)으로 덮여 있으며, 그 옆에는 질화막 격벽(128)이 형성되어 있다. 이 질화막 격벽(128)이 소스-드레인 영역(114) 위의 실리사이드막(150)과 게이트 패턴(130)을 전기적으로 절연시켜 주고 있다.A gate pattern 130 is formed on a portion of the center portion on the gate oxide film 120, and a thin oxide film 122 is formed on the surface of the gate pattern 130. The polysilicon barrier rib 134 is attached to the side of the oxide layer 122 on the side of the gate pattern 130, and the side surface of the polysilicon barrier rib 134 is formed perpendicular to the surface of the semiconductor substrate 110 to form a step. Extends to the surface of the low concentration region 112 and is attached to the gate oxide film 120 on the low concentration region 112. The surface of the polysilicon barrier rib 134 is again covered with an oxide film 124, and a nitride barrier rib 128 is formed next to it. The nitride barrier rib 128 electrically insulates the silicide film 150 on the source-drain region 114 from the gate pattern 130.
게이트 패턴(130)과 폴리실리콘 격벽(134) 위의 표면에는 실리사이드막(150)이 형성되어 있어, 게이트 패턴(130)과 폴리실리콘 격벽(134)을 전기적으로 연결시켜 주고 있다.The silicide layer 150 is formed on the surface of the gate pattern 130 and the polysilicon barrier rib 134 to electrically connect the gate pattern 130 and the polysilicon barrier rib 134.
제2도 내지 제4도는 종래의 반도체 장치의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2 to 4 are cross-sectional views showing a conventional method for manufacturing a semiconductor device, in accordance with the process order thereof.
제2도에서와 같이, 반도체 기판(110)에 게이트 산화막(120)을 형성하고, 반도체 기판(110) 전면에 채널 형성을 위한 이온 주입을 한다. 그 위에 N형으로 도핑된 폴리실리콘층을 형성하고, 사진식각하여 게이트 패턴(130)을 형성한다. 게이트 패턴(130) 표면에 산화막(122)을 형성한다. 반도체 기판(110)과 게이트 패턴(130)에 형성되어 있는 산화막(122) 위에 폴리실리콘막(132)을 형성하고, 그 위에 다시 도핑된 유리막(140)을 형성한다.As shown in FIG. 2, the gate oxide layer 120 is formed on the semiconductor substrate 110, and ion implantation is performed on the entire surface of the semiconductor substrate 110. The N-type doped polysilicon layer is formed thereon, and photo-etched to form the gate pattern 130. An oxide film 122 is formed on the gate pattern 130. The polysilicon film 132 is formed on the oxide film 122 formed on the semiconductor substrate 110 and the gate pattern 130, and then the doped glass film 140 is formed thereon.
제3도에서와 같이, RSE(Reactive Sputter Etching) 방법으로 폴리실리콘 격벽(134)을 형성하고, 남아있는 도핑된 유리막(140)을 습식 식각으로 제거한다. 다음 폴리실리콘 격벽(134)을 통하여 인 이온을 주입하고, 게이트 산화막(120)을 통하여 비소 이온을 반도체 기판(110)에 주입한다.As shown in FIG. 3, the polysilicon barrier rib 134 is formed by a reactive sputter etching (RSE) method, and the remaining doped glass layer 140 is removed by wet etching. Next, phosphorus ions are implanted through the polysilicon barrier rib 134, and arsenic ions are implanted into the semiconductor substrate 110 through the gate oxide layer 120.
이 때, PMOSFET를 형성하려면 플르오르화 브롬(BF2)을 높은 에너지와 낮은 에너지로 주입한다.At this time, to form a PMOSFET, bromide fluoride (BF 2 ) is injected with high energy and low energy.
제4도에서와 같이, 폴리실리콘 격벽(134)의 표면을 산화하여 산화막 격벽(124)을 형성한다. 그리고, 반도체 기판(110) 위에 질화막을 침적하고, RSE(Reactive Sputter Etching)방식으로 사진식각하여 질화막 격벽(128)을 형성한다.As shown in FIG. 4, the surface of the polysilicon barrier rib 134 is oxidized to form an oxide barrier rib 124. The nitride film is deposited on the semiconductor substrate 110 and photo-etched by a reactive sputter etching (RSE) method to form the nitride film partition wall 128.
이후, 통상의 방법에 의해 게이트 패턴(130)의 표면과 소스-드레인 영역(114)의 표면에 실리사이드막(150)을 형성하면 제1도와 같게 된다.Subsequently, when the silicide layer 150 is formed on the surface of the gate pattern 130 and the surface of the source-drain region 114 by a conventional method, the silicide layer 150 is the same as that of FIG. 1.
이러한 종래의 반도체 장치에서는 ITLDD를 제조하여, 핫 캐리어 신뢰성을 향상하게 된다.In such a conventional semiconductor device, an ITLDD is manufactured to improve hot carrier reliability.
그러나, 이러한 종래의 반도체 장치 및 그 제조 방법에서는 제조 공정이 복잡하다는 문제점과 반도체 기판 전면에 채널 형성을 위한 이온 주입을 함으로써, 저농도 영역이나 소스-드레인 영역에도 채널 이온이 확산되어 전자의 이동도가 낮아진다는 문제점을 가지고 있다. 또한, 쇼트 채널 효과가 생길 수 있다는 문제점을 가지고 있다.However, in such a conventional semiconductor device and its manufacturing method, the manufacturing process is complicated, and ion implantation for channel formation is performed on the entire surface of the semiconductor substrate, whereby channel ions are diffused in a low concentration region or a source-drain region, thereby allowing electron mobility. It has a problem of being lowered. In addition, there is a problem that a short channel effect may occur.
본 발명의 목적은 이러한 문제점을 해결하기 위한 것으로서, 반도체 소자에 ITLDD 를 형성하여 핫 캐리어 현상을 감소하고, 채널 이온을 채널이 형성되는 부분에만 주입하여 전자의 이동도를 향상하며, 자기 정렬(self-align)을 이용하여 제1도전형의 소스-드레인 옆에 제2도전형의 이온을 주입하여 쇼트 채널 효과를 방지하는 데에 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, to form an ITLDD in a semiconductor device, to reduce hot carrier phenomenon, to inject channel ions into a portion where a channel is formed, to improve electron mobility, and to self-align The second conductive type is implanted next to the source-drain of the first conductive type by using -align to prevent the short channel effect.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 장치는,The semiconductor device according to the present invention for achieving this object,
제1도전형의 반도체 기판,A first conductive semiconductor substrate,
반도체 기판에 간격을 두고 형성되어 있는 확산 영역,Diffusion regions formed on the semiconductor substrate at intervals,
확산 영역의 일부와 그 사이의 반도체 기판 표면에 형성되어 있는 게이트 산화막,A gate oxide film formed on a part of the diffusion region and the surface of the semiconductor substrate therebetween,
게이트 산화막 위에 형성되어 있는 폴리실리콘층,A polysilicon layer formed on the gate oxide film,
폴리실리콘층의 면적보다 작고, 폴리실리콘층 위에 형성되어 있는 게이트 패턴,A gate pattern smaller than the area of the polysilicon layer and formed on the polysilicon layer,
게이트 패턴이 측면과 폴리실리콘층의 윗면에 부착되어 형성되어 있는 절연막 격벽을 포함하고 있다.The gate pattern includes an insulating film partition wall formed by being attached to the side surface and the top surface of the polysilicon layer.
또한, 본 발명에 의한 반도체 제조 방법은,In addition, the semiconductor manufacturing method according to the present invention,
제1도전형 반도체 기판 위에 게이트 산화막을 형성하고, 그 위에 제2도전형의 폴리실리콘층을 형성하는 제1단계,Forming a gate oxide film on the first conductive semiconductor substrate and forming a polysilicon layer of the second conductive type thereon;
폴리실리콘층 위에 질화막을 침적하고, 사진식각으로 질화막의 일부를 제거하여 밑의 폴리실리콘층이 노출되도록 하는 제2단계,A second step of depositing a nitride film on the polysilicon layer and removing a portion of the nitride film by photolithography to expose the underlying polysilicon layer;
질화막의 측면에 제1산화막 격벽을 형성하고, 제1산화막 격벽 사이에 채널 이온 주입을 하는 제3단계,A third step of forming a first oxide barrier rib on the side of the nitride film and implanting channel ions between the first oxide barrier rib,
반도체 기판 표면에 제2도전형의 폴리실리콘을 층적하고 평탄화 식각하여 제1산화막 격벽 사이에 게이트 패턴을 형성하는 제4단계,A fourth step of forming a gate pattern between the first oxide barrier ribs by laminating and planarizing a second conductive polysilicon on the surface of the semiconductor substrate;
제1산화막 격벽을 제거하고, 반도체 기판에 이온을 주입하여 제2도전형의 저농도 영역을 형성하는 제5단계,A fifth step of removing the first oxide barrier rib and implanting ions into the semiconductor substrate to form a low concentration region of the second conductivity type,
질화막을 제거하고 기판 전면에 산화막을 적층하는 제6단계,A sixth step of removing the nitride film and laminating an oxide film on the entire surface of the substrate;
산화막을 식각하여 게이트 패턴의 측면에 제2산화막 격벽을 형성하고, 이와 동시에 기판 표면에 형성되어 노출되어 있는 폴리실리콘층을 제거하여 게이트 산화막이 노출되도록 하는 제7단계,Etching the oxide film to form a second oxide barrier rib on the side of the gate pattern, and simultaneously removing the exposed polysilicon layer formed on the substrate surface to expose the gate oxide film;
게이트 패턴을 중심으로 양 쪽의 반도체 기판에 저농도 영역과 접하는 소스-드레인 영역을 형성하는 제8단계An eighth step of forming a source-drain region in contact with the low concentration region on both semiconductor substrates around the gate pattern;
를 포함한다.It includes.
이러한 방법에서, 반도체 기판에 이온을 주입하여 제2도전형의 저농도 영역을 형성하는 제5단계에서 이와 동시에 제1도전형의 포켓(pocket) 이온 주입을 실시할 수도 있다.In this method, a pocket ion implantation of the first conductivity type may be performed simultaneously with the fifth step of implanting ions into the semiconductor substrate to form a low concentration region of the second conductivity type.
본 발명에 따른 이러한 반도체 장치 및 그 제조 방법에서는 폴리실리콘을 두 단계로 나누어서 적층하여 패터닝하는 방법으로 하여 역 'T'자 형의 게이트를 형성함으로써, 게이트의 전기장에 의하여 핫 캐리어 현상이 감소하고, 소스-드레인 영역과 게이트 산화막과의 계면 사이에 전자가 모이게 되어, 소스 저항과 드레인 저항을 감소하게 된다. 또한 질화막 패턴을 이용하여 선택적으로 채널 이온 주입을 하여 전자의 이동도를 높이고, 제1도전형의 포켓 이온 주입으로 쇼트 채널 효과를 방지한다.In the semiconductor device and the method of manufacturing the same according to the present invention, the polysilicon is formed by dividing and patterning the polysilicon in two steps to form an inverted 'T' shaped gate, thereby reducing the hot carrier phenomenon due to the electric field of the gate, Electrons are collected between the interface between the source-drain region and the gate oxide film, thereby reducing the source resistance and the drain resistance. In addition, channel ion implantation is selectively performed using a nitride film pattern to increase electron mobility, and a short channel effect is prevented by pocket ion implantation of the first conductivity type.
그러면, 첨부한 도면을 참고로 하여 본 발명에 따른 반도체 장치와 그 제조 방법의 실시예를 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 상세히 설명한다.DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, exemplary embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.
제5도는 본 발명에 의한 반도체 장치의 단면도이다.5 is a cross-sectional view of a semiconductor device according to the present invention.
제5도에 도시한 바와 같이 본 발명의 실시예에 따른 반도체 장치에는,As shown in FIG. 5, in the semiconductor device according to the embodiment of the present invention,
P형의 반도체 기판(또는 반도체 기판에 형성되어 있는 P형 우물)(10) 위에 게이트 패턴(60)이 형성되어 있는데, 게이트 패턴(60)의 밑면에는 게이트 패턴(60)의 밑면적보다 큰 폴리실리콘층(30)이 형성되어 있어 폴리실리콘 패턴(30, 60)이 역 'T'자형의 모양으로 형성되어 있다. 폴리실리콘층(30)과 반도체 기판(10) 사이에는 게이트 산화막(20)이 형성되어 있으며, 게이트 패턴(60)의 측면에는 산화막 격벽(80)이 형성되어 있다.The gate pattern 60 is formed on the P-type semiconductor substrate (or P-type well formed on the semiconductor substrate) 10, and the polysilicon having a larger surface area than the bottom surface of the gate pattern 60 is formed on the bottom of the gate pattern 60. The layer 30 is formed so that the polysilicon patterns 30 and 60 are formed in an inverted 'T' shape. A gate oxide film 20 is formed between the polysilicon layer 30 and the semiconductor substrate 10, and an oxide film partition wall 80 is formed on the side surface of the gate pattern 60.
그리고, 폴리실리콘층(30), 게이트 패턴(60)과 산화막 격벽(80)은 절연막(90)으로 둘러싸여 있다. 게이트 패턴(60)을 둘러싸고 있는 절연막(90)과 간격을 두고, 반도체 기판(10) 표면에 절연막(90)이 형성되어 있다. 절연막(90) 사이의 반도체 기판(10) 위에는 금속 전극(95)이 형성되어 있다.The polysilicon layer 30, the gate pattern 60, and the oxide film partition wall 80 are surrounded by the insulating film 90. An insulating film 90 is formed on the surface of the semiconductor substrate 10 at intervals from the insulating film 90 surrounding the gate pattern 60. The metal electrode 95 is formed on the semiconductor substrate 10 between the insulating films 90.
반도체 기판(10)에는 N형의 저농도 영역(LDD)(12)과 N+형의 소스-드레인 확산층(14)이 형성되어 있는데, 저농도 영역(12)은 산화막 격벽(80)의 아래쪽 반도체 기판(10)에 형성되어 있고, 소스-드레인 영역(14)은 저농도 영역(12)과 접하면서, 금속 전극(95) 밑에 형성되어 있어 금속 전극(95)과 전기적으로 연결되어 있다.The N-type low concentration region (LDD) 12 and the N + type source-drain diffusion layer 14 are formed in the semiconductor substrate 10, and the low concentration region 12 is formed under the semiconductor substrate ( 10, the source-drain region 14 is formed under the metal electrode 95 while being in contact with the low concentration region 12, and is electrically connected to the metal electrode 95.
제6도 내지 제11도는 본 발명에 의한 반도체 장치의 제조8 방법을 그 공정 순서에 따라 도시한 단면도이다.6 to 11 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention 8 in accordance with the processing procedures thereof.
제6도에서와 같이, P형 반도체 기판(또는 반도체 기판에 형성되어 있는 P형 우물)(10) 위에 두께 약 150-200Å의 게이트 산화막(20)을 형성하고, 그 위에 두께 500Å 정도로 N+형의 폴리실리콘층(30)을 형성한다.As shown in FIG. 6, a gate oxide film 20 having a thickness of about 150-200 kPa is formed on the P-type semiconductor substrate (or P-type well formed in the semiconductor substrate) 10, and the N + type has a thickness of about 500 kPa thereon. Polysilicon layer 30 is formed.
제7도에서와 같이, 폴리실리콘층(30) 위에 약 3000Å의 두께로 질화막(40)을 적층한 다음 게이트 마스크를 이용하여 질화막(40)을 사진식각한다. 질화막(40)은 반도체 기판(10)의 중앙 부분이 식각되어, 식각된 부분으로 폴리실리콘층(30)이 노출되도록 한다.As illustrated in FIG. 7, the nitride film 40 is stacked on the polysilicon layer 30 to a thickness of about 3000 μm, and then the nitride film 40 is etched using a gate mask. In the nitride layer 40, a central portion of the semiconductor substrate 10 is etched to expose the polysilicon layer 30 to the etched portion.
제8도에서와 같이, 반도체 기판(10) 전면에 1500-2000Å 정도의 두께로 산화막을 적층한 다음, RIE(Reactive Ion Etching) 방법으로 식각하여 질화막(40) 측면에 제1산화막 격벽(50)을 형성한다. 그리고, 제1산화막 격벽(50) 사이의 반도체 기판(10)에 채널 이온 주입을 한다. 이 때, 질화막(40)과 제1산화막 격벽(50)이 마스크로 작용하여 채널 이온은 반도체 기판(10)의 일부분에만 주입된다. 이 부분이 후에 채널이 형성될 영역이다.As shown in FIG. 8, an oxide film is deposited on the entire surface of the semiconductor substrate 10 at a thickness of about 1500-2000 μm, and then etched by a reactive ion etching (RIE) method to form the first oxide barrier 50 on the side of the nitride film 40. To form. Then, channel ions are implanted into the semiconductor substrate 10 between the first oxide film partition walls 50. At this time, the nitride film 40 and the first oxide film partition wall 50 serve as masks so that channel ions are implanted only in a portion of the semiconductor substrate 10. This part is the area where the channel will be formed later.
제9도에서와 같이, 반도체 기판(10) 전면에 5000-6000Å 정도의 두께로 N+형의 폴리실리콘층(60)을 적층한다. 그리고, 포토레지스트막(도면에 표시 안함)을 도포하고, 질화막(40)이 드러나도록 평탄화 에칭(etch-back)을 한다.As shown in FIG. 9, an N + type polysilicon layer 60 is laminated on the entire surface of the semiconductor substrate 10 with a thickness of about 5000-6000 mm 3. Then, a photoresist film (not shown) is applied, and planar etching is performed so that the nitride film 40 is exposed.
제10도에서와 같이, 제1산화막 격벽(50)을 식각하여 제거하고, N+형 마스크를 이용하여 패터닝한 후 N형 이온을 저농도로 주입한다.(도면 표시 없음) 이 때, 이와 동시에 P형 이온으로 포켓(pocket) 이온 주입을 실시한다.As shown in FIG. 10, the first oxide film barrier 50 is etched and removed, and patterned using an N + type mask, followed by implantation of N type ions at low concentrations (not shown). Pocket ion implantation is performed with form ions.
제11도에서와 같이, 반도체 기판(10)의 질화막(40)을 식각한 다음 2000-2500Å 정도의 두께로 산화막을 침적하고, RIE 방법으로 식각하여 제2산화막 격벽(80)을 형성한다. 이 때 제2산화막 격벽(80) 외부의 폴리실리콘층(30)도 함께 제거한다. 따라서, 산화막 격벽(80)을 형성함과 동시에 역 'T'자형의 패턴을 완성하므로 종래의 방법보다 간단하다.As shown in FIG. 11, after the nitride film 40 of the semiconductor substrate 10 is etched, an oxide film is deposited to a thickness of about 2000-2500 Å and then etched by an RIE method to form a second oxide film partition wall 80. At this time, the polysilicon layer 30 outside the second oxide barrier rib 80 is also removed. Therefore, since the oxide barrier rib 80 is formed and the inverse 'T'-shaped pattern is completed, it is simpler than the conventional method.
다음, N+마스크를 이용하여 패터닝한 후 N형의 이온을 고농도로 주입하여 소스-드레인 영역(14)을 형성한다.Next, after patterning using an N + mask, N-type ions are implanted at a high concentration to form the source-drain region 14.
이후부터는 통상의 공정을 통하여 반도체 소자를 완성한다.Thereafter, the semiconductor device is completed through a conventional process.
따라서, 본 발명에 따른 반도체 장치 및 그 제조 방법은 폴리실리콘을 두 단계로 나누어서 적층하여 패터닝하는 방법으로 하여 역 'T'자 형의 게이트를 형성함으로써, 게이트의 전기장에 의하여 핫 캐리어 현상이 감소하고, 소스-드레인 영역과 게이트 산화막과의 계면 사이에 전자가 모이게 되어, 소스 저항과 드레인 저항을 감소하도록 하는 효과가 있다. 또한 질화막 패턴을 이용하여 선택적으로 채널 이온 주입을 하여 전자의 이동도를 높이고, 포켓 이온 주입으로 쇼트 채널 효과를 방지하는 효과가 있다. 한편으로는, 역 'T'자 형의 게이트를 형성하는 데에, 종래의 폴리실리콘 격벽을 이용하지 않고, 폴리실리콘층을 형성하고, 질화막을 제거할 때 함께 식각하여 패터닝함으로써, 공정을 단순화하는 효과도 있다.Accordingly, the semiconductor device and the method of manufacturing the same according to the present invention form a gate of inverse 'T' shape by dividing and patterning polysilicon in two stages, thereby reducing the hot carrier phenomenon by the electric field of the gate. The electrons are collected between the interface between the source-drain region and the gate oxide film, thereby reducing the source resistance and the drain resistance. In addition, channel ion implantation is selectively performed using a nitride film pattern to increase electron mobility, and pocket ion implantation prevents short channel effects. On the other hand, to form an inverted 'T'-shaped gate, a polysilicon layer is formed without using a conventional polysilicon barrier, and is etched and patterned together when removing the nitride film, thereby simplifying the process. It also works.
Claims (11)
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