US20010021588A1 - Nitridation for split gate multiple voltage devices - Google Patents

Nitridation for split gate multiple voltage devices Download PDF

Info

Publication number
US20010021588A1
US20010021588A1 US09/215,909 US21590998A US2001021588A1 US 20010021588 A1 US20010021588 A1 US 20010021588A1 US 21590998 A US21590998 A US 21590998A US 2001021588 A1 US2001021588 A1 US 2001021588A1
Authority
US
United States
Prior art keywords
oxide
layer
exposing
nitrogen ion
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/215,909
Other versions
US6331492B2 (en
Inventor
George R. Misium
Sunil V. Hattangady
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US09/215,909 priority Critical patent/US6331492B2/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HATTANGADY, SUNIL V., MISIUM, GEORGE R.
Publication of US20010021588A1 publication Critical patent/US20010021588A1/en
Application granted granted Critical
Publication of US6331492B2 publication Critical patent/US6331492B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/976—Temporary protective layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • the present invention relates in general to the field of integrated circuit manufacturing, and more particulary, to the formation of a thin film of nitride by using a nitrogen plasma to allow selectively etching of layers during the formation of integrated circuit components requiring multiple voltages.
  • CMOS complementary metal oxide silicon devices
  • CVD chemical-vapor deposition
  • ion implantation techniques e.g., etch protective overcoats, and of masking material.
  • Vacuum deposition and sputtering coat the wafer with a thin film which can, e.g., form an inorganic insulating material when heated in a reactive atmosphere. All three techniques can be used to achieve the deposition of a conducting or insulating layer.
  • the deposited layers may also be used as sacrificial layers for use in the selective etching and formation of an integrated circuit component.
  • the deposition of thick silicon nitride layers can be required when deep etching of surrounding area is to be accomplished. Due to the thermal expansion of the layer during high temperature steps, mechanical stress resulting from the thick silicon nitride layer can lead to device failure.
  • nitride layer that, does not require a high temperature deposition step. Also, a need has arisen for a nitride layer that can be selectively deposited without affecting a photoresist layer. Also needed, is a thinner layer (to lessen the mechanical stress otherwise caused within a thick layer at high temperatures). The layer, however, preferably still should be an effective barrier against mobile ions, and be easily removed in subsequent steps when used as a sacrificial layer.
  • the present invention provides an improved method for creating a nitrided silicon layer, or nitrided layer, which is resistant to oxide etching agents but does not require a high temperature deposition step.
  • a nitrided layer can be selectively deposited without affecting a photoresist layer.
  • the method of the present invention can also allow for the deposition of a thin layer that lessens the mechanical stress caused within the layer at high temperatures.
  • the nitrided layer of the present invention can provide an effective barrier against mobile ions, and can be easily removed during subsequent steps when used as, e.g., a sacrificial layer.
  • the present invention is directed to a method of making gate oxides on a silicon wafer surface, for multiple voltage applications, comprising the steps of growing a first oxide layer on at least first and second areas of the wafer surface and exposing the oxide areas to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer.
  • a photoresist is patterned over the first area of oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist.
  • the photoresist is then stripped and the wafer cleaned prior to etching the remaining oxide from the second area. Etching of the remaining oxide from the second area exposes the wafer surface prior to the grow of a second oxide layer without exposing the bare silicon surface of the wafer to photoresist contaminants.
  • a low temperature method for making gate oxides on a silicon wafer surface for dual voltage application comprises the steps of, obtaining a substrate and growing an oxide layer on the substrate.
  • the oxide layer has a surface that is exposed to a nitrogen ion containing plasma, where the nitrogen ions form a nitrided layer on the oxide containing surface that can be used to protect layers underneath the nitridated layer from, for example, selective etching agents.
  • the portion of the second oxide layer that is etched down after removal of the photoresist is about 40 angstroms before final etching.
  • the silicon oxide layer is maintained at a temperature below 600 degrees Celsius during nitridation of the oxide layer, and in one embodiment the temperature being room temperature.
  • the nitrogen ion plasma can be created by a remote plasma.
  • the step of exposing the oxide containing surface to a nitrogen ion containing plasma can be further defined as occurring at between about 4 and 12 mTorr, and in one embodiment may be, for example, at about 4 mTorr.
  • the step of exposing the oxide containing surface to a nitrogen ion containing plasma can also be defined as occurring for between about 10 to 90 seconds, in one embodiment the exposure occurring for about 60 seconds.
  • the oxide containing surface can be exposed to a nitrogen ion containing plasma at between about 1000 and 3000 watts.
  • the nitrogen ion containing plasma can be created at about 2000 watts.
  • the oxide surface is nitridated for 30 seconds in a 2000 W plasma.
  • the oxide is etched in a buffered hydrofluoric acid for 100 seconds.
  • a silicon layer such as a polysilicon or amorphous silicon layer can be deposited on the oxide layer after the second oxide growth step.
  • the rate of formation of the nitrided oxide layer is dependent on a substrate bias, where the rate of nitrogen ion implantation into the silicon substrate depends on the voltage difference between the substrate and the plasma.
  • a low temperature method for making gate oxides on a silicon wafer surface for dual voltage applications comprises the steps of growing a first oxide layer on at least first and second areas of the surface, at least one of the areas is exposed to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer.
  • a layer of photoresist is patterned over the first area of the oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist.
  • the photoresist is stripped and the silicon wafer cleaned to remove any photoresist contamination.
  • the remaining oxide is etched from the second area of the oxide layer.
  • the nitrided layer over the first area is etched and the wafer surface is then exposed to an oxidating environment in order to grow a silicon oxide over first and second areas.
  • FIGS. 1 a - d are illustrative cross-sections of one embodiment of the method of the present invention.
  • FIGS. 2 a - f are illustrative cross-sections of another embodiment of the method of the present invention.
  • the present invention is directed to a process for rendering a silicon dioxide layer resistant to etch chemistries used in integrated circuit component manufacturing, such as, hydrofluoric acid (HF).
  • Remote plasma nitridation is used to selectively nitridate or nitridize a small layer of a silicon dioxide layer.
  • the remote plasma nitridation may form, in situ, a “silicon nitride” which is to be understood as including a heterogenous mixture of silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiNO x ).
  • a layer of lithographically developed photoresist can be placed over the silicon dioxide prior to nitridation to cover portions of the silicon dioxide.
  • the photoresist prevents the interaction between the nitrogen ions created in the remote plasma and the silicon dioxide covered by the photoresist.
  • An alternative option is use remote plasma nitridation to cover the surface of the silicon dioxide layer with a nitrided layer prior to the application of a lithographic photoresist layer.
  • the photoresist then serves as a masking layer to protect portions of the nitridized areas during a nitride removal etch.
  • FIGS. 1 a - c The general features of the method for rendering silicon dioxide resistant to HF chemistries by the remote plasma nitridation of the present invention are shown in FIGS. 1 a - c .
  • a portion of a wafer 10 on which a silicon dioxide layer 12 has been formed is illustrated FIG. 1 a .
  • the wafer 10 is typically on a single crystal silicon substrate and can include circuit devices as well as wiring and insulating layers.
  • FIGS. 1 a - c An method for rendering silicon dioxide resistant to HF chemistries by the remote plasma nitridation is shown in FIGS. 1 a - c .
  • the silicon dioxide layer 12 is grown over the wafer 10 by a high temperature processing step in an oxidating environment.
  • a nitrided layer 22 is created on the entire surface of the silicon dioxide layer 12 as shown in FIG. 1 b .
  • a photoresist layer 14 is patterned to cover a portion of the nitrided layer 22 as shown in FIG. 1 c .
  • etching chemicals that are capable of etching nitrided portions of the oxide, are applied to remove the exposed portion of the nitrided layer 22 over the silicon dioxide layer 12 .
  • the portion of the nitrided layer 22 that was under the photoresist layer 14 still contains the nitrided surface that is resistant to HF chemistry etchants, while the exposed portion of the nitrided layer 22 was etched away, leaving bare oxide, as shown in FIG. 1 d.
  • HF in various dilutions in water and often buffered with ammonium fluoride can be used. Silicon is etched in HF at a minuscule rate and thus provides an etch stop after an overlying oxide layer is etched.
  • HF etchants the etching rate increases and decreases with etchant concentration. Increasing the temperature also increases the etch rate, with buffered solutions containing the etchants having a slightly higher activation energy.
  • FIGS. 2 a - f are illustrative cross-sections of one embodiment of a gate oxide structure and method made using the RPN process described in FIG. 1.
  • An isolation 30 is made on a portion of a wafer 10 on which a silicon dioxide layer 12 has been grown.
  • a nitrided layer 22 is formed on the entire surface of the silicon dioxide layer 12 and the isolation 30 as shown in FIG. 2 b .
  • the nitrided layer 22 can be created by, for example, a 30 second exposure to a remote plasma containing nitrogen ion created using 2000 watts of power.
  • a photoresist layer 14 is patterned to cover a portion of the nitrided layer 22 as shown in FIG. 2 c .
  • a short anneal step can be used before the photoresist layer 14 is patterned or before a subsequent etching step.
  • One such anneal step can be a rapid thermal anneal carried out at 950degrees Celsius for 30 seconds.
  • the nitrided layer 22 is etched. Etching chemicals that are capable of etching the nitridated layer 22 on the oxide layer 12 , (but that do not completely affect the photoresist layer 14 ), are applied to remove the exposed portion of the nitrided layer 22 over the silicon dioxide layer 12 .
  • the photoresist layer 14 has now been removed using, e.g., an ashing step followed by a cleaning step, while a thinner silicon dioxide layer 32 remains after the nitridated layer 22 that was covering it has been etched away.
  • the wafer 10 can now be cleaned to remove all photoresist 14 and any mobile ions that could have become associated with the bare silicon on wafer 10 .
  • silicon dioxide layer 12 can also be selectively etched to a small thickness, such as a 40 angstrom thickness over the wafer 10 .
  • the thinner silicon dioxide layer 32 has been etched away to exposed silicon wafer 10 .
  • the nitride layer 22 can also be etched away, either prior to, concurrently with, or after, the etching of thinner silicon dioxide layer 32 .
  • Etching conditions can vary, but in one example can be a 100 second exposure to buffered hydrofluoric acid. A partial etching step may also be added for 155 seconds in BHF.
  • the nitrided layer 22 as been removed and a second silicon dioxide layer 34 is grown, while at the same time the remaining silicon dioxide layer 12 is further grown. Further oxide growth yields a thicker silicon dioxide layer 12 and a new thinner silicon dioxide layer 34 , having different thicknesses for use in dual voltage gates.
  • the nitrided layer 22 does not have to removed and only a thin silicon dioxide layer 34 can be grown from wafer 10 to yield the dual thickness silicon oxide for dual voltage gates depicted in FIG. 2 f.
  • the process of the present invention prevents the exposure of the wafer 10 to contaminants from the photoresist layer 14 and the etch chemicals that can deposit reactive radicals. These reactive radicals, also known as mobile ions, decrease the reliability of the device by contaminating subsequent layers or structures.
  • the photoresist layer 14 can be removed with a standard piranha or nanostrip, followed by gate clean-up step of HF and SC 1 .
  • additional layers can be deposited and protected by the remote plasma nitridation and photoresist process to have more than two layers having different thicknesses, as is found in electrically erasable programmable read-only memory (EEPROM) cells and non-volatile memory applications.
  • Additional layers such as polysilicon and amorphous silicon layers (not depicted) can be deposited and protected using the remote plasma nitridation process disclosed herein.
  • the nitridation step may introduce nitrogen in the oxide-silicon interface, thereby improving device reliability.
  • Silicon nitride can be wet etched, for example, with either HF solutions or with hot phosphoric acid. Phosphoric acid is the “standard” wet nitride etch. In it, the nitride can etch more than 40 times as fast as CVD oxide, which is often used as a mask. The selectivity decreases at high temperatures, but in order to have useful etch rates, high-temperature boiling concentrated H 3 PO 4 generally are used. For example, 91.5% H 3 PO 4 boils at 180 degrees Celsius, etches high-temperature nitride at approximately 100 Angstroms/minute, and etches CVD oxide at about 10 Angstroms/minute. Under these same conditions, single-crystal silicon etches about 30% as fast as CVD oxide.
  • the remote plasma nitridation used in the invention can be carried out as follows. Nitridation can be performed at, for example, room-temperature by exposing a gate oxide to a short, high-density, remote helicon-based nitrogen discharge. Process conditions for the nitridation can be, for example, a process pressure of 2.7 to 12 mTorr, an input plasma power of 500 to 3000 watts, and a durations of 3 to 90 seconds. In one embodiment of the present invention, a high density plasma discharge from a helicon-based nitrogen discharge is created using a plasma power of 1000 to 3000 watts. A power of 2000 watts can also be used. The chamber pressure can also be from 4 to 12 mTorr.
  • a nitridation exposure time can be from about 10 to 90 seconds. In one embodiment, the nitridation exposure time was 20 seconds.
  • the wafer can be supported on a ceramic ring (electrically floating) or, alternatively, on an electrostatic chuck (capacitively coupled to ground).
  • Post-nitridation annealing in an inert or low partial-pressure oxygen ambient can be performed using a furnace or rapid-thermal annealing.
  • the post-nitridation anneal is conducted in a controlled environment having, e.g., N 2 , in an ambient or dilute ambient oxidation environment.
  • a rapid thermal anneal at 1000 degrees Centigrade for 60 seconds is conducted.
  • Depth profiling analysis can be performed on nitrided oxides with or without a 10 nm a-Silicon dioxide cap layer.
  • Dynamic SIMS analysis can be performed using 1 keV Cs primary ion bombardment. Monitoring of CsSi+, CsO+, and CsN+ ions can be conducted to track [SI], [N] concentrations, respectively.
  • Time-of-flight SIMS analysis can be performed using a 2 keV Ga+ primary ion bombardment, achieving 0.5-0.7 nm depth resolution within the top 5 nm of the dielectric film.
  • Gallium for example, can be selected as a primary ion source to minimize the pre-equilibrium effect nominally associated with Cs+ and O+ ion sources, allowing meaningful analysis of N and O concentrations from the top five angstroms.
  • Si x N+ and Si x O+ ions can be used to track [N] and [O] as a function of depth.

Abstract

A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention relates in general to the field of integrated circuit manufacturing, and more particulary, to the formation of a thin film of nitride by using a nitrogen plasma to allow selectively etching of layers during the formation of integrated circuit components requiring multiple voltages. [0001]
    • BACKGROUND OF THE INVENTION
  • Without limiting the scope of the invention, its background is described in connection with the manufacture and formation of integrated circuit components for use in the creation of metal oxide semiconductors, as an example. [0002]
  • Heretofore, in this field, the major steps in silicon wafer fabrication have been the use of diffusion, metallization, etching and chemical clean-up steps to form semiconductors. The introduction of thermal oxidation of silicon, the use of lithographic photoresist techniques and etching of the various components using specific and non-specific chemical agents brought forth the era of the planar processing of semiconductor integrated circuits. [0003]
  • More recently, complementary metal oxide silicon devices (CMOS) have been formed by the growth, deposition and etching of conductive and non-conductive layers taking advantage of chemical-vapor deposition (CVD) and ion implantation techniques. Chemical vapor deposition allowed for the selective and non-selective deposition of, e.g., etch protective overcoats, and of masking material. [0004]
  • In addition to CVD, other common ways for the deposition of conducting or insulation thin films has been the use of vacuum deposition or sputtering. Vacuum deposition and sputtering coat the wafer with a thin film which can, e.g., form an inorganic insulating material when heated in a reactive atmosphere. All three techniques can be used to achieve the deposition of a conducting or insulating layer. The deposited layers may also be used as sacrificial layers for use in the selective etching and formation of an integrated circuit component. [0005]
    • SUMMARY OF THE INVENTION
  • It has been found, however, that present methods for integrated circuit design and manufacture using silicon nitride layers account for a significant portion of the thermal budget during wafer processing. The thermal budget must be lowered to, e.g., enable scaling of high density integrated circuits. In addition, the large number of high temperature processing steps cause a significant impact on energy consumption and environmental impact of the current methods. The use of large amounts of chemical etching agents to remove these sacrificial layers can contribute to device failure (due, e.g., to mobile ions in the etching agents). [0006]
  • Furthermore, the deposition of thick silicon nitride layers can be required when deep etching of surrounding area is to be accomplished. Due to the thermal expansion of the layer during high temperature steps, mechanical stress resulting from the thick silicon nitride layer can lead to device failure. [0007]
  • What is needed is an improved method for the formation of a nitride layer, but that, does not require a high temperature deposition step. Also, a need has arisen for a nitride layer that can be selectively deposited without affecting a photoresist layer. Also needed, is a thinner layer (to lessen the mechanical stress otherwise caused within a thick layer at high temperatures). The layer, however, preferably still should be an effective barrier against mobile ions, and be easily removed in subsequent steps when used as a sacrificial layer. [0008]
  • The present invention provides an improved method for creating a nitrided silicon layer, or nitrided layer, which is resistant to oxide etching agents but does not require a high temperature deposition step. Using the present invention a nitrided layer can be selectively deposited without affecting a photoresist layer. The method of the present invention can also allow for the deposition of a thin layer that lessens the mechanical stress caused within the layer at high temperatures. The nitrided layer of the present invention can provide an effective barrier against mobile ions, and can be easily removed during subsequent steps when used as, e.g., a sacrificial layer. [0009]
  • More particulary, the present invention is directed to a method of making gate oxides on a silicon wafer surface, for multiple voltage applications, comprising the steps of growing a first oxide layer on at least first and second areas of the wafer surface and exposing the oxide areas to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer. Next a photoresist is patterned over the first area of oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist. The photoresist is then stripped and the wafer cleaned prior to etching the remaining oxide from the second area. Etching of the remaining oxide from the second area exposes the wafer surface prior to the grow of a second oxide layer without exposing the bare silicon surface of the wafer to photoresist contaminants. [0010]
  • In one embodiment, a low temperature method for making gate oxides on a silicon wafer surface for dual voltage application comprises the steps of, obtaining a substrate and growing an oxide layer on the substrate. The oxide layer has a surface that is exposed to a nitrogen ion containing plasma, where the nitrogen ions form a nitrided layer on the oxide containing surface that can be used to protect layers underneath the nitridated layer from, for example, selective etching agents. In one embodiment, the portion of the second oxide layer that is etched down after removal of the photoresist is about 40 angstroms before final etching. [0011]
  • More particularly, the silicon oxide layer is maintained at a temperature below 600 degrees Celsius during nitridation of the oxide layer, and in one embodiment the temperature being room temperature. The nitrogen ion plasma can be created by a remote plasma. [0012]
  • The step of exposing the oxide containing surface to a nitrogen ion containing plasma can be further defined as occurring at between about 4 and 12 mTorr, and in one embodiment may be, for example, at about 4 mTorr. The step of exposing the oxide containing surface to a nitrogen ion containing plasma can also be defined as occurring for between about 10 to 90 seconds, in one embodiment the exposure occurring for about 60 seconds. In yet another embodiment, the oxide containing surface can be exposed to a nitrogen ion containing plasma at between about 1000 and 3000 watts. In one embodiment the nitrogen ion containing plasma can be created at about 2000 watts. In yet another embodiment the oxide surface is nitridated for 30 seconds in a 2000 W plasma. During the etching step, in one embodiment, the oxide is etched in a buffered hydrofluoric acid for 100 seconds. Additionally, a silicon layer, such as a polysilicon or amorphous silicon layer can be deposited on the oxide layer after the second oxide growth step. In yet another embodiment, the rate of formation of the nitrided oxide layer is dependent on a substrate bias, where the rate of nitrogen ion implantation into the silicon substrate depends on the voltage difference between the substrate and the plasma. [0013]
  • In yet another embodiment of the invention a low temperature method for making gate oxides on a silicon wafer surface for dual voltage applications comprises the steps of growing a first oxide layer on at least first and second areas of the surface, at least one of the areas is exposed to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer. A layer of photoresist is patterned over the first area of the oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist. Next, the photoresist is stripped and the silicon wafer cleaned to remove any photoresist contamination. The remaining oxide is etched from the second area of the oxide layer. The nitrided layer over the first area is etched and the wafer surface is then exposed to an oxidating environment in order to grow a silicon oxide over first and second areas. [0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures in which corresponding numerals in the different figures refer to corresponding parts and in which: [0015]
  • FIGS. 1[0016] a-d are illustrative cross-sections of one embodiment of the method of the present invention; and
  • FIGS. 2[0017] a-f are illustrative cross-sections of another embodiment of the method of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention. [0018]
  • The present invention is directed to a process for rendering a silicon dioxide layer resistant to etch chemistries used in integrated circuit component manufacturing, such as, hydrofluoric acid (HF). Remote plasma nitridation is used to selectively nitridate or nitridize a small layer of a silicon dioxide layer. The remote plasma nitridation may form, in situ, a “silicon nitride” which is to be understood as including a heterogenous mixture of silicon nitride (Si[0019] 3N4) and silicon oxynitride (SiNOx).
  • To prevent the nitridation by remote plasma deposition over specific locations on a silicon dioxide layer, a layer of lithographically developed photoresist can be placed over the silicon dioxide prior to nitridation to cover portions of the silicon dioxide. The photoresist prevents the interaction between the nitrogen ions created in the remote plasma and the silicon dioxide covered by the photoresist. [0020]
  • An alternative option is use remote plasma nitridation to cover the surface of the silicon dioxide layer with a nitrided layer prior to the application of a lithographic photoresist layer. The photoresist then serves as a masking layer to protect portions of the nitridized areas during a nitride removal etch. [0021]
  • The general features of the method for rendering silicon dioxide resistant to HF chemistries by the remote plasma nitridation of the present invention are shown in FIGS. 1[0022] a-c. A portion of a wafer 10 on which a silicon dioxide layer 12 has been formed is illustrated FIG. 1a. The wafer 10 is typically on a single crystal silicon substrate and can include circuit devices as well as wiring and insulating layers.
  • An method for rendering silicon dioxide resistant to HF chemistries by the remote plasma nitridation is shown in FIGS. 1[0023] a-c. The silicon dioxide layer 12 is grown over the wafer 10 by a high temperature processing step in an oxidating environment.
  • A [0024] nitrided layer 22 is created on the entire surface of the silicon dioxide layer 12 as shown in FIG. 1b. Next, a photoresist layer 14 is patterned to cover a portion of the nitrided layer 22 as shown in FIG. 1c. Next, etching chemicals that are capable of etching nitrided portions of the oxide, are applied to remove the exposed portion of the nitrided layer 22 over the silicon dioxide layer 12. When the photoresist layer 14 is removed, the portion of the nitrided layer 22 that was under the photoresist layer 14 still contains the nitrided surface that is resistant to HF chemistry etchants, while the exposed portion of the nitrided layer 22 was etched away, leaving bare oxide, as shown in FIG. 1d.
  • To etch the silicon dioxide layers, HF in various dilutions in water and often buffered with ammonium fluoride can be used. Silicon is etched in HF at a minuscule rate and thus provides an etch stop after an overlying oxide layer is etched. When using HF etchants the etching rate increases and decreases with etchant concentration. Increasing the temperature also increases the etch rate, with buffered solutions containing the etchants having a slightly higher activation energy. [0025]
  • FIGS. 2[0026] a-f are illustrative cross-sections of one embodiment of a gate oxide structure and method made using the RPN process described in FIG. 1. An isolation 30 is made on a portion of a wafer 10 on which a silicon dioxide layer 12 has been grown. A nitrided layer 22 is formed on the entire surface of the silicon dioxide layer 12 and the isolation 30 as shown in FIG. 2b. The nitrided layer 22 can be created by, for example, a 30 second exposure to a remote plasma containing nitrogen ion created using 2000 watts of power. Next, a photoresist layer 14 is patterned to cover a portion of the nitrided layer 22 as shown in FIG. 2c. Before the photoresist layer 14 is patterned or before a subsequent etching step, a short anneal step can be used. One such anneal step can be a rapid thermal anneal carried out at 950degrees Celsius for 30 seconds.
  • Next, the [0027] nitrided layer 22 is etched. Etching chemicals that are capable of etching the nitridated layer 22 on the oxide layer 12, (but that do not completely affect the photoresist layer 14), are applied to remove the exposed portion of the nitrided layer 22 over the silicon dioxide layer 12. As shown in FIG. 2d, the photoresist layer 14 has now been removed using, e.g., an ashing step followed by a cleaning step, while a thinner silicon dioxide layer 32 remains after the nitridated layer 22 that was covering it has been etched away. The wafer 10 can now be cleaned to remove all photoresist 14 and any mobile ions that could have become associated with the bare silicon on wafer 10. In an alternative embodiment, silicon dioxide layer 12 can also be selectively etched to a small thickness, such as a 40 angstrom thickness over the wafer 10.
  • In FIG. 2[0028] e the thinner silicon dioxide layer 32 has been etched away to exposed silicon wafer 10. The nitride layer 22 can also be etched away, either prior to, concurrently with, or after, the etching of thinner silicon dioxide layer 32. Etching conditions can vary, but in one example can be a 100 second exposure to buffered hydrofluoric acid. A partial etching step may also be added for 155 seconds in BHF.
  • Next, as shown in FIG. 2[0029] f the nitrided layer 22 as been removed and a second silicon dioxide layer 34 is grown, while at the same time the remaining silicon dioxide layer 12 is further grown. Further oxide growth yields a thicker silicon dioxide layer 12 and a new thinner silicon dioxide layer 34, having different thicknesses for use in dual voltage gates. Alternatively, the nitrided layer 22 does not have to removed and only a thin silicon dioxide layer 34 can be grown from wafer 10 to yield the dual thickness silicon oxide for dual voltage gates depicted in FIG. 2f.
  • Unlike dual or multiple gate-oxide processes of the prior art, the process of the present invention prevents the exposure of the [0030] wafer 10 to contaminants from the photoresist layer 14 and the etch chemicals that can deposit reactive radicals. These reactive radicals, also known as mobile ions, decrease the reliability of the device by contaminating subsequent layers or structures. The photoresist layer 14 can be removed with a standard piranha or nanostrip, followed by gate clean-up step of HF and SC1.
  • Alternatively, additional layers can be deposited and protected by the remote plasma nitridation and photoresist process to have more than two layers having different thicknesses, as is found in electrically erasable programmable read-only memory (EEPROM) cells and non-volatile memory applications. Additional layers, such as polysilicon and amorphous silicon layers (not depicted) can be deposited and protected using the remote plasma nitridation process disclosed herein. Furthermore, the nitridation step may introduce nitrogen in the oxide-silicon interface, thereby improving device reliability. [0031]
  • Silicon nitride can be wet etched, for example, with either HF solutions or with hot phosphoric acid. Phosphoric acid is the “standard” wet nitride etch. In it, the nitride can etch more than 40 times as fast as CVD oxide, which is often used as a mask. The selectivity decreases at high temperatures, but in order to have useful etch rates, high-temperature boiling concentrated H[0032] 3PO4 generally are used. For example, 91.5% H3PO4 boils at 180 degrees Celsius, etches high-temperature nitride at approximately 100 Angstroms/minute, and etches CVD oxide at about 10 Angstroms/minute. Under these same conditions, single-crystal silicon etches about 30% as fast as CVD oxide.
  • The remote plasma nitridation used in the invention can be carried out as follows. Nitridation can be performed at, for example, room-temperature by exposing a gate oxide to a short, high-density, remote helicon-based nitrogen discharge. Process conditions for the nitridation can be, for example, a process pressure of 2.7 to 12 mTorr, an input plasma power of 500 to 3000 watts, and a durations of 3 to 90 seconds. In one embodiment of the present invention, a high density plasma discharge from a helicon-based nitrogen discharge is created using a plasma power of 1000 to 3000 watts. A power of 2000 watts can also be used. The chamber pressure can also be from 4 to 12 mTorr. Finally, a nitridation exposure time can be from about 10 to 90 seconds. In one embodiment, the nitridation exposure time was 20 seconds. The wafer can be supported on a ceramic ring (electrically floating) or, alternatively, on an electrostatic chuck (capacitively coupled to ground). [0033]
  • Post-nitridation annealing in an inert or low partial-pressure oxygen ambient can be performed using a furnace or rapid-thermal annealing. In one embodiment, the post-nitridation anneal is conducted in a controlled environment having, e.g., N[0034] 2, in an ambient or dilute ambient oxidation environment. Next, a rapid thermal anneal at 1000 degrees Centigrade for 60 seconds is conducted.
  • Depth profiling analysis can be performed on nitrided oxides with or without a 10 nm a-Silicon dioxide cap layer. Dynamic SIMS analysis can be performed using 1 keV Cs primary ion bombardment. Monitoring of CsSi+, CsO+, and CsN+ ions can be conducted to track [SI], [N] concentrations, respectively. [0035]
  • Separately, Time-of-flight SIMS (TOFSIMS), analysis can be performed using a 2 keV Ga+ primary ion bombardment, achieving 0.5-0.7 nm depth resolution within the top 5 nm of the dielectric film. Gallium, for example, can be selected as a primary ion source to minimize the pre-equilibrium effect nominally associated with Cs+ and O+ ion sources, allowing meaningful analysis of N and O concentrations from the top five angstroms. Si[0036] xN+ and SixO+ ions can be used to track [N] and [O] as a function of depth. While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims (25)

What is claimed is:
1. A method of making gate oxides an a silicon wafer surface, for multiple voltage applications, comprising the steps of:
growing a first oxide layer on at least first and second areas of said surface;
exposing said first and second oxide areas to a nitrogen ion containing plasma, wherein said nitrogen ions convert a top layer of said exposed oxide area into a nitrided layer;
patterning a layer of photoresist over said first area of said oxide layer;
partially etching said second area of the oxide layer not protected by said photoresist;
stripping said photoresist;
etching the remaining oxide from said second area, thereby exposing the wafer surface to an oxidating environment in order to grow a second oxide layer.
2. The method of
claim 1
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further as occurring at a temperature below 600 degrees Celsius.
3. The method of
claim 2
, wherein said temperature is room temperature.
4. The method of
claim 1
, wherein said nitrogen ion plasma is created by a remote plasma.
5. The method of
claim 1
, wherein the etching step is further defined as etching the exposed portion of said second area to a thickness of about 40 angstroms.
6. The method of
claim 1
, further comprising the step of:
depositing a polysilicon layer over said first and second oxide areas.
7. The method of
claim 1
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring at between about 4 and 12 mTorr.
8. The method of
claim 7
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring at about 4 mTorr.
9. The method of
claim 1
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring for between about 10 to 90 seconds.
10. The method of
claim 1
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring for about 60 seconds.
11. The method of
claim 1
, wherein said step of exposing said oxide containing surface to a nitrogen ion containing plasma said plasma is further defined as being created at between about 1000 and 3000 watts.
12. The method of
claim 1
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as being created at about 2000 watts.
13. A low temperature method for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of:
growing a first oxide layer on at least first and second areas of said surface;
exposing said first and second areas to a nitrogen ion containing plasma, wherein said nitrogen ions convert a top layer of said exposed oxide area into a nitrided layer;
patterning a layer of photoresist over said first area of the oxide layer;
partially etching the said second area of the oxide layer not protected by said photoresist;
stripping said photoresist;
etching the remaining oxide from said second area;
etching the nitrided layer; and
exposing the wafer surface to an oxidating environment in order to grow said first and second areas.
14. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further as occurring at a temperature below 600 degrees Celsius.
15. The method of
claim 14
, wherein said temperature is room temperature.
16. The method of
claim 13
, wherein said nitrogen ion plasma is created by a remote plasma.
17. The method of
claim 13
, wherein the etching step is further defined as etching the exposed portion of said second area to a thickness of about 40 angstroms.
18. The method of
claim 13
, further comprising the step of:
depositing a polysilicon layer over said first and second oxide areas.
19. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring at between about 4 and 12 mTorr.
20. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring at about 4 mTorr.
21. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring for between about 10 to 90 seconds.
22. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as occurring for about 60 seconds.
23. The method of
claim 13
, wherein said step of exposing said oxide containing surface to a nitrogen ion containing plasma said plasma is further defined as being created at between about 1000 and 3000 watts.
24. The method of
claim 13
, exposing at least one of said oxide areas to a nitrogen ion containing plasma is further defined as being created at about 2000 watts.
25. The method of
claim 13
, wherein said substrate is further defined as having a substrate bias, said substrate bias affecting the rate of formation of said nitrided layer.
US09/215,909 1997-12-31 1998-12-18 Nitridation for split gate multiple voltage devices Expired - Lifetime US6331492B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/215,909 US6331492B2 (en) 1997-12-31 1998-12-18 Nitridation for split gate multiple voltage devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7017497P 1997-12-31 1997-12-31
US09/215,909 US6331492B2 (en) 1997-12-31 1998-12-18 Nitridation for split gate multiple voltage devices

Publications (2)

Publication Number Publication Date
US20010021588A1 true US20010021588A1 (en) 2001-09-13
US6331492B2 US6331492B2 (en) 2001-12-18

Family

ID=26750866

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/215,909 Expired - Lifetime US6331492B2 (en) 1997-12-31 1998-12-18 Nitridation for split gate multiple voltage devices

Country Status (1)

Country Link
US (1) US6331492B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030119262A1 (en) * 2001-12-20 2003-06-26 Nec Electronics Corporation Method for manufacturing non-volatile semiconductor memory device
WO2003079405A2 (en) * 2002-03-13 2003-09-25 Varian Semiconductor Equipment Associates, Inc. Method for forming thin film layers by simultaneous doping and sintering
EP1453083A1 (en) * 2001-12-07 2004-09-01 Tokyo Electron Limited Nitriding method for insulation film, semiconductor device and production method for semiconductor device, substrate treating device and substrate treating method
US20040185647A1 (en) * 2002-02-08 2004-09-23 Zhong Dong Floating gate nitridation
US20050273686A1 (en) * 2004-06-03 2005-12-08 Turner Bryan C Arrangement in a network node for secure storage and retrieval of encoded data distributed among multiple network nodes
CN102779743A (en) * 2011-05-13 2012-11-14 台湾积体电路制造股份有限公司 Fabrication methods of integrated semiconductor structure

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649543B1 (en) * 2000-06-22 2003-11-18 Micron Technology, Inc. Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices
US6833329B1 (en) 2000-06-22 2004-12-21 Micron Technology, Inc. Methods of forming oxide regions over semiconductor substrates
US6686298B1 (en) 2000-06-22 2004-02-03 Micron Technology, Inc. Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates
US6660657B1 (en) 2000-08-07 2003-12-09 Micron Technology, Inc. Methods of incorporating nitrogen into silicon-oxide-containing layers
JP4720058B2 (en) * 2000-11-28 2011-07-13 株式会社Ｓｕｍｃｏ Silicon wafer manufacturing method
US7214593B2 (en) * 2001-02-01 2007-05-08 International Business Machines Corporation Passivation for improved bipolar yield
US6399443B1 (en) * 2001-05-07 2002-06-04 Chartered Semiconductor Manufacturing Ltd Method for manufacturing dual voltage flash integrated circuit
US6555485B1 (en) * 2002-01-28 2003-04-29 United Microelectronics Corp. Method for fabricating a gate dielectric layer
DE10207122B4 (en) 2002-02-20 2007-07-05 Advanced Micro Devices, Inc., Sunnyvale A method of forming layers of oxide on a surface of a substrate
KR100434110B1 (en) * 2002-06-04 2004-06-04 삼성전자주식회사 Method of Manufacturing Semiconductor Device
US7887711B2 (en) * 2002-06-13 2011-02-15 International Business Machines Corporation Method for etching chemically inert metal oxides
US6821904B2 (en) * 2002-07-30 2004-11-23 Chartered Semiconductor Manufacturing Ltd. Method of blocking nitrogen from thick gate oxide during dual gate CMP
US6716685B2 (en) * 2002-08-09 2004-04-06 Micron Technology, Inc. Methods for forming dual gate oxides
US6846714B1 (en) * 2002-10-03 2005-01-25 Lattice Semiconductor Corporation Voltage limited EEPROM device and process for fabricating the device
KR100448240B1 (en) * 2002-12-30 2004-09-13 주식회사 하이닉스반도체 Method of forming multiple gate oxide
US20050074947A1 (en) * 2003-09-18 2005-04-07 Kim Hak Dong Methods for fabricating semiconductor devices
KR100540060B1 (en) * 2003-12-31 2005-12-29 동부아남반도체 주식회사 Methods of manufacturing gate insulation film and measuring nitrogen density
DE102005051819B3 (en) * 2005-10-28 2007-06-14 Infineon Technologies Ag Production process for semiconductor structures
US8263463B2 (en) 2009-03-30 2012-09-11 Freescale Semiconductor, Inc. Nonvolatile split gate memory cell having oxide growth

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03231456A (en) * 1990-02-07 1991-10-15 Matsushita Electron Corp Manufacture of semiconductor device
WO1995019884A1 (en) * 1994-01-21 1995-07-27 The Regents Of The Universtiy Of California Surface treatment of ceramic articles
US5558718A (en) * 1994-04-08 1996-09-24 The Regents, University Of California Pulsed source ion implantation apparatus and method
US5502009A (en) * 1995-02-16 1996-03-26 United Microelectronics Corp. Method for fabricating gate oxide layers of different thicknesses
US6110842A (en) * 1996-06-07 2000-08-29 Texas Instruments Incorporated Method of forming multiple gate oxide thicknesses using high density plasma nitridation
US6048769A (en) * 1997-02-28 2000-04-11 Intel Corporation CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
US6063670A (en) * 1997-04-30 2000-05-16 Texas Instruments Incorporated Gate fabrication processes for split-gate transistors
US5989962A (en) * 1997-09-26 1999-11-23 Texas Instruments Incorporated Semiconductor device having dual gate and method of formation
US6235590B1 (en) * 1998-12-18 2001-05-22 Lsi Logic Corporation Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
JP2000311949A (en) * 1999-04-28 2000-11-07 Texas Instr Japan Ltd Manufacture of semiconductor device
JP2000349164A (en) * 1999-06-08 2000-12-15 Nec Corp Manufacture of semiconductor device with element isolation insulating film
US6225167B1 (en) * 2000-03-13 2001-05-01 Taiwan Semiconductor Manufacturing Company Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1453083A4 (en) * 2001-12-07 2007-01-10 Tokyo Electron Ltd Nitriding method for insulation film, semiconductor device and production method for semiconductor device, substrate treating device and substrate treating method
US20050170541A1 (en) * 2001-12-07 2005-08-04 Tokyo Electron Limited Radical processing of a sub-nanometer insulation film
US20080139000A1 (en) * 2001-12-07 2008-06-12 Tokyo Electron Limited Radical Processing of a Sub-Nanometer Insulation Film
EP1453083A1 (en) * 2001-12-07 2004-09-01 Tokyo Electron Limited Nitriding method for insulation film, semiconductor device and production method for semiconductor device, substrate treating device and substrate treating method
US20030119262A1 (en) * 2001-12-20 2003-06-26 Nec Electronics Corporation Method for manufacturing non-volatile semiconductor memory device
US7001810B2 (en) 2002-02-08 2006-02-21 Promos Technologies Inc. Floating gate nitridation
US20040185647A1 (en) * 2002-02-08 2004-09-23 Zhong Dong Floating gate nitridation
WO2003079405A2 (en) * 2002-03-13 2003-09-25 Varian Semiconductor Equipment Associates, Inc. Method for forming thin film layers by simultaneous doping and sintering
WO2003079405A3 (en) * 2002-03-13 2003-12-18 Varian Semiconductor Equipment Method for forming thin film layers by simultaneous doping and sintering
US7163901B2 (en) 2002-03-13 2007-01-16 Varian Semiconductor Equipment Associates, Inc. Methods for forming thin film layers by simultaneous doping and sintering
US20030181068A1 (en) * 2002-03-13 2003-09-25 Varian Semiconductor Equipment Associates, Inc. Methods for forming thin film layers by simultaneous doping and sintering
US20050273686A1 (en) * 2004-06-03 2005-12-08 Turner Bryan C Arrangement in a network node for secure storage and retrieval of encoded data distributed among multiple network nodes
CN102779743A (en) * 2011-05-13 2012-11-14 台湾积体电路制造股份有限公司 Fabrication methods of integrated semiconductor structure
US20120289040A1 (en) * 2011-05-13 2012-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication methods of integrated semiconductor structure
US9082789B2 (en) * 2011-05-13 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication methods of integrated semiconductor structure

Also Published As

Publication number Publication date
US6331492B2 (en) 2001-12-18

Similar Documents

Publication Publication Date Title
US6331492B2 (en) Nitridation for split gate multiple voltage devices
US6140024A (en) Remote plasma nitridation for contact etch stop
US6261973B1 (en) Remote plasma nitridation to allow selectively etching of oxide
US6597046B1 (en) Integrated circuit with multiple gate dielectric structures
TWI255012B (en) Method of manufacturing a flash memory cell
US5244819A (en) Method to getter contamination in semiconductor devices
US5668035A (en) Method for fabricating a dual-gate dielectric module for memory with embedded logic technology
US6268296B1 (en) Low temperature process for multiple voltage devices
US6828205B2 (en) Method using wet etching to trim a critical dimension
US5393686A (en) Method of forming gate oxide by TLC gettering clean
US6465323B1 (en) Method for forming semiconductor integrated circuit microelectronic fabrication having multiple gate dielectric layers with multiple thicknesses
US6579766B1 (en) Dual gate oxide process without critical resist and without N2 implant
US7547639B2 (en) Selective surface exposure, cleans and conditioning of the germanium film in a Ge photodetector
US5631178A (en) Method for forming a stable semiconductor device having an arsenic doped ROM portion
US6096664A (en) Method of manufacturing semiconductor structures including a pair of MOSFETs
US6524910B1 (en) Method of forming dual thickness gate dielectric structures via use of silicon nitride layers
US4148133A (en) Polysilicon mask for etching thick insulator
CN107978606B (en) Embedded flash memory process integration method
JPH09223752A (en) Manufacture of nonvolatile semiconductor storage device
US5877073A (en) Modified poly-buffered locos forming technology avoiding the positive charge trapping at the beak of field oxide
KR100503746B1 (en) Method for fabricating semiconductor device
US5021358A (en) Semiconductor fabrication process using sacrificial oxidation to reduce tunnel formation during tungsten deposition
JP3917282B2 (en) Method for forming insulating film on semiconductor substrate surface
KR100466209B1 (en) Method of manufacturing semiconductor device
KR20030050595A (en) Method of fabricating semiconductor device with dual gate oxide

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MISIUM, GEORGE R.;HATTANGADY, SUNIL V.;REEL/FRAME:009684/0686

Effective date: 19980302

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12