JP2915507B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a field effect transistor, and particularly uses a III-V compound semiconductor such as gallium arsenide (GaAs) as an active layer. The present invention relates to a Schottky gate type field effect transistor.

(Prior art) A Schottky junction gate field effect transistor (MESFET) using a semi-insulating GaAs substrate cannot be obtained with an integrated circuit using a silicon substrate due to the high electron mobility of GaAs. Attention has been paid to the basic elements of GaAs ICs and LSIs that enable ultra-high-speed operation.

In this GaAs field effect transistor, for example, as shown in FIG. 7, an n-type active layer 2 is formed in a semi-insulating GaAs substrate 1, and a gate electrode 3 made of a refractory metal is formed thereon. High-concentration n ⁺ layers 5 and 6 constituting source and drain are formed on the gate electrode 3 in a self-aligned manner.

It is effective to reduce the active layer width to increase the integration of integrated circuits using such GaAs field-effect transistors.However, when this reduction is performed, fluctuations in FET characteristics such as a shift in the threshold voltage to the positive side are caused. The resulting narrow channel effect is problematic.

 This narrow channel effect is as follows.

In the MESFET, a gate electrode protruding portion formed so that the gate electrode protrudes from the active layer in the width direction of the active layer is necessary for a process margin.

The influence of the Schottky barrier from the gate electrode protruding portion on the potential of the active layer is increased as the width of the active layer with respect to the active layer is reduced. As a result, the active layer region is narrowed and the threshold voltage is shifted to the positive side. For this reason, in FETs having different active layer widths, a difference occurs in the threshold voltage even if the active layers are formed with the same channel concentration.

(Problems to be Solved by the Invention) As described above, in the conventional GaAsFET, when the gate width is reduced at the time of high integration, there is a problem that the characteristics are varied due to a so-called narrow channel effect.

The present invention has been made in view of the above circumstances, and has as its object to provide a high-performance MESFET in which a narrow channel effect is completely suppressed.

〔The invention's effect〕

(Means for Solving the Problems) In the present invention, a Schottky gate electrode formed on the surface of a first conductivity type semiconductor layer formed on the surface of a substrate so as to cross the active layer, In a field-effect transistor having a source region and a drain region formed on both sides of an active layer, a neutral region is formed below the active layer and inside an edge of the active layer as viewed from above the Schottky gate electrode. A second conductivity type region having a different impurity concentration is provided.

Here, when the second conductivity type region is a p-type region, the acceptor concentration is desirably 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm.
^-3 , more preferably 1 × 10 ¹⁶ cm ^{-3 to} 1 × 10 ¹⁷
cm _-3 .

 In addition, it is desirable that the concentration is at least one digit higher than the concentration of the substrate.

Further, the width of the inside of the p-type layer is preferably 0.05 to 0.5 μm.

(Operation) In a normal MESFET, as shown in FIG. 6A, a gate electrode protruding portion formed so that the gate electrode protrudes from the active layer in the width direction of the active layer is required in view of a process margin.

The influence of the Schottky barrier at the gate electrode protrusion protruding from the active layer reaches the active layer. Due to this effect, the potential near the active layer rises and narrows the active layer region. In other words, the increase in the potential increases as the width of the active layer decreases, resulting in a narrow channel effect that narrows the channel region and shifts the threshold value to the positive side.

On the other hand, as shown in FIG. 6 (b), when a low-concentration reverse conductivity type layer (p layer) is formed at a width equal to or greater than the width of the active layer, the influence of the Schottky barrier from the protruding portion of the gate electrode is shielded. It does not reach the active layer. However, since the active layer is affected by the protrusion from the active layer in the p-layer as indicated by the dashed arrow, the potential near the channel end increases, and the threshold voltage shifts to the positive side by that amount. .

Therefore, the width of the p-layer was changed near the width of the active layer, and the threshold voltage was measured. As a result, as shown in FIG.
From the point where the width of the layer is slightly smaller than the width of the active layer,
It has been found that the shift of the threshold voltage is greatly reduced.

That is, this shift occurs even when the width of the p-layer is the same as the width of the active layer. By forming the p-layer narrower than the active layer, it is possible to suppress the shift of the threshold voltage to the positive side for the first time. it can.

On the other hand, by the above-mentioned configuration-disposing the second conductivity type region slightly inside the edge of the active tank below the active layer-the narrow channel effect can be suppressed, but in an element having a short gate length, However, this configuration rather causes a short channel effect.

Therefore, in addition to the above configuration, an intermediate concentration layer having an impurity concentration higher than that of the active layer and lower than that of the source / drain region is interposed between the active layer and the source / drain region. The distance between them can be increased to suppress the occurrence of the short channel effect, and a good effect that is not affected by both the short channel effect and the narrow channel effect
A MESFET can be formed.

In addition, the above configuration suppresses the shift of the threshold voltage and, in addition, forms an intermediate concentration layer between the active layer and the source region where the impurity concentration is higher than the active layer and lower than the source region. If the drain region is directly connected to the active layer, in the above-described configuration (LDD structure FET), the concentration and depth of the intermediate concentration layer formed in a self-aligned manner with the gate are determined by the parasitic distance between the gate and the source. Although optimization between the contradictory parameters of the resistance and the reverse breakdown voltage between the gate and the drain was required, the short channel effect can be further suppressed because the intermediate concentration layer is formed only on the source side. In addition, it is not necessary to consider the drain withstand voltage when designing the concentration depth and the like, and the degree of freedom in the design is increased, and as a result, the gate-source resistance Rs can be further reduced.

Further, compared to the case of the LDD structure, since there is no intermediate concentration layer on the drain side, the gate length can be shortened, the gate capacitance Cg can be reduced, and at the same time, the current driving force Gm can be improved.

In addition, this transistor directly connects a first field-effect transistor and a second field-effect transistor, such as an SLCF circuit or a DCFL circuit, in which capacitance between a gate and a drain is a particularly important factor, Is effective in forming an integrated circuit by using the as a switching element of an inverter. That is, the capacitance between the gate and drain is
In the case of the switching FET of the FL circuit, it works as a feedback capacitance between the input and the output. Therefore, reducing this has about twice the contribution to high-speed operability as compared with that between the gate and the source, and the effect is extremely large.

As described above, according to the configuration of the present invention, it is possible to obtain an extremely reliable MESFET having no short channel effect and narrow channel effect.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIGS. 1 (a) to 1 (c) are a plan view, an AA 'sectional view and a BB' sectional view of a GaAs-MESFET according to an embodiment of the present invention.

In this GaAs-MESFET, an n-type active layer 2 is formed in a semi-insulating GaAs substrate 1, and a p-type layer 9 is provided below this so that the edge is slightly inside the edge of the active layer 2. A gate electrode 3 made of tungsten nitride (WN) is formed on an upper layer of the n-type active layer 2, and a high-concentration n which forms a source / drain in a self-aligned manner is formed on the gate electrode 3. ⁺ Layers 5 and 6 are formed. Reference numeral 4 denotes an insulating film formed on the side wall of the gate, and reference numerals 7 and 8 denote source / drain electrodes made of AuGe / Au layers.

 Next, the manufacturing process of the GaAs-MESFET will be described.

First, a resist pattern having a window in a formation region of a p-type layer 9 shown by a broken line in FIG. 1A of a semi-insulating GaAs substrate 1 is formed. Ion implantation is performed at 180 KeV and a dose of 2 × 10 ¹² cm ⁻² to form a p-type layer 9. Here, the p-type layer 9 may be formed by another method such as a solid phase diffusion method.

Next, a resist pattern for forming an active layer is formed, and ions of Si ions are implanted, for example, at an acceleration voltage of 25 KeV and a dose of 7 × 10 ¹² cm ⁻² to form an n ⁻ -type layer 2 serving as an active layer of the FET.

After that, the resist pattern is removed, and a gate metal made of tungsten nitride (WN) is formed by sputtering.
The gate electrode 3 is formed by depositing the film so as to have a thickness of 3000 ° and forming a pattern by reactive ion etching.

Next, the resist pattern is removed, and a silicon oxide film having a thickness of 0.4 is formed by a method having excellent step coverage such as a plasma CVD method.
After depositing about μm, the silicon oxide film 4 is left only on the side wall of the gate electrode by etching by a thickness corresponding to the film thickness in the vertical direction by anisotropic etching such as reactive in etching (RIE).

Further, a resist pattern having a window is formed in an element forming region including a source / drain region, and Si ions, for example, at an acceleration voltage of 80 KeV and a dose of 3 × 10 3 are masked using the silicon oxide film, the resist pattern, and the gate electrode as a mask.
Ion implantation is performed at ¹³ cm ⁻² to form n ⁺ -type layers 5 and 6.

Finally, an AuGe / Au layer is formed, a source electrode 7 and a drain electrode 8 are formed by a lift-off method, and annealing for activating the ion-implanted layer is performed (800 to 900 ° C.).
The FET according to the embodiment of the present invention is completed. By forming each impurity layer under such ion implantation conditions, a neutral region is reliably formed in the p-type layer 9. This region is such that almost the same number of acceptors and holes exist.

According to this MESFET, it is possible to obtain an extremely reliable integrated circuit without a shift in threshold voltage.

The result of measuring the relationship between the active layer width Wg and the threshold voltage Vth of the MESFET having this structure is shown by a curve a in FIG. Curve b is p
Active layer width Wg and threshold voltage Vth of a conventional FET without a mold layer
The relationship is shown below. Here, the gate length Lg was 1.0 μm.
As is apparent from this figure, in the conventional FET, the average value of the threshold voltage Vth greatly changes in the positive direction when the active layer width Wg decreases, whereas in the case of the FET of the present invention, The average value of the threshold voltage Vth does not change even with the change of the active layer width Wg.

In addition, the variation in threshold voltage
It can be seen that the variation increases as the active layer width Wg decreases, whereas the FET of the present invention does not show much variation.

Further, by varying the amount of protrusion of the p layer from the active layer width, shown in Figure 3 the results of measuring the relationship between the shift amount ΔVth of the protrusion amount W _pn and the threshold voltage. Here, the vertical axis indicates a threshold voltage shift amount ΔVth in which the active layer width is 1 μm with respect to a threshold voltage having an active layer width of 20 μm in which the narrow channel effect does not occur, and the horizontal axis indicates the protrusion of the p layer from the active layer in the active layer width direction. _{Shows the} quantity _Wpn .

From this figure, when forming a p layer to 0.1μm inside than when the protrusion amount W _pn is -0.1μm or active layer width, it is possible to completely suppress the narrow channel effect, the threshold voltage shift amount [Delta] Vth 0 Can be

Embodiment 2 Next, as a second embodiment of the present invention, a structure for preventing a short channel effect which is likely to occur when the gate width is reduced will be described. In the following description, a detailed description of the same parts as in the first embodiment will be omitted.

FIG. 4 is a sectional view showing an FET structure according to a second embodiment of the present invention. This medieval region is formed in the p-type layer 9 in the same manner as in the previous embodiment. This corresponds to the cross section shown in FIG. 1B in the first embodiment.

In this structure, the source / drain regions 5, 6 and the active layer 2
And an intermediate concentration region 2n having an impurity concentration lower than that of the source / drain regions 5 and 6 and higher than that of the active layer 2 therebetween to form an LDD structure.

In this structure, the short channel effect is suppressed by increasing the distance between the deep high-concentration n ⁺ layers 5 and 6 by the intermediate concentration layer rather than the gate length, and at the same time, the n-type layer serving as the intermediate concentration layer
Due to the presence of 4a and 4b, an increase in source resistance Rs can be suppressed.

This MESFET is the same as the embodiment 1 except that an intermediate concentration layer is formed.
Can be formed by the same manufacturing method as that shown in FIG.

 An example of a method for forming the intermediate concentration layer will be described below.

Before depositing the insulator 4 formed on the side wall of the gate,
A resist pattern having a window is formed in an element formation region including a source / drain region.
Ion implantation is performed at 50 keV and a dose of 1 × 10 ¹³ cm ⁻² .

Third Embodiment However, also in the structure of the second embodiment, since the concentration of the n-type layer 2n of the intermediate concentration layer is as large as 2 to 10 times that of the active layer 2, the capacitance between the gate and the drain increases. In addition, if the concentration of the intermediate concentration layer 2n is increased to further reduce Rs, the capacitance between the gate and the drain increases, and at the same time, the breakdown voltage between the gate and the drain also decreases. Optimization has to be performed, and there is a problem that the degree of freedom in device design is small.

Therefore, as a third embodiment of the present invention, as shown in FIG. 5, the intermediate concentration layer 2n between the active layer 2 and the source region 5 has an impurity concentration higher than that of the active layer 2 and lower than that of the source region.
Is formed, and the drain region 6 is directly connected to the active layer 2.

This MESFET can be realized by forming a resist pattern having a window in the element formation region including the source / drain regions shown in the method of forming the intermediate concentration layer shown in the second embodiment. In other words, the resist pattern may be formed such that the window extending to the drain side is narrowed to the gate electrode.

This FET can suppress both the short channel effect and the narrow channel effect.

That is, during this because FET is the between the source and drain regions 5 and 6 is a deep n ⁺ layer with high concentration is formed apart added d1 + d2 in the gate length L _g, source drain regions 5 and 6 through the semi-insulating substrate The leakage current flowing through is reduced. Therefore it is possible to shorten the gate length, a gate capacitance Cg is reduced, thereby improving the current drivability g _m.

Further, an intermediate concentration layer is provided between the gate electrode 3 and the source region 5.
Since 2n is present, the source resistance Rs is reduced, thereby improving the current drivability g _m.

Paying attention to the drain end of the gate electrode, the source end is in contact with the intermediate-concentration layer 2n having a higher concentration than the active layer 2, whereas the drain end has no intermediate-concentration layer 2n. It is only in contact with the active layer 2. For this reason,
As compared with the case where the intermediate concentration layer 2n exists, the impurity concentration at the drain end of the gate electrode is significantly reduced, and as a result, the junction capacitance between the gate and the drain is greatly reduced. In the case of a switching FET of a DCFL circuit, this gate-drain capacitance acts as a feedback capacitance between the input and output, so reducing it is about twice as fast as that between the gate and source for high-speed operation. The effect is great.

As described above, this transistor directly connects the first field-effect transistor and the second field-effect transistor, such as the SLCF circuit and the DCFL circuit, in which the capacitance between the gate and the drain is a particularly important factor. This is effective when an integrated circuit is formed using one transistor as a switching element of an inverter.

Further, as a result of the drastic reduction of the impurity concentration at the drain end of the gate electrode, there is an effect that the Schottky reverse characteristics between the gate and the drain, particularly the breakdown voltage, are greatly improved.

Further, in the conventional LDD structure, the degree of freedom was small because the setting of the depth and concentration of the intermediate concentration layer had to be determined in consideration of both the series resistance Rs on the source side and the gate reverse breakdown voltage on the drain side. On the other hand, the structure of the present invention does not need to consider the gate breakdown voltage on the drain side, and has an advantage that the degree of freedom in design is large.

The present invention is not limited to the above embodiment, and can be appropriately changed without departing from the spirit of the present invention.

〔The invention's effect〕

As described above, according to the MESFET of the present invention,
A layer of the second conductivity type is provided below the active layer of the first conductivity type in a region slightly narrower than the width, and a neutral concentration region is provided. A high semiconductor integrated circuit can be provided.

[Brief description of the drawings]

1A to 1C show a GaAs MESFET according to a first embodiment of the present invention, and FIG. 2 shows a MESFET according to an embodiment of the present invention.
FIG. 3 is a diagram showing a relationship between an active layer width Wg and a threshold voltage Vth of a conventional MESFET, and FIG. 3 is a diagram showing a relationship between a protrusion amount _Wpn of a p-layer from the active layer width and a threshold voltage shift amount ΔVth. FIG. 4 is a view showing a MESFET of a second embodiment of the present invention, FIG. 5 is a view showing a MESFET of a third embodiment of the present invention, FIGS. 6 (a) and 6 (b). Is a diagram for explaining the operation principle of the present invention, and FIG. 7 is a diagram showing a conventional MESFET. DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate, 2 ... Active layer (n layer), 2n ... Intermediate concentration layer, 3 ... Gate electrode, 4 ... Insulating film, 5 ... Source region, 6 ... Drain region, 7 ... Source electrode, 8 ... a drain electrode, 9 ... a p-type layer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (1)

(57) [Claims] An active layer formed of a semiconductor layer of a first conductivity type formed on a surface of a substrate; a Schottky gate electrode formed on a surface of the active layer so as to cross the active layer; In a field effect transistor having a source region and a drain region formed on both sides, a neutral region is formed below the active layer and inside an edge of the active layer when viewed from above the Schottky gate electrode. A field-effect transistor comprising a second conductivity type region having an impurity concentration.