JPS61110466A - Field effect semiconductor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high performance field effect semiconductor device by forming the second conductive type barrier layer in a junction with a substrate except the portion contacted with the operation layer of source and drain regions, thereby preventing a threshold voltage from decreasing due to shortening of a channel, a drain conductance from increasing and mutual conductance from decreasing. CONSTITUTION:With a gate electrode 13 and an SiO2 film 20 of the side wall of the electrode as masks Si ions are implanted. Thus, N<+> type source and drain regions 14, 15 which is higher density and deeper than an operation layer 12 are formed in a self-aligning manner for the electrode 13. Subsequently, with the same masks Mg ions are implanted, for example, as P type impurity. The means flying distance of the Mg ions is longer than that of Si ions at source and drain region forming time, and lateral extension due to the scattering at ion implanting time is large. Accordingly, P type barrier layers 16, 17 are formed at the lower and side portions of the regions 14, 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same.

[Technical background of the invention and its problems]

The one shown in FIG. 5 is known as a Schottky gate field effect transistor (MESFET) using a semi-insulating GaAs substrate. In the figure, 31 is a semi-insulating GaAS substrate, on the surface of which an n-type operating layer 32 is formed, and with this operating layer 32, a gate electrode 33 forming a Schottky barrier is formed. n+ type source region [
34 and a drain region 35 are formed in a self-aligned manner with the gate electrode 33 by ion implantation, and a source electrode 36 and a drain electrode 37 are formed on their respective surfaces. When such GaAs-MESFETs are miniaturized, the source electrode 36. The spacing between the drain electrodes 37 becomes narrower, and the effect of applying a high electric field between them and the source region 3
4 and the effect of the close proximity of the drain region 35, the current flowing through the substrate 31 in addition to the 'R current flowing through the active layer 32, which is the channel, increases. As a result, MESFE
There are problems in that the threshold voltage of T decreases, the drain conductance increases, and the mutual conductance decreases. In particular, MESFETs using semi-insulating substrates are
Unlike a 51-MOSFET or the like that uses a conductive substrate, the potential barrier between the source and train regions and the substrate is low, so the above-mentioned problems associated with shortening the channel become noticeable.

In order to solve this problem, as shown in FIG. 6, a p-type! ! It is proposed to form 38. However, this structure causes the following new problem. In other words, it is difficult to form a p-type layer on a GaAS substrate with good controllability, and in the structure in which the p-type layer 38 is formed partially over the active layer 32 that becomes the channel, as shown in FIG.
Variations in the formation of the p-type layer 38 are directly reflected in variations in the threshold voltage of the MESFET. Also, since the pn junction capacitance l is in parallel with the Schottky barrier capacitance, the gate capacitance l
increases, resulting in a decrease in operating speed.

[Purpose of the invention]

In view of the above points, the present invention has solved the problem of characteristic deterioration due to miniaturization. An object of the present invention is to provide a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same.

(Summary of the Invention) A field effect semiconductor device according to the present invention includes an active layer of a first conductivity type formed on a surface portion of a semi-insulating compound semiconductor substrate,
In a structure in which deep and high degree source and drain regions of the same conductivity type as the active layer are formed in self-alignment with the gate electrode formed on the surface thereof, the substrate excludes the portions of the source and drain regions that are in contact with the active layer. It is characterized in that a barrier layer of the second conductivity type is provided at the joint portion with the substrate.

Further, the method of the present invention for manufacturing such a field effect semiconductor device includes forming source and drain regions of the first conductivity type by implanting impurity ions using an insulating film selectively formed on the gate electrode and its sidewalls as a mask. In addition to this process, another impurity ion implantation is performed to form a second conductivity type barrier layer at the junction with the substrate except for the portions of the source and drain regions that are in contact with the active layer. In this case, the ion implantation process for forming the barrier layer may be performed after or before the ion implantation process for forming the source and train regions. Also, before forming an insulating film on the side walls of the gate electrode, the source is formed later using only the gate electrode as a mask.

It is also possible to form the barrier layer only directly under the portion of the source and drain regions that contact the active layer by implanting ions to a depth shallower than or approximately the same as that of the drain region.

(Effects of the Invention) The field effect semiconductor device according to the present invention can suppress the current flowing through the semi-insulating substrate under the active layer, which is the channel region, even when miniaturized.
Decrease in threshold voltage and increase in drain conductance due to shorter channels.

A high-performance field-effect semiconductor device can be obtained by preventing a decrease in mutual conductance. Furthermore, in the present invention, the barrier layer that suppresses the substrate current is provided only around the source and drain regions rather than the entire surface under the active layer, which is the channel region. There is no increase, and there is no increase in gate capacitance.

Furthermore, according to the method of the present invention, the excellent device characteristics described above can be achieved by simply adding a slight ion implantation step for forming a barrier layer to the conventional steps. Moreover, the ion implantation process for forming the barrier layer can be easily carried out at an appropriate time after or before the ion implantation process for forming the source and drain regions, using the gate electrode or an insulating film formed on the gate electrode and its sidewalls as a mask. is possible.

In particular, when the device and method of the present invention are applied to an integrated circuit,
This is useful for high-speed operation and high integration.

(Example of the invention) The present invention will be explained in detail below.

FIG. 1 shows an example of a (3aAs-MESFET).

11 is semi-insulating Ga with a resistivity of about 107 to 108 Ω・α
An n-type active layer 12 serving as a channel region is formed on the surface of the As substrate, and a Schottky gate electrode 13 made of 4000 tungsten nitride (WNx) is formed on the surface. Operation II! is performed by ion implantation on both sides of the substrate across the gate electrode 13! An n+ type source region 14 and a drain region [15] which are higher in concentration and deeper than 12 are formed. These source and drain regions 14.1
A high barrier is formed at the junction with the substrate 11 except for the portion in contact with the active layer 12 around the source and drain regions 14 and 15 to prevent carrier injection (electron injection in this example) from the source and drain regions 14 and 15. P-type barrier layers 16 and 17 are formed.

18 and 19 are source and drain electrodes, respectively.

An example of manufacturing such a MESFET is shown in Figure 2 (
This will be explained next with reference to a) to (e).

First, 50% of 3i ions are placed on a semi-insulating GaAS substrate 11.
KeV, 2. Ox10' z/df) conditional ion implantation is performed to form the n-type operating layer 12. Next, add W on this board.
A gate electrode 13 having a width of 1.0 μm is formed using a known photolithography technique and dry etching technique (FIG. 2(a)). After this, a 5iOz film was deposited on the entire surface of the substrate for 30 minutes by plasma CVD.
000 is deposited, and this Si 02 II is etched by an amount equivalent to the film thickness by an anisotropic dry etching method such as RIE.

The 5iOz film formed by plasma CvO is isotropically deposited and the same film thickness is formed on the side walls of the gate electrode 13. Therefore, by etching the entire surface using anisotropic dry etching, it is selectively etched only on the side walls of the gate electrode 13. The SiO2 film 20 can be left behind (FIG. 2(b)).

After this, the gate electrode 13 and its ll! 3i0
Si ions are implanted using the second film 20 as a mask. At this time, the ion implantation conditions are, for example, 100KeV, 1.0x
By selecting lO1'/ai, n" type source and drain regions 14 and 15, which are higher in concentration and deeper than the active layer 12, are formed in a self-aligned manner with respect to the gate electrode 13 (FIG. 2(C)).

Subsequently, using the same mask, as a p-type impurity, for example, M
O ions, 240 KeV, 5x1011/a
Ion implantation is performed under the conditions of i. Under these conditions, the average range of MO ions is larger than that of 3i ions when forming the source and drain regions, and the lateral spread due to scattering during ion implantation is also large. A p-type barrier layer 16.17 is formed at the bottom and sides (FIG. 2(d)). Source, train area 1
MO ions are also implanted in 4.15, but the implantation amount is less than that of Si.
The source and drain regions 14. are smaller than those of the source and drain regions 14.
The decrease in concentration of 15 is negligible. Additionally, Mg ions also enter the 0-operation layer 12 under the SiO2 film 20 due to the lateral scattering during the ion implantation described above, but for the same reason, the operation layer in this portion is not inverted.

After this, annealing for activation of the implanted impurities was performed at 800-850°C.
The process was carried out at 0°C, and the source and drain electrodes 18 and 19 were formed using an AuGe alloy, and a self-aligned GaAs-M
The ESFET is completed (Fig. 2(e)).

MESFET according to this example and conventional MESF manufactured under the same conditions as the pond water example without forming a p-type barrier layer.
As a result of comparison with ET, the threshold voltage of the conventional MESFET is -0.1V, while the threshold voltage of this example is +0.
．． The voltage was 0.05V.

By the way, MESF with a gate length of 10 μm was fabricated at the same time.
The threshold voltage of ET for both the present example and the conventional type was +0.1v. From these data, it can be seen that in the conventional MESFET, the threshold voltage is shifted to the negative side by 0.2 V due to the current flowing through the semi-insulating substrate due to the shortened channel, whereas in this example, this shift l is It can be seen that the value is kept to a small value of 0.05■.

Furthermore, when comparing the MESFET according to this example with the MESFET in which a p-type layer is provided in the entire lower part of the active layer as shown in FIG. It was confirmed that high-speed operation is possible in this example because there is no increase in gate capacitance.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, as explained in FIGS. 2(c) and 2(d) of the above embodiment, 3i forming the source and drain regions 11g14.15.
The ion implantation process of ions and the ion implantation process of MQ ions forming the p-type barrier layer 16.17 can be reversed.

In addition, the n-type operating layer 1 accompanying the formation of the p-type barrier layers 16 and 17
In order to compensate for the decrease in the concentration of 2, as shown in Figure 3,
Under the 5iOz film 20, an n-type layer 21 is formed separately from the auxiliary IY layer 12.
22 may be formed. Such a structure can be constructed, for example, in the state shown in FIG. 2(a) of the above embodiment, that is, after forming the gate electrode 13 and before forming the Si02 film 20 on its sidewall, 3i ions are heated at 50 KeV and 5x1012 / This can be obtained by implanting ions to about ci. This results in
If the n-type layer 21.22 is formed to the same depth as the active layer 12 and has an impurity concentration 1.2 to 5 times higher than that of the active layer 12, a decrease in the concentration of the active layer during formation of the p-type layer can be effectively prevented. be able to.

Furthermore, in the above embodiments, the p-type barrier layer is used as the source.

Although it is formed at all junctions with the substrate except for the portion of the drain region in contact with the active layer, the same effect can be obtained by providing it locally under the active layer. Such an embodiment will be explained with reference to FIG. As in the previous example, the semi-insulating G
The n-type active layer 1 is formed by ion implantation of Sl into the aAS substrate 11.
2 and a Schottky gate electrode 13 on its surface.
form. In this state, $1 ions and MO ions are successively implanted using the gate electrode 13 as a mask to form n-type layers 21, 22 and p-type layers having a slightly higher concentration than the active layer 12.
type barrier layers 16 and 17 are formed (FIG. 4(a)), at this time, the peak position of the 3i ions is set to be approximately the same as that of the active layer 12, and the peak position of the MQ ions is set to the same level as the active layer 12. The ion implantation conditions are set so that the ion implantation condition is deeper than that of the ion implantation layer, and the ion implantation condition is about the same level or slightly shallower than that of the n+ type layer of the source and drain to be formed later. Thereafter, as in the previous embodiment, a SiO2 film 20 is selectively formed on the sidewalls of the gate electrode 13.
to form a ko(DS i 02 M! 20 t'y
h? Using 1q1413 as a mask, 3i is ion-implanted at a high concentration to form n''' type source and drain regions 14.15.
and source and train electrodes 18 and 19 on its surface.
is completed by forming (Fig. 4(b)).

In this way, the p-type barrier 1116.17 becomes the source.

A MESFET is obtained that is formed only on the side of the drain region 14, 15 directly below the active layer 12. Such a structure includes an n-type layer 21 .
It is also effective to apply the embodiment described in FIG. 1 or 2, for example, in which the structure 22 is not formed.

Several modifications can be made to the materials and substances used in the present invention. For example, as the gate electrode, n-type Ga
In addition to WNx, W and WSix can be used as long as they form a good Schottky barrier with As and maintain their properties even after heat treatment.

W-Affi, Mo, MOS ix, etc. can be used. The implanted impurity is Se, S, etc. in the case of n-type, p
In the case of a mold, 8e etc. can be used. Further, in the above embodiment, only n channel was explained, but the present invention can also be applied to the case of ρ channel. Furthermore, the present invention can be applied to junction FETs in addition to MESFETs, and can also be applied to junction FETs, using Ga as a substrate.
The present invention can be similarly applied when a semi-insulating compound semiconductor substrate other than As is used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a GaAS-MESFET according to an embodiment of the present invention, FIG. 2 <a) to (e) are diagrams for explaining the manufacturing process, and FIG. MESF
ET, FIGS. 4(a) and 4(b) are diagrams for explaining the manufacturing process of GaAs-MESFET of Ike's embodiment, and FIGS. 5 and 6 are diagrams for conventional GaAs-MESFET.
FIG. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAS substrate, 12... N-type operating layer, 13... Schottky gate electrode [i, 14...
・n++ source region, 15...n+ type drain region 16.17...p type barrier layer, 18...source electrode, 19...drain electrode, 20...5iO211,
21°22...n-type layer. Applicant's agent Patent attorney Takehiko Suzue No. 30 Figure 4 Figure 5r5 Figure 6

Claims (7)

[Claims] (1) A semi-insulating compound semiconductor substrate, a first conductivity type active layer formed on the surface of the substrate, a gate electrode formed on the active layer, and the substrate surface with the gate electrode in between. source and drain regions of a first conductivity type and with high impurity concentration formed deeper than the operating layer; and a second conductive region at a junction with the substrate excluding a portion of the source and drain regions in contact with the operating layer. A field-effect semiconductor device characterized by providing a type barrier layer. (2) The semi-insulating compound semiconductor substrate is semi-insulating GaA
2. The field effect semiconductor device according to claim 1, wherein the gate electrode is an S substrate and forms a Schottky barrier between the gate electrode and the active layer. (3) forming an active layer of a first conductivity type on the surface of a semi-insulating compound semiconductor substrate, forming a gate electrode on the active layer, and selectively forming an insulating film on the sidewalls of the gate electrode; a step of ion-implanting impurities using the gate electrode and the insulating film as a mask to form source and drain regions of a first conductivity type and high impurity concentration deeper than the active layer; and a step of implanting another impurity. forming a barrier layer of a second conductivity type at the junctions of the source and drain regions with the substrate, excluding the junctions with the active layer, by ion implantation. Production method. (4) The ion implantation step for forming the barrier layer is performed after forming an insulating film on the side wall of the gate electrode, and before or after the ion implantation step for forming the source and drain regions. A method for manufacturing a field effect semiconductor device. (5) Before the step of forming an insulating film on the side walls of the gate electrode, using the gate electrode as a mask, impurity ions are implanted to the same depth as the active layer and 1.2 to 5 times the impurity. 4. The method of manufacturing a field effect semiconductor device according to claim 3, further comprising the step of forming a first conductivity type layer having a high concentration. (6) The ion implantation step for forming the barrier layer is performed at a depth shallower than or to the same depth as the source and drain regions to be formed later, before forming an insulating film on the sidewalls of the gate electrode. 4. A method for manufacturing a field-effect semiconductor device according to item 3. (7) The semi-insulating compound semiconductor substrate is semi-insulating GaA
4. The method of manufacturing a field effect semiconductor device according to claim 3, wherein the gate electrode is an S substrate and forms a Schottky barrier between the gate electrode and the active layer.