JPS62206884A - Field-effect type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the deterioration in characteristics caused by fining by forming a conductivity type barrier layer to the junction section of a first conductivity type layer in the lower section of the side section of a gate electrode and a substrate in depth deeper than source-drain regions. CONSTITUTION:An n-type operating layer 12 as a channel region is shaped to the surface section of a semi-insulating GaAs substrate 11, and a Schottky- gate electrode 13 consisting of tungsten nitride is formed onto the surface of the operating layer 12. n<+> type source region 14 and drain region 15, which has concentration higher than the operating layer 12 and is deeper than the operating layer 12, are shaped on both sides of the substrate through ion implantation, holding the gate electrode 13. p-type barrier layers 16, 17 forming high barriers to carrier injection to the substrate 11 from the source-drain regions 14, 15 are shaped on boundary sections with the substrate 11 of sections adjacent to the gate electrode of these source-drain regions 14, 15. Accordingly, the drop of threshold voltage with the shortening of a channel, the increase of drain-conductance and the lowering of mutual conductance are prevented, thus improving performance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same.

[Technical background of the invention and its problems]

The Schottky gate field effect transistor (MESFET) using a semi-insulating GaAs substrate is shown in FIG. An n-type operating layer 32 is formed, and a gate f4 pole 33 forming a Schottky barrier with this operating layer 32 is formed.

The R+ type source region 34 and drain region 35 are formed in a self-aligned manner with the gate electrode 33 by ion implantation, and a source 11iIi@36 and a drain electrode 37 are formed on their respective surfaces. Such GaAg −
As MESFETs are miniaturized, the spacing between the source electrode 36 and drain electrode 37 narrows, and the effect of applying a high electric field between them and the effect of the source region 34 and drain region 35 being extremely close to each other combine to improve channel operation [ 32
In addition to the current flowing through the substrate 31, the current flowing through the substrate 31 increases.

As a result, there are problems in that the threshold voltage of the MESFET decreases, the drain conductance increases, and the mutual conductance decreases.

In particular, NESFETs that use semi-insulating substrates differ from S, t-MESFETs, etc. that use conductive substrates in that they
Since the potential barrier between the drain region and the substrate is low, the above-mentioned problems associated with shortening the channel become noticeable.

Therefore, a structure has been proposed in which two layers serving as a potential barrier are formed around the source/drain regions as shown in FIGS. 5 and 6. However, in the structure shown in FIG. 5, the junction area between the source/drain regions 14, 15 and the p-type pRs 16, 17 is large, so the capacitance with respect to the substrate is large. Showa 59-2
31711), the p-wall region 1
There was a problem that the barrier effect was insufficient due to the small size of 6.17 mm.

[Purpose of the invention]

In view of the above points, the present invention has solved the problem of characteristic deterioration due to miniaturization. An object of the present invention is to provide a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same.

[Summary of the invention]

A field-effect semiconductor device according to the present invention includes an active layer of a first conductivity type formed on a surface portion of a semi-insulating compound semiconductor substrate,
In a structure in which deep and highly doped source/drain regions of the same conductivity type as the active layer are formed in self-alignment with the gate electrode formed on the surface, the first region below the side of the gate electrode is formed.
The method is characterized in that a barrier layer of the second conductivity type is formed deeper than the source/drain regions at the junction between the conductivity type layer and the substrate.

In addition, the method of the present invention for manufacturing such a field effect semiconductor device includes forming source/drain regions of the first conductivity type by ion implantation of impurities using the gate electrode as a mask, and then selectively implanting the source/drain regions on the sidewalls of the gate electrode. After forming an insulating film on the first conductivity type layer, another insulating film is formed, and then only the side wall portion is removed and a second conductivity type layer is formed through this opening at the junction between the first conductivity type layer and the substrate.
It is characterized by forming a barrier layer depending on the conductivity type deeper than the source/drain region.

Further, the step of forming the sidewalls may be performed before forming the source/drain regions.

〔Effect of the invention〕

The field effect semiconductor device according to the present invention can control the current flowing through the semi-insulating substrate under the active layer, which is the channel region, even when miniaturized. As a result,
Decrease in threshold voltage and increase in drain conductance due to shorter channels.

A high-performance field-effect semiconductor device can be obtained by preventing a decrease in mutual conductance.6 In addition, in the present invention, the barrier layer that suppresses substrate current has a small area in contact with the N intermediate layer, so that it can be easily used as a barrier. It is possible to secure the area necessary to fully demonstrate the effect. Therefore, the device and method of the present invention can realize a high-performance device, and when applied to an integrated circuit, high-speed operation and high integration are possible.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows an example of a GaAs-MESFET.

11 is semi-insulating Ga with a resistivity of about 10' to 101Ω・1
An n-type active layer 12 that becomes a channel region is formed on the surface of the As substrate, and a Schottky gate made of 4,000 tungsten nitride (vNX) is formed on the surface.
l[13 is formed. On both sides of the substrate with the gate electrode 13 in between, an n+ type source region 14 and a drain region 15, which are higher in concentration and deeper than the operation M12, are formed by ion implantation. These source/drain regions 14°15
At the boundary with the substrate 11 in the vicinity of the guard electrode, there is a p-type barrier that forms a high barrier against carrier injection (electron injection in this embodiment) from the source/drain region 14.15 into the substrate 11. Layers 16 and 17 are formed. 18 and 19 are source and drain electrodes, respectively.

An example of manufacturing such a MESFET is shown in Figure 2 (
This will be explained next with reference to a) to (e). First, Si ions were applied to a semi-insulating GaAs substrate 11 at 50 KeV and 2. O
The n-type operating layer 12 is formed by ion implantation under the condition of X 10''/at!.

Next, 4,000 VNx films were formed on this substrate, and a film of 1.0 was formed using known photolithography and dry etching techniques. Gate electrode 13 is formed.

Using this gate electrode as a mask, 18 Si ions were further applied.
Ion implantation is performed under the conditions of 0 KeV and 3 x 10"/al to form source/drain regions 14.15 (
Figure 2(a)) After this, plasma C is applied to the entire surface of the substrate.
A 4000 SiO□ film is deposited by VD, and the SiO film is etched by an amount corresponding to the film thickness by an anisotropic dry etching method such as IIIE. The 5iOzll'2 deposited by plasma CVD is isotropically deposited and the same film thickness is formed on the side walls of the gate electrode 13, so by etching the entire surface using anisotropic dry etching, it is selectively etched only on the side walls of the gate electrode 13. In general, the 5i02 film 20 can be left (FIG. 2(b)).

Next, a SiN film with a thickness of 40% is deposited on the entire surface of the substrate by plasma CVD.
The gate electrode, the Sin, and the sidewall surfaces are exposed by a planarization method and an etchback method using a known resist (FIG. 2(C)). Here, 21 is the remaining SiN film.

Next, the 5108 sidewall 2o is removed by selective wet etching using ammonium fluoride, and Zn ions, for example, are injected at 500KeV5X10 as a p-type impurity through this opening.
”/aJ (Fig. 2(d)).

Zn ions are also implanted into a part of the source/drain regions 14.15, but the implantation amount is smaller than that of SL, and the high-energy implantation results in a particularly low concentration on the surface side. - There is almost no increase in parasitic resistance due to a decrease in concentration in the drain regions 14 and 15. Further, a p-layer is also formed in a part of the junction between the active layer and the substrate due to lateral scattering due to ion implantation, but there is no problem for the same reason.

After that, the SiN film 21 is peeled off, and the implanted impurity is activated by annealing for 80 minutes using a capless method in a S atmosphere.
The self-line type Ga
The As-MESFET is completed (Fig. 2(e)).

The NHSFET according to this example and a conventional MESFET without a p-type barrier layer were fabricated under similar conditions and their performances were compared.
The shift amount of the threshold voltage when reduced to 400 for the conventional type
+mV, whereas in this example it was improved to 100mV. This value is slightly inferior in performance in this respect to the value 60+aV obtained in the example shown in FIG. However, the delay time per gate stage of the circuit configured with MESFETs according to this example is 35 ps, which is approximately 20% faster than the structure in which most of the periphery of n0 is surrounded by a p layer as shown in FIG. There is. This is because the capacitance relative to the substrate has decreased. Furthermore, compared to a conventional structure without a p-type barrier layer, the delay time is improved by as much as 40%. In addition, in the structure (Fig. 6) in which a shallow p is formed on a small part of the contact surface with the substrate around n10, the threshold voltage shift amount is 200 V and the delay time is 40 ps. Higher performance was obtained.

In the present invention, the ion implantation process for forming the source/drain regions 14 and 15 and the process for forming the sidewalls of the gate electrode described in FIGS. 3A and 3B can be reversed.

In that case, as shown in FIG. 3, the p-type region expands and becomes more effective as a potential barrier. According to this method, the accelerating voltage, dose, and ion species of ion implantation for forming the p-type layer are adjusted so that the p-type layer 16 is formed at the boundary between the n-type layer 12 and the substrate 11 in the channel region. Depending on the selection, it becomes possible to realize high-performance PET.

[Brief explanation of drawings]

FIG. 1 shows a GaAs-MESFET according to an embodiment of the present invention.
2(a) to 2(e) are diagrams for explaining the manufacturing process, and FIG. 3 is a diagram showing the GaAs-ME of another example.
Figures 4@, 5, and 6 showing SFETs are diagrams showing conventional GaAs-MESFETs. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAs substrate, 12... N-type operating layer, 13... Schottky gate electrode, 14...
n raw type source region, 15...n medium type drain region,
16.17...p-type barrier layer. 18... Source ff electrode, 19... Drain il!
Pole, 20...SiO□ film, 21...SiN film, 22
...N-type layer. Agent Patent Attorney Nori Ken Yudo Takehana Kikuozu 1 Figure 1 l Figure 2 Figure 2 Figure 3

Claims (4)

[Claims] (1) A semi-insulating compound semiconductor substrate, a first conductivity type active layer formed on the surface of this substrate, a gate electrode formed on this active layer, and the substrate surface with this gate electrode in between. a first conductivity type high impurity concentration source and drain region formed deeper than the active layer, at a boundary between the first conductivity type layer below the gate electrode side and the substrate;
A field effect semiconductor device characterized in that a barrier layer of a second conductivity type is formed deeper than a source/drain region. (2) The semi-insulating compound semiconductor substrate is semi-insulating GaA
2. The field effect semiconductor device according to claim 1, wherein the gate electrode is an S substrate and forms a Schottky barrier between the gate electrode and the active layer. (3) forming an active layer of the first conductivity type on the surface of the semi-insulating compound semiconductor substrate; forming a gate electrode on the active layer; After forming source and drain regions with impurity concentration and forming sidewalls on the gate electrode, another insulating film is formed, and after exposing the upper part of the gate electrode and sidewalls, the sidewalls are removed to form this part. A barrier layer of the second conductivity type is formed deeper than the source and drain regions at the junction between the first conductivity type and the substrate below the side of the gate electrode by forming an opening and implanting ions of another impurity. A method for manufacturing a field effect semiconductor device, comprising the steps of: (4) Manufacturing the field effect semiconductor device according to claim 3, wherein the step of forming the gate sidewall is performed before forming the source/drain region, and the source/drain region is formed using the gate electrode and the gate electrode sidewall as a mask. Method.