JP2732845B2 - Method for manufacturing MIS type field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention has an LDD (Lighty Doped Drain) structure
The present invention relates to a method for manufacturing an MIS type field effect transistor. [Summary of the Invention] The method of manufacturing the MIS type field effect transistor of the present invention comprises:
An MIS-type electric field in which at least the drain region of the semiconductor substrate comprises a high concentration region and a low concentration region, and the low concentration region comprises a first concentration region and a second concentration region having a higher concentration than the first concentration region. In the method for manufacturing an effect transistor, a step of introducing an extremely low concentration of impurities using a gate electrode formed on a semiconductor substrate as a mask, and forming a first insulating film at least on the side wall of the gate electrode; Introducing a low-concentration impurity using the insulating film as a mask, forming a second insulating film on the first insulating film, and further etching to leave a second insulating film on the gate electrode side wall; Introducing a high-concentration impurity using the mask as a mask, wherein the second concentration region is formed deeper in the depth direction of the semiconductor substrate than the first concentration region, and the first concentration region is Above Intended to obtain a low concentration region of gate electrode overlaps the structure, thereby, high integration,
It is intended to obtain a highly reliable MIS type field effect transistor. [Prior art and its problems] In the field of transistors in recent years, for example, as the design rules of VLSI have become more and more miniaturized, the internal electric field strength of the element has inevitably increased. Along with this,
The problem of the short channel effect has arisen. For example, in the saturation operation state of an n-channel MOS transistor, if electrons flow through the channel and the drain electric field is sufficiently high,
Ionizing collisions occur in the depletion layer near the drain, causing electrons and
Hole pairs are generated. Among the electrons generated here, electrons having sufficient energy to exceed the potential barrier between the semiconductor substrate and the gate insulating film, which is an insulating film, become hot electrons and penetrate into the gate insulating film. Such electrons cause fluctuations in threshold voltage, deterioration in conductance, and the like, and reduce the reliability of the semiconductor device. Such a phenomenon becomes more conspicuous as the channel length becomes shorter. In order to solve the above problems, a so-called LDD structure has been proposed in which a low-concentration region is provided near the drain to reduce the electric field intensity near the drain. Conventional L
Regarding the technology of the DD structure, for example, supervision of Takuo Sugano, edited by Susumu Kayama, super-high-speed digital device series "2.
Device "(Baifukan). Hereinafter, the related art will be specifically described with reference to the drawings. FIG. 6 is a diagram showing a cross-sectional structure of a conventional MIS field-effect transistor. 7 (a) to 7 (e) are views for explaining an example of a method for manufacturing the conventional MIS field effect transistor shown in FIG. In these figures, 1 is a semiconductor substrate made of, for example, Si, 2 is a gate insulating film made of, for example, SiO ₂ , 3 is, for example,
Isolation insulating film made of SiO _2, a gate electrode is made of, for example, poly-Si 4, 5, for example a first insulating film made of SiO _2,
Reference numeral 6 denotes a low-concentration region, reference numeral 7 denotes an insulating film made of, for example, SiO _2, and reference numeral 7a denotes a second insulating film, which is a portion remaining after an unnecessary portion of the insulating film 7 is removed. Reference numeral 8 denotes a high concentration region, 9 denotes an interlayer insulating film made of, for example, SiO ₂ , and 10 denotes a wiring layer made of, for example, Al. Here, the source / drain region includes a high concentration region 8 and a low concentration region 6. Next, the manufacturing process will be described. First, as shown in FIG. 7A, an element isolation insulating film 3 is formed on a semiconductor substrate 1 by thermal oxidation. Next, after depositing poly-Si on the entire surface by, for example, CVD, the gate electrode 4 is formed by photo-etching. Next, as shown in FIG. 7 (b), after depositing SiO ₂ over the entire surface by, eg, CVD to form a first insulating film 5, a low concentration impurity (eg, p ⁺ ) is introduced by ion implantation. Thus, a low concentration region 6 is formed. Next, as shown in FIG. 7C, an insulating film 7 is formed by depositing SiO ₂ on the entire surface by, for example, CVD. Next, as shown in FIG. 7D, the insulating film 7 is selectively etched by anisotropic etching to form a second insulating film 7a on the side wall of the gate electrode 4, and then the second film is formed by ion implantation. High-concentration impurities (for example,
As ⁺ ) is introduced to form the high concentration region 8. Then, for example, by depositing SiO ₂ on the entire surface by CVD to form an interlayer insulating film 9, the wiring layer 10 is formed so as to make contact with the high-concentration region 8, so that the MIS as shown in FIG. Type field effect transistor is completed. As described above, the use of the LDD structure can prevent the drain current from decreasing over time. Specifically, the low-concentration region 6 of the LDD structure may be adjusted and optimized. As means therefor, there is firstly a means for reducing the injection amount of hot electrons injected into the gate insulating film 2 from the high electric field region near the drain region. This includes reducing the dose amount of the low concentration drain region 6 to 3 × 10 ¹³ cm. ^Although it is better to set it to about ^-3 , this does not mean that hot electrons are not injected into the gate oxide film, and the injected electrons generate fixed charges and lower the channel conductance (drain current Lower). This decrease is an initial deterioration mode, and is a problem peculiar to the LDD structure, and the initial deterioration is larger than that of the conventional drain structure. To prevent this initial deterioration, it is necessary to increase the carrier concentration in the drain region so as not to lose the charge generated in the gate insulating film 2. Specifically, the optimum value of the dose amount of the drain region is set to about 5 × 10 ¹³ cm ⁻² .
However, when the dose is increased, for example, the low-concentration region 6 diffuses sideways (diffuses in the lateral direction) during annealing and goes around to the lower portion of the gate electrode 4, which is disadvantageous for forming a short channel. The problem of punch-through occurs. Therefore, there is a problem that high integration and high reliability cannot be obtained. [Object of the Invention] The present invention has been made to solve such a problem, and can be optimized so as to minimize the amount of hot electrons injected into the gate insulating film. It is an object of the present invention to provide a method for manufacturing a MIS field-effect transistor which can be optimized to minimize the decrease in channel conductance due to electrons and can prevent source / drain puncture through due to side diffusion in a low concentration region. [Means for Solving the Problems] According to a method of manufacturing an MIS field-effect transistor of the present invention, at least a drain region of a semiconductor substrate includes a high-concentration region and a low-concentration region. In a method for manufacturing a MIS field-effect transistor comprising a region and a second concentration region having a higher concentration than the first concentration region, an extremely low concentration impurity is introduced using a gate electrode formed on a semiconductor substrate as a mask. Forming a first insulating film on at least the side wall of the gate electrode, introducing a low-concentration impurity using the first insulating film as a mask, and forming a second insulating film on the first insulating film. Forming an insulating film, further leaving a second insulating film on the side wall of the gate electrode by etching, and introducing a high-concentration impurity using the second insulating film as a mask. concentration With deep formed in the depth direction of the semiconductor body than the frequency, the first doped region is characterized in that to obtain a low-concentration region of the gate electrode and the overlapping structure. The configuration of the present invention will be described below using an embodiment of the present invention described in detail below. That is, in the method of manufacturing the MIS field-effect transistor of the present invention, at least the drain region of the semiconductor substrate 1 includes a high-concentration region 8 and a low-concentration region 6 as illustrated in FIG.
The low density region 6 is a first density region (extremely low density region 6a).
When manufacturing an MIS field-effect transistor comprising a second concentration region (low concentration region 6b) having a higher concentration than the first concentration region 6a, as shown in FIGS. 3 (a) to 3 (d), ,
Using the gate electrode 4 formed on the semiconductor substrate 1 as a mask, an extremely low concentration impurity (p ^{+ in the} embodiment) is introduced (FIG. 3 (a)), and at least Forming a first insulating film on a side wall of the gate electrode;
Low concentration impurities (in the embodiment,
p ⁺⁾ was introduced and then, as shown in FIG. 3 (c), the second insulating film 7 is formed on the first insulating film 5, a further side wall of the gate electrode 4 by etching 2 insulating film
As shown in FIG. 3 (d) while leaving 7a, using this second insulating film 7a as a mask, high-concentration impurities (A in the embodiment)
s ⁺ ), whereby the second concentration region (low-concentration region 6b) is divided into the first concentration region (extremely-low-concentration region) as illustrated in FIG. 1 and more specifically in FIG. While being formed deeper in the depth direction of the semiconductor substrate 1 than the region 6a),
The first concentration region (extremely low concentration region 6a) is for obtaining a low concentration region 6 having a structure overlapping with the gate electrode 4. [Operation] In the present invention, as shown in FIG. 1, the extremely low-concentration region 6a formed in the drain region
The electric field of 6a is relaxed, and the injection amount of hot electrons injected into the gate insulating film 2 can be reduced. Further, as shown in FIG. 1, the low-concentration region 6b formed in the drain region can reduce the amount of decrease in channel conductance due to hot electrons injected into the gate insulating film 2, thereby reducing the low-concentration region 6b. If formed by appropriately adjusting (adjusting the amount of toe), optimization can be made to minimize the initial deterioration due to the injection amount of hot electrons. Further, the low-concentration region 6 is defined as an extremely low-concentration region 6a and a low-concentration region 6b.
Therefore, the dose in the low-concentration region 6 can be made smaller than that in the conventional device shown in FIG. Problem is eliminated. Further, since the low-concentration region 6b is formed deeper in the depth direction of the semiconductor substrate 1 than the extreme-concentration region 6a, hot carriers are less likely to be generated, and hot carrier resistance is improved. Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. Note that, needless to say, the present invention is not limited to the embodiments described below. FIG. 1 is a diagram showing a cross-sectional structure of an example of a transistor structure obtained by a method of manufacturing an MIS field-effect transistor according to the present invention, and FIG. 2 is a diagram showing details of the LDD structure. In these figures, FIG. 6 or FIG.
The same reference numerals as in (d) indicate the same or corresponding parts, 6a is an extremely low density area, and 6b is a low density area. Here, the low-concentration region 6 includes an extremely low-concentration region 6a and a low-concentration region 6b. Further, the source / drain region is composed of a high concentration region 8 and a low concentration region. 3 (a) to 3 (d) are diagrams for explaining one embodiment of a method of manufacturing the MIS field effect transistor according to the present invention. In this figure, the same or corresponding parts as those in FIGS. 1 and 5 (a) to (d) are shown. Next, the manufacturing process will be described. First, as shown in FIG. 3A, after an element isolation insulating film 3 is formed on a semiconductor substrate 1 by thermal oxidation, a gate insulating film 2 is formed by thermal oxidation. Next, after depositing poly-Si on the entire surface by, for example, CVD, the gate electrode 4 is formed by photo-etching. Next, an extremely low concentration of impurities (for example, using the gate electrode 4 as a mask by ion implantation)
p ⁺ ) is introduced to form the extremely low concentration region 6a. At this time, the dose is preferably, for example, about 1 × 10 ¹³ cm ⁻² , which is considered to reduce the electric field near the drain. This corresponds to the step of introducing an extremely low-concentration impurity using the gate electrode formed on the semiconductor substrate as a mask according to the present invention. Next, as shown in FIG. 3B, SiO ₂ is deposited on the entire surface by, eg, CVD to form a first insulating film 5 having a thickness of about 1000 °, and then the first insulating film 5 is formed by ion implantation. The low concentration region 6b is formed by introducing a low concentration impurity (for example, p ⁺ ) as a mask. At this time, the ion implantation is performed on the gate electrode 4.
From a distance of 1000 mm from The dose is preferably, for example, about 7 × 10 ¹³ cm ^−2, and it is considered that the influence of the charge trapped in the gate insulating film 2 is eliminated. Next, as shown in FIG. 3C, an insulating film 7 is formed by depositing SiO ₂ on the entire surface by, for example, CVD. Next, as shown in FIG. 3D, the insulating film 6 is selectively etched by anisotropic etching to form a second insulating film 7a on the side walls of the gate electrode 4, and then the second insulating film 7a is formed by ion implantation. Using the insulating film 7a as a mask, a high concentration impurity (for example, As ⁺ ) is introduced to form a high concentration region 8. This forms a second insulating film on the side wall of the gate electrode of the present invention,
This corresponds to the step of introducing high-concentration impurities using the insulating film as a mask. Then, for example, SiO ₂ is deposited on the entire surface by CVD to form an interlayer insulating film 9. Next, the wiring layer 10 is moved to the high concentration region 8.
The MIS field effect transistor as shown in FIG. 1 is completed. That is, in the above embodiment, the extremely low concentration region 6a is formed in the drain region.
Is formed, the electric field in the extremely low-concentration region 6a is reduced, and optimization can be performed to minimize the amount of hot electrons injected into the gate insulating film 2. In the above embodiment, since the low-concentration region 6b is formed in the drain region, the electric field to the channel region due to the hot electrons injected into the gate insulating film 2 can be reduced, and the low-concentration region 6b is appropriately adjusted (dose). (Adjustment of the amount), it is possible to optimize so as to minimize the deterioration of the channel conductance. In the above embodiment, the low-concentration region 6 is replaced with the extremely low-concentration region 6a.
And the low-concentration region 6b, the dose of the low-concentration region 6 can be made smaller than that of the conventional device shown in FIG. The problem of punch-through between drains is eliminated. In the above embodiment, the low-concentration region 6 is replaced with the extremely low-concentration region.
Although a case has been described in which the low density region 6c is composed of two regions having different densities, that is, the low density region 6c, the present invention is not limited to this. And may be formed of three or more regions having different densities. In the above embodiment, as shown in FIG. 3B, the case where the low concentration region 6b is formed by ion implantation through the first insulating film 5 and the gate insulating film 2 has been described. Even if the low-concentration region 6b is formed directly by ion implantation into the semiconductor substrate 1 as shown in FIG. 4, the first region is formed only on the side wall of the gate electrode 4 as shown in FIG. The low concentration region 6b may be formed directly by ion implantation into the semiconductor substrate 1 while leaving the insulating film 5. [Effects of the Invention] As described above, according to the present invention, the amount of hot electrons injected into the gate insulating film can be optimized to be minimized, and the channel conductance due to the electrons injected into the gate insulating film can be reduced. Can be optimized to minimize, and the source /
Drain punch-through can be prevented. Therefore, there is an effect that a highly integrated and highly reliable MIS transistor can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a transistor structure obtained by one embodiment of a method for manufacturing an MIS field-effect transistor according to the present invention, and FIG. 2 is a view showing details of an LDD structure of the example. FIG. 3 is a view for explaining one embodiment of the method of manufacturing the MIS field-effect transistor of the present invention, and FIGS. 4 and 5 are diagrams of the present invention.
FIG. 11 is a diagram for explaining another embodiment of the method for manufacturing the MIS field-effect transistor. FIG. 6 is a cross-sectional view showing a structure of an example of a conventional MIS field-effect transistor, and FIG. 7 is a view for explaining an example of a method of manufacturing a conventional MIS field-effect transistor. 1 ... Semiconductor substrate, 4 ... Gate electrode, 5 ... First insulating film, 6 ... Low concentration region, 6a ... Ultra low concentration region, 6b ...
Low concentration region, 7a: second insulating film.

Claims (1)

(57) [Claims] An MIS-type electric field in which at least the drain region of the semiconductor substrate comprises a high concentration region and a low concentration region, and the low concentration region comprises a first concentration region and a second concentration region having a higher concentration than the first concentration region. A method of manufacturing an effect transistor, a step of introducing an extremely low concentration impurity using a gate electrode formed on a semiconductor substrate as a mask, forming a first insulating film on at least the side wall of the gate electrode, Introducing a low-concentration impurity using the insulating film as a mask, forming a second insulating film on the first insulating film, and further etching to leave a second insulating film on the side wall of the gate electrode; Using the mask as a mask to introduce a high-concentration impurity, wherein the second concentration region is formed deeper in the depth direction of the semiconductor substrate than the first concentration region, and the first concentration region is the above A method for manufacturing an MIS type field effect transistor, characterized in that a low concentration region having a structure overlapping with a gate electrode is obtained.