JPH041505B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate (IG) static induction transistor, and more particularly to an insulated gate (IG) static induction transistor (SIT) with sufficiently reduced gate capacitance and a semiconductor memory using the same. Concerning integrated circuits.

Conventional field effect transistors, both junction type and insulated gate type, have exhibited saturation type current-voltage characteristics in which the drain current gradually saturates as the drain voltage increases.

On the other hand, a static induction field effect transistor (hereinafter referred to as SIT) in which the drain current continues to increase as the drain voltage increases was invented by the present inventor (Patent No. 968336), and various developments have been made since then. (Patent No. 968337, etc.). SIT has the following characteristics compared to conventional field effect transistors (hereinafter referred to as FETs).

(1) In at least a part of the main operating region, there remains a state in which there is no punch-through between the source and drain, that is, a state in which there is no depletion state between the source and gate, and a carrier injection state exists, and furthermore, from the source to the pinch-off point By having the impurity density and various dimensions selected so that the product of the series resistance r _s and the specific (true) conversion conductance G _n is less than 1, the current-voltage characteristics exhibit unsaturated characteristics. .

(2) Since the current-voltage characteristics exhibit unsaturated characteristics, it can be used as a high input impedance, low output impedance element, and the apparent conversion conductance G _n can be increased and distortion can be reduced.

(3) A large output current can be obtained, and the withstand voltage can also be increased by using a high-low resistance layer in a predetermined region, and a large output device with a large current and a high withstand voltage can be obtained.

(4) Since the density of the gate region can be made high and the gate shape can be made small, it is possible to reduce parasitic capacitance between electrodes and gate resistance. Speeding up the process.

(5) In SIT, where the channel is almost covered by the depletion layer extending from the gate, the gate voltage range is extremely wide, and the current-voltage characteristics almost follow an exponential law, not only in the low current region. Due to the effects of the series resistance r _s and drain resistance R _d , the characteristics deviate from the exponential law and become almost linear over an extremely wide current range, including a large current range, in some cases over 10 orders of magnitude. Ability to operate with extremely low distortion, such as by keeping the amplification coefficient almost constant.

(6) Since the amplification coefficient can be kept almost constant even when the current value is extremely small, it is possible to
Ability to perform extremely excellent switching operations under low power consumption conditions.

(7) Thermal runaway does not occur because the temperature characteristics in the large current state can be made negative. Also, it is possible to design a structure that has almost no temperature characteristics.

(8) The amplification factor can be kept constant over an extremely wide operating temperature range, for example over 200°C.

(9) By narrowing the channel width and lowering the impurity density in the channel, it is possible to achieve high-speed enhancement, in which almost no current flows when the gate voltage is zero, and current only flows when a forward voltage is applied to the gate. Ability to perform mode switching operations.

In other words, SIT is superior in all aspects such as high power, high withstand voltage, large current, low distortion, low noise, low power consumption, and high speed operation. Transistors have many advantages over other transistors. Its excellence has already been demonstrated both as an individual element and as an element for integrated circuits.
It is opening up new fields of application in various fields.

In particular, when applied to integrated circuits, the high input impedance allows for high integration without the need for drive current, and the unsaturated current-voltage characteristics and large conversion conductance allow for high fan-out. It has the advantage of being able to obtain a large amount of

An example of the current-voltage characteristics of junction type SIT is shown in Figure 1a,
Shown in b. At a gate voltage of 1 to 2 V or higher, at which the channel is pinched off by the gate voltage alone, the drain current I _d almost follows an exponential law in the low current state for both the gate voltage V _g and the drain voltage V _d . As the current increases and the negative feedback effect of the series resistance begins to take effect, the exponential law deviates from the law. The reason why regions of large current are indicated by dotted lines in FIG. 1b is that the results are shown by pulse measurement to avoid temperature rise.

Enhancement mode (E mode) or enhancement mode and depression mode (D mode)
The basic structure of an insulated gate type electrostatic induction transistor that operates in the present invention has already been clarified by the inventor of the present invention in his application entitled "MOS, MIS electrostatic induction field effect transistor" filed on January 11, 1972. Specifically, five types of structures are proposed as means for creating a potential barrier near the source region by weakening the influence of gate voltage, including the diffusion potential, near the source. That is, (1) gate electrode (metal such as Al or low resistance semiconductor such as polysilicon)
(2) A structure in which the insulating layer near the source region is partially thickened; (3)
(4) a structure in which the gate electrode metal near the source region is a different metal; (4) a structure in which a part of the insulating film under the gate electrode near the source region is made of a material with a low dielectric constant; and (5) a channel. This is a structure in which the impurity density is partially high near the source region.
These structures may be incorporated as planar structures, or may be formed on the sides of a notch (V-shaped, U-shaped, etc.) provided on the semiconductor surface. In any case, a potential barrier is generated in front of the source in the channel in the main operating region, resulting in a majority carrier injection amount control operation, and unsaturated current-voltage characteristics are exhibited. However, in these structures, the gate electrode extends almost from the source region to the drain region, and the gate capacitance (capacitance between the gate and substrate) of conventional MOSFETs is large, and the gate electrode extends from the source region to the drain region. The drawbacks such as slow operation speed due to large capacitance between the gate and low breakdown voltage between the gate and drain, which is not suitable for high voltage operation, have not been completely overcome, and low power consumption in junction type SIT has not been completely overcome. However, the characteristics of high-speed operation, high voltage, and high power operation were not always fully demonstrated.

The purpose of the present invention is to provide the above-mentioned insulated gate (IG) SIT
The present invention aims to overcome the drawbacks of the present invention by providing an insulated gate static induction transistor having a structure that has low gate capacitance and gate-drain capacitance, high gate-drain breakdown voltage, and can operate at low power and high speed. At the same time, it is an object of the present invention to provide a semiconductor integrated circuit using such an insulated gate static induction transistor that operates at low power and at high speed.

The present invention will be described in detail below with reference to the drawings.

In order to reduce the gate capacitance in IGSIT, it is natural to either reduce the area of the gate electrode existing on the channel or increase the thickness of the insulating layer under the gate electrode.
If the insulating film is made thicker, the voltage applied to the gate (threshold voltage) necessary to create an inversion layer and make the channel conductive becomes higher, which is not desirable in terms of operating characteristics. The only remaining method is to make the gate electrode smaller. FIG. 2 shows a cross-sectional view of one embodiment of an n-channel type structure with a sufficiently small gate capacitance.

In FIG. 2, n ⁺ regions 51 and 54 are a source region and a drain region, respectively, and the impurity density is 10 ¹⁷ ~
It is about 10 ²¹ cm ^-3 . The p region 52 becomes a channel portion that controls the amount of electrons injected from the source to the drain side, and its impurity density is approximately 10 ¹⁴ to ^{10 20} cm ⁻³ depending on the channel length. The impurity density in this region is selected so that there is no punch-through between the source and drain in the main operating region, that is, the entire region is not covered by a depletion layer extending from the drain. Moreover, its length is from several 100 Å to several μm. The p ^- region 53 is a low impurity density region, and has such dimensions and impurity density that the entire p ^- region becomes a depletion layer just by the diffusion potential with the drain region 54 . For example, the impurity density is
The impurity density is approximately 10 ¹¹ to 10 ¹⁶ cm ^-3 , and the longer the distance from the channel to the drain region, the lower the impurity density must be. 55 is SiO ₂ , Si ₃ N ₄ ,
This is an insulating layer such as Al ₂ O ₃ or a combination of two or more of these. 51' and 54' are source and drain metal electrodes, respectively. Reference numeral 56 denotes a gate electrode, which may be made of a metal such as Al or a low resistivity semiconductor such as polysilicon. However, when the channel becomes very short and the gate electrode becomes thin, the time constant determined by the gate electrode's resistance and gate capacitance limits the operating speed, so a metal electrode is recommended. This is desirable, and the thicker the metal, the lower the resistance. The thickness of the insulating layer under the gate electrode varies depending on the channel length and operation mode (E mode or E/D mode), but is about 100 Å to 1000 Å. If the material is the same and the channel length is the same, E
When operating in mode, the thickness of the insulating layer is E/D
Slightly thicker than when operating in mode. A certain positive voltage is applied to the drain electrode, and a positive voltage is further applied to the gate electrode so that the p
When the potential near the surface of the region is lowered, electrons are injected across this potential barrier into the p ^- layer, which has become a depletion layer, and the p ^- layer drifts due to the electric field and flows to the drain region. Therefore, in this structure, the flowing current is mostly determined by the amount of electrons injected into the drain side, so there is a negative feedback effect due to the series resistance rs from the source to the potential barrier, and a negative feedback effect from the potential barrier to the drain. In the current region where the voltage effect of the drain resistance is not significant, the drain current is proportional to the gate voltage.
The drain current flows almost according to an exponential law for both Vg and drain voltage Vd. If the impurity density of the p-region, which becomes a channel, is distributed near the surface so that it gradually decreases from the surface to the inside, the inversion layer, which becomes a channel, becomes wider, the series resistance decreases, and the rise of the current becomes steeper. The same is true for the p ^- region on the drain side.
If the impurity density decreases from the surface to the inside, the injected electrons will spread out more and flow, reducing the drain resistance. Although the gate capacitance is sufficiently small with the structure shown in Figure 2, there is another insulated gate (IG)
The source-to-substrate capacitance and drain-to-substrate capacitance, which are major factors that reduce the operating speed of SIT, have hardly decreased. Of course, when using the source and substrate at the same potential, the capacitance between the source and the substrate does not affect the operation.If the drain and the substrate are at the same potential, the capacitance between the drain and the substrate does not affect the operation, but when the source and the substrate Since the potential of at least one of the drain and the drain fluctuates, its capacitance limits the operating speed. A structure for reducing the drain-to-substrate capacitance is shown in FIG. That is, p which should be the channel
Region 62 is formed only around source region 61 . Its thickness is the same as in Figure 2.
It is determined together with the impurity density to prevent punch-through between drains. The thickness and impurity density of p region 62 are determined in relation to the impurity density and thickness of p ^- region 63. Thickness W ₂ of p region 62, impurity density N _A2 , thickness W ₁ of p ^- region 63,
Assuming that the impurity density N _A1 is the typical voltage applied to the drain, V _D , and the diffusion potential Vbi, the conditions for preventing punch-through between the source and drain are: V _D + VbiqN _A1 W ₁ ² /2ε +qN _A2 W ₁ ² /2ε + qN _A2 It is approximately given by W ₁ W ₂ /ε. n ⁺ region 64 is the drain, 6
6 is a gate electrode. The impurity density etc. of each region are the same as in the case of FIG. 2. drain region 6
Since 4 is in contact with the p ^- region 63, the depletion layer spreads sufficiently into the p ^- region 63, and the capacitance between the drain and the substrate can be made very small. In the structure shown in FIG. 3, if the drain voltage changes rapidly, the change in the width of the depletion layer in the p ^- layer cannot be followed, causing power consumption. Therefore, in the case of very high-speed operation, a p ^- region 67 is further provided below the p-region as shown in FIG. It is sufficient if the number reaches 67. The impurity density of p-region 67 is sufficiently higher than that of p ^- region 63, and is 10 ¹⁵ to 10 ²⁰ cm.
It is about ^-3 . FIG. 5 shows an example of a structure in which the source region is extended toward the drain side by ion implantation or the like. The impurity density and operation are almost the same as in FIG. Similarly to Fig. 3, if the delay in the change in the drain depletion layer width limits the operating speed,
It is sufficient to provide a p region 77 as shown in the figure so that the depletion layer from the drain reaches the p region 77 under most operating conditions. In either structure, the impurity density and dimensions are selected so that the p ^- region from the drain to the channel becomes a depletion layer with only a diffusion potential. Of course, the structure in which the capacitance is reduced by reducing the area of the gate electrode is not limited to this. It may be a p-channel in which the conductivity type is completely reversed, and the shapes of the source, gate, and drain and the shape of the channel are, of course, not limited to these, and there are various modifications.

Examples of the cross-sectional structure of a vertical IG SIT in which the gate capacitance is sufficiently reduced by reducing the gate electrode area are shown in FIGS. 7 to 10 using an n-channel as an example.

In FIG. 7, n ⁺ regions 81 and 84 are sources, respectively.
A p region 82 is a region to be a channel, a p ⁻ region 83 is a region which becomes a depletion layer only by a diffusion potential, 85 is an insulating layer, and 86 is a gate electrode. The impurity density etc. are the same as in the case of the planar type described above. When an inversion layer begins to form due to the gate electrode, a drain current begins to flow. In Fig. 7, the gate-source capacitance tends to increase, but Fig. 8 shows an example in which this has been improved. It is the same as Figure 7. FIG. 9 shows an example in which the source is arranged on the substrate side. n ⁺ area 101,
104 are the source, drain, and p region 10, respectively.
The area where 2 should be the channel, p ^- area 103
105 is an insulating layer, and 106 is a gate electrode. FIG. 10 shows an example in which the V-shaped structure in FIG. 9 is changed to a U-shaped structure.
The principle is the same as that in FIG. 9 except that the gate electrode 116 is divided into two parts. Of course, the two gate electrodes may be connected as long as the capacitance between the source and the gate becomes somewhat large. In Figures 7 to 10, when the source and drain face each other over a wide area and the distance between the source and drain is shortened for the purpose of high-speed operation, the capacitance between the source and drain tends to increase. This is a factor that limits high-speed operation. To overcome this difficulty, either the source or the drain can be made smaller. Examples are shown in FIGS. 11-13.

FIGS. 11 and 12 show cases in which the source regions are made smaller in the structures shown in FIGS. 7 and 8. In FIG. 11, n ⁺ regions 121 and 131 are sources,
124 is a drain, p regions 122 and 132 are regions that become channels, p ^- region 123 is a region that becomes a depletion layer only by diffusion potential, 125 is an insulating layer, and 12
6 and 136 are gate electrodes, and 121' and 132' are source and metal electrodes, respectively. FIG. 12 shows an example in which the V-shaped cut reaches up to n ⁺ of the substrate, and the rest is the same as FIG. 11. FIG. 13 shows an example in which the drain shown in FIG. 9 is formed in a small region 164. By configuring as shown in FIGS. 11 to 13, it is possible to keep various capacitances sufficiently small and create an IG SIT capable of high-speed operation. Figures 7 to 1
Of course, the structure shown in FIG. 3 is not limited to this, and the cut is not limited to the V-shape or U-shape. Of course, it is possible to use a p-channel whose conductivity type is completely reversed, and it is also easy to use a multi-channel type having a large number of channels. If high power operation is desired, the p ^- region from the drain to the channel may be made long to ensure sufficient breakdown voltage. Also, at this time, it is okay to apply a certain amount of drain voltage so that the entire p ^- region becomes a depletion layer, so the diffusion potential alone is not sufficient.
The length and impurity density of the entire p ^- region may be selected so as not to form a depletion layer. Furthermore, in such a case, even if the gate electrode protrudes considerably over the p ^- region, the p ^- region eventually becomes a depletion layer in most operating conditions, so the capacitance hardly increases. Of course, when used for low-power, high-speed switching in integrated circuits, etc., it is often more advantageous to form a depletion layer in the entire region without applying a drain voltage, since current flows with a small drain voltage. However, in order to allow the desired current to flow only after a certain amount of drain voltage is applied, the p ^- region may be designed so that a region that does not become a depletion layer with only the diffusion potential remains.
If the channel length is short, the insulating layer under the gate electrode is thin, and the dielectric constant is set high, most of the voltage applied to the gate will be applied to the semiconductor region that becomes the channel, and the voltage will be applied to the drain beyond the potential barrier. The amount of carriers injected into the side is quite similar to that of a bipolar transistor.

The present invention operates at such low power and high speed.
If IG SIT is used as a semiconductor storage device,
Its performance can be further improved. A specific example is shown below.

FIGS. 14 and 15 are examples of dynamic RAM memory cells using the IG SIT of the present invention.

FIG. 14 shows a memory cell that uses one IG SIT 303 to store memory in a capacitor C 304. 30
1 is the write/read address line (column line), 3
02 is a data line (row line) for writing and reading. Writing and reading speeds are almost given by C/G _n , where G _n is the conversion conductance of IG SIT. Since G _n of the IG SIT of the present invention can be set to a value quite close to that of a bipolar transistor,
Writing and reading can be performed at least an order of magnitude faster than memory cells using MOS FETs. 1st
Figure 5 shows three SITs of the present invention, 315, 316,
It is a memory cell using 317, and 311, 31
2 is write and read address line, 313,3
14 is a data read line and a write line. In this circuit, the memory is stored in the gate capacitance of the SIT 316, so it is desirable that the gate capacitance of the SIT 316 is large.Also, since the gate capacitance of the SIT 316 does not significantly affect the operating speed, a conventional IG SIT may be used.
An IG FET may also be used.

Figure 16 shows the IG SIT of the present invention.
This is an example of application to RAM memory cells.

321 is an address line, 322 is a data read line, 323 is a data write line, 324 to 32
9 is the IG SIT of the present invention. In particular, for the SITs 324, 325, 328, and 329 that determine the operating speed, each capacitance such as the gate capacitance is preferably set to be small, and gm is also set to be large. 326,3
27 may be a conventional SIT or a conventional MOS FET. With the configuration shown in FIG. 16, write and read speeds can be performed that are about one order of magnitude faster than those conventionally configured with MOS FETs. Of course, the circuit configuration of the RAM is not limited to these. Further, although the circuit is constructed mainly using an n-channel SIT, it goes without saying that a p-channel may also be used. FIG. 17 shows an example of a static RAM memory cell in which the IG SIT of the present invention is constructed in a complementary manner. 16th
Compared to the one shown in the figure, power consumption is extremely low due to the complementary configuration, and has been reduced to about 1/10. 331 is an address line, 332 is a data read line, 333 is a data write line, 334
339 are IG SITs of the present invention.

The SIT of the present invention is not limited to such RAM.
It can be applied to ROM (Read Only Memory), shift registers, and nonvolatile memories equipped with floating gates.

The IG SIT described above and the memory integrated circuit using the same can all be manufactured using conventionally known crystal technology, diffusion technology, ion implantation technology, and microfabrication technology.

In the IG SIT of the present invention, a gate electrode is formed via an insulating layer on a narrow semiconductor region that is to become a channel near the source, and the region from the channel to the drain is a high resistivity region that is essentially a depletion layer. The carrier is drifting. With this configuration, the gate capacitance can be made sufficiently small, the drain-to-substrate capacitance can be made sufficiently small, and the conversion conductance can be made large, so that the device operates at extremely low power and high speed. Coupled with the fact that its manufacture is not so complicated, it brings about a very significant performance improvement when applied to storage devices, and its industrial value is very large.

[Brief explanation of drawings]

1a and 1b are operational characteristic diagrams of an example of a structure of a static induction transistor, FIGS. 2 to 6 are sectional views of a planar structure of an IG SIT according to an embodiment of the present invention, and FIGS. FIG. 10 is a cross-sectional view showing the structure of a notched gate type IG SIT according to an embodiment of the present invention, and FIGS. 11 to 13 are cross-sectional views showing the structure of a notched gate type IG SIT according to other embodiments of the present invention. Figures 14 and 15 are circuit diagrams of an example of a dynamic RAM memory cell configured with IG SIT, and Figure 16 is a circuit diagram of an example of a dynamic RAM memory cell configured with IG SIT.
A circuit diagram of an example of a RAM memory cell, FIG. 17 is an example of a complementary IG SIT static RAM memory cell.
FIG. 3 is an example circuit diagram.

Claims (1)

[Claims] 1. Providing an opposite conductivity type region adjacent to a source region consisting of a high impurity density region at least in part at the intersection of a matrix consisting of a required number of address column lines and a required number of write/read row lines; Further, the high resistance regions of the opposite conductivity type and the same conductivity type are arranged adjacent to a drain region made of a highly impurity region of the same conductivity type as the source region, and the opposite A gate electrode is provided almost localized in a conductivity type region, and the high resistivity opposite conductivity type region is always depleted due to the diffusion potential of the drain region and the high resistivity opposite conductivity type region, resulting in unsaturated current-voltage characteristics. A memory cell including at least one insulated gate static induction transistor whose impurity density and various dimensions are selected to exhibit the A semiconductor memory device characterized in that at least a portion of the semiconductor memory device includes a portion configured to be connected to the column line.