JPS5936960A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce consumed power and make the action speedy by a method wherein a gate electrode is provided on the surface of a part close to the source via an insulator film, and a region of reverse conductivity type of high resistivity is always made into a depletion layer in a region of the main action. CONSTITUTION:A memory cell including an electrostatic induction transitor is arranged in the intersection of a matrix composed of the matrix line of an address column line and a write-read row line. The region 52 of reverse conductivity type is provided adjacent to the source region 51 composed of a region of high impurity density. The region 53 of high resistivity of the same conductivity type as the reverse conductivity type is interposed between the drain region 54 composed of the region of impurity density of the same conductivity type as the region 51. The gate electrode 56 is provided on the surface of the part close to the source via the insulator film 55. The region 53 always becomes a depletion layer in the main action, and the impurity density and various dimensions are selected so as to show the characteristic of unsaturated current- voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate type (IG) static induction transnoster, and in particular to an insulated gate type (IG) static induction transistor (SIT) with a sufficiently small gate capacitance (1+t) and its use. The present invention relates to semiconductor memory integrated circuits.

Conventional field effect transistors, both junction type and insulated gate type, exhibit saturation type current-voltage characteristics that gradually saturate as drain current or drain voltage increases.

On the other hand, a static induction field effect transistor (hereinafter referred to as SIT) in which the drain current continues to increase as the drain voltage increases was invented by the present inventor 4=hk (Patent No. 9683'36), and subsequently various It has been developed (Patent No. 968337, etc.). SIr has the following characteristics compared to conventional field effect transistors (hereinafter referred to as FETs).

1) In at least a portion of the main operating region, the source,
There remains a state in which there is no punch-through between the drains, that is, a state in which there is no depletion state between the source and gate, and a carrier injection state exists.Moreover, there is a series resistance r from the source to the pinch-off point, and an inherent (true) conversion conductance. G.

The impurity density and various dimensions are selected such that the product of is less than 1, and the current-voltage characteristics exhibit unsaturated characteristics.

2) Since the current-voltage characteristics exhibit unsaturated characteristics, it can be used as a commercial impedance and low output impedance element, and moreover, the apparent conversion conductance CT□ can be increased and the distortion can be reduced.

3) It is possible to obtain a large output current, and to increase the withstand voltage by using a high resistance layer in a predetermined region, and to obtain a large output device with a large current and a high withstand voltage.

4) Since the density of the gate region can be made high impurity density 1 and the shape of the gate can be made small, inter-electrode parasitics 7 (1
, i and gate resistance can be reduced, and together with the small single-row resistance, high frequency and high speed can be achieved.

5) SIT, in which the channel is almost completely depleted by the depletion layer extending from the gate, has an extremely wide gate voltage range, as well as a low current region where the current-voltage characteristics almost follow an exponential function. , due to the effects of the single-row resistor r8 and the drain resistor R, the characteristic shifts from an exponential function to a very linear characteristic over a very wide current range, including a large current range, in some cases more than 10 orders of magnitude, Keeping the amplification factor almost constant at 1, etc.
Ability to perform operations with extremely low distortion.

6) Since the amplification coefficient can be kept almost constant even when the current value is extremely small, extremely excellent switching operations can be performed in low current and low power consumption states.

7) Since the temperature characteristics in the large current state are negative, thermal runaway does not occur. Also, it is possible to design a structure that has almost no temperature characteristics.

8) Over a very wide operating temperature range, e.g.
The amplification factor can be kept constant over 0°C.

9) By narrowing the channel width and lowering the impurity density in the channel, almost no current flows when the gate voltage is zero, and current only flows when a forward voltage is applied to the gate. Ability to perform switch-notching operations in hancement mode.

In other words, SIT is superior in terms of high power, high withstand voltage, large current, low distortion, low noise, low power consumption, and high speed operation, etc., and its excellence as a thermal element and as an element for integrated circuits. It has been proven successfully and is opening up new fields of application in various fields.

Particularly when applied to integrated circuits, the high impedance of integrated circuits requires high drive currents.
And unsaturated type electric current 1! .

It has many advantages such as a large number of fan-outs due to its large conversion conductance.

An example of the current-voltage characteristics of a junction-type SIT is shown in Figure 1 (al, (
Shown in bi. At gate voltages higher than 1-2 V, which pinch off the channel as the gate voltage increases, the drain current I
d is the gate voltage Vg.

For any drain voltage Vd, in a low current state, it almost follows an exponential function I, but as the current increases and a negative feedback effect due to the series resistance begins to occur, it deviates from the exponential function. The reason why the region of large current is indicated by a dotted line in FIG. 1 tb+ is that it shows the result of pulse measurement to avoid a temperature increase of 1.

The basic structure of an insulated gate static induction transistor that operates in enhancement mode (E mode) or enhancement mode and depletion mode (D mode) is known from the rMO3, MIS electrostatic transistor filed by the inventor on January 11, 1978. This was fully clarified in ``Induced Field Effect Transistor''. Specifically, five types of structures are proposed as a means of creating a potential barrier near the source region by weakening the influence of the gate voltage, including the diffusion potential, near the source. In other words, (1) a structure in which the gate electrode (a metal such as An or a low-resistance semiconductor such as poly7 silicon) does not reach the source region; and (2) the thickness of the insulating layer near the source region is partially increased. (3) a structure in which the gate electrode metal near the source region is a different metal; (4) a structure in which a part of the insulating film under the gate electrode near the source region is made of a material with a low dielectric constant; and (5
) This is a structure in which the impurity density of the channel is partially increased near the source region. These structures may be incorporated as planar structures, or may be formed on the sides of a notch (V-shaped, U-shaped, etc.) provided on the semiconductor surface. In any case, in the main operating region, a potential barrier is generated in front of the source in the channel, resulting in majority carrier r-to-input 111 control operation, and unsaturated current-voltage characteristics are exhibited.

However, in these structures, the gate electrode extends almost from the source region to the drain region, and the conventional M
O3FET had a gate capacity (with gate)
The shortcomings such as slow operation speed due to the large capacitance 11t) between the λ plates and large gate-drain fit, or unsuitability for high-voltage operation due to the small gate-drain breakdown voltage, cannot be completely overcome. The previously overcome features of junction-type SITs, such as low power, high speed operation, or high voltage, high power input operation, were not necessarily fully utilized.

An object of the present invention is to overcome the drawbacks of the above-mentioned insulated gate (rG) SIT, have small gate capacitance and gate-drain capacitance, and high gate-drain breakdown voltage (low power, high speed operation). It is an object of the present invention to provide an insulated gate static induction transistor having a structure that enables the above-mentioned insulated gate static induction transistor, and at the same time to provide a semiconductor integrated circuit using such an insulated gate static induction transistor that operates at low power and at high speed.

The present invention will be described in detail below with reference to the drawings.

In order to reduce the gate capacitance in IGSIT,
Naturally, either the area of the gate electrode present in the channel 10 should be reduced, or the thickness of the insulating layer under the gate electrode should be increased. If the insulating film is made thicker, the voltage applied to the gate (threshold voltage) necessary to create an inversion layer and make the channel conductive becomes higher, which is not desirable in terms of operating characteristics. The only remaining method is to make the gate electrode smaller. A cross-sectional view of one example of a structure with a sufficiently small gate capacitance is shown in the second example of a Le channel type structure.
As shown in the figure.

In Figure 2, the n+ regions 51 and 54 are the source region and drain region, respectively, and the impurity density is +o17~1021α
, about -3. The r region 52 becomes a channel portion that controls the amount of electrons injected from the source to the train side, and its impurity ratio is 1 depending on the channel length.
The impurity density in this region is set to prevent punch-through between the source and drain in the main operating region, that is, the entire candy region is covered by a depletion layer extending from the drain. The length is selected to be from several 10 mm to several μm.P-
The region 53 is a low impurity density region, and the impurity density is set to a dimension d: such that the entire P- region becomes a depletion layer due to the diffusion potential with the drain region 54. For example, the impurity density is 10"-10"an-3 ('L degree), and the longer the distance from the channel to the drain region, the lower the impurity density must be.55 is 5i02s Si3
This is an insulating layer made of N4, Alz 03, etc., or a combination of a plurality of these. 51' and 54' are source and drain metal electrodes, respectively.

Reference numeral 56 denotes a gate electrode, which may be made of a metal such as AI or a low resistivity semiconductor such as poly-7 silicon. However, if the channel becomes very short and the gate electrode becomes thin, the time constant or operating speed limit determined by the resistance of the gate electrode and the gate capacitance will be lowered. It is desirable that the metal is thick, and that the eye resistance is small. The thickness of the insulating layer under the gate electrode varies depending on the channel length and operation mode (E mode or E/D mode).
Approximately 00 people. For the same channel length, the thickness of the insulating layer is slightly thicker when operating in E mode than when operating in E/D mode. When a positive voltage is applied to the drain electrode and a positive voltage is further applied to the gate electrode, which lowers the potential near the surface of the P region in contact with the insulating layer, the depletion layer is formed across this potential barrier. Electrons are injected into the P layer, which drifts due to the electric field and flows into the drain region. Therefore, in this structure, the flowing current is mostly determined by the amount of electrons injected to the drain side, so from the source to the potential barrier,
In the current region where the negative feedback effect due to the series resistor rs of the gate and the electric moon effect of the drain resistance from the potential barrier to the drain are not noticeable, the drain/current is reduced to the gate voltage Vg.
, the drain voltage IA flows almost exponentially with respect to any of the drain voltages Vd. The impurity density in the P region, which becomes a channel, is set near the surface and gradually decreases from the surface to the inside. becomes steep. In addition, the P region on the drain side is also the same (l), and the impurity density decreases from the surface to the inside, and the injected electrons spread out more and flow, reducing the drain resistance.Structure shown in Figure 2 Then, the gate capacitance Ju becomes sufficiently small, or another insulated gate (I
G) The source-to-substrate capacitance and the drain-to-substrate capacitance, which are major factors that reduce the operating speed of SIT, have hardly decreased. Of course, when using the source and the board at the same potential, the source/substrate question and answer ji' will not affect the operation, and if the train and the board are at the same potential, the capacitance between the 1/1 twin/board will not affect the operation. However, since at least one of the source and the train undergoes potential fluctuations, its capacity and operating speed are limited. Drain/board question and answer fj
FIG. 3 shows a structure for reducing . That is, the cleavage P region 62 which becomes a failure is formed only around the source region 61. The thickness is determined together with the impurity density so as to prevent unwanted leakage between the source and drain, as in FIG. 2. The thickness and impurity density of P region 62 are determined in relation to the impurity density and thickness of P- region 63. Thickness W2 of P◇r1 region 62, impurity density N
A2, thickness Wl of P-region 63, impurity degree N^1, typical voltage VD applied to the drain, diffusion potential Vb
Assuming that i, the condition that no punch-through occurs between the source and drain can be obtained as approximately tJ. T-' region 64 is the drain, 66
or gate electrode. The impurity density etc. of each region are the same as in the case of FIG. Drain region 64 is P- region 63
Since the depletion layer is in contact with the P- region 63, the depletion layer spreads sufficiently into the P- region 63, and the drain voltage (Itama valley IIF becomes small to 1i'). If it changes at high speed, it cannot follow the change in the width of the depletion layer in the P layer, which causes power consumption.
When performing high-speed operation, a P region 67 is provided roughly below the P- region as shown in Fig. 4, and the P region 67 is reached in most of the operation region, whether it is the drain region or the depletion layer. Just do what you do. The impurity density of the P region 67 is sufficiently higher than the impurity density of the P- region 63, and is 1015 to IQ20c.
Figure 5 shows an example of a structure in which the source region is extended to the drain side by ion implantation etc. The impurity density and operation are almost the same as in Figure 3. If the delay in the change in the width of the drain depletion layer limits the operating speed, as shown in the figure, a p-region 77 is provided as shown in Figure 6, and the drain is separated from the drain in most of the dynamic f'1 states. The depletion layer of P
It is only necessary to make sure that the area 77 is reached. In either structure, the impurity density and the =1 method are selected so that the P- region from the drain to the channel becomes a depletion layer as the diffusion potential increases. Of course, the structure that reduces the gate electrode area and reduces the capacitance is, of course, Ill! It's not something you can do.

It may be a P channel whose conductivity type is completely reversed, and the shapes of the source, drain, and channel are, of course, not limited to these, and there are various modifications.

An example of the cross-sectional structure of a vertical IG SIT in which the gate capacitance is sufficiently reduced by reducing the gate electrode area is shown in FIGS. 7 to 10, using an n-channel as an example.

84 are the source and drain, respectively, the P region 82 is a separate region that becomes a channel, the P-motion region 83 is a region that becomes a depletion layer due to the diffusion potential, 8
5 is an insulating layer, and 86 is a gate electrode. The impurity density etc. are the same as in the case of the planar type described above. When an inversion layer begins to form due to the gate tLt pole, the drain voltage At flows out. In Fig. 7, the capacitance between the gate and the source is increasing, and Fig. 8 shows an example of changing it.
Kate electrode becomes channel 7 le p I'ir! It is the same as Fig. 7 except that it is mostly limited to "area". 9th
The figure shows an example in which the source is configured on the board side.

n 10 head area 101.104 respectively sauce, toluin,
P area 102 or a separate area that becomes a channel, P- area 1
03 is a region which becomes a depletion layer as the diffusion potential increases, 105 is an insulating layer, and 106 is a gate electrode. V-shaped t1η in Figure 9
An example of a U-shaped structure is shown in FIG. In principle, except for the fact that the gate electrode 116 was separated into two parts, the ninth
It is the same as the figure. Of course, the two gate electrodes may be connected if the capacitance between the source and the gate is somewhat thick. Therefore, when the distance between the source and drain is shortened for the purpose of high-speed operation, the capacitance between the source and the train tends to increase, which becomes a factor that limits high-speed operation. To overcome this difficulty, either the source or the drain can be made smaller.

Examples are shown in FIGS. 11-13.

FIGS. 11 and 12 show cases in which the source regions are made smaller in the structures shown in FIGS. 7 and 8. In Fig. 11, rL+ regions 121.131 are sources, 124 are drains, P regions 122.132 are channel regions, P~
Region 123 is a region that becomes a depletion layer due to the diffusion potential, 125
is an insulating layer, 126, ]36 is a gate electrode, 121', 1
31' are a source and a metal electrode, respectively. FIG. 12 shows an example in which the V-shaped cut reaches up to n0 of the substrate, and the rest is the same as FIG. 11. FIG. 13 shows an example in which the drain shown in FIG. 9 is formed in a small region 164.

By configuring 11th to 13th sections 1, various capacities can be kept sufficiently small and IG SIT can operate at high speed.
can be made. Of course, the 41η structure shown in Figure 7 and Figure 13 is not limited to this, and the notches are also 7 characters, U
It is not limited to fonts. It goes without saying that a P channel with completely reversed conductivity type may be used, and it is also easy to use a multichannel type with a large number of channels. If high power operation is desired, the P'' region from the drain to the channel may be made long to ensure sufficient breakdown voltage. In addition, at this time, the drain voltage may be increased to a certain extent so that the entire P- region becomes a depletion layer, so the diffusion potential must be so long that the entire P- region does not become a depletion layer. It may be selected depending on the impurity density. In addition, in such a case, even if the gate electrode or the P-region 2 is filled, the P-region will eventually become a depletion layer in most operating conditions, so the capacitance will hardly increase. . Of course, for applications such as low-power, high-speed switching in integrated circuits, it is often more convenient to have a depletion layer in the entire region without applying a drain voltage, since current flows even with a small drain voltage. be. However,
In order to allow the desired current to flow by applying a certain amount of drain voltage, the P- region may be designed so that a portion of the region does not become a depletion layer due to the diffusion potential alone. If the channel length is short, the insulating layer under the gate electrode is thin, and the dielectric constant is set high, most of the voltage applied to the gate will be applied to the semiconductor region that will become the channel. The number of carrier stars that are injected into the I' lane side is quite similar to that of a bipolar transistor.

The IG of the present invention operates at such low power and high speed.
If BIT is used as a semiconductor memory device, its performance can be further improved. A specific example is shown below.

FIGS. 14 and 15 are examples of dynamic RAM memory cells using the IG SIT of the present invention.

Figure 14 uses IGSIT3o3, capacity C3
This is a memory cell that stores memory in 04.

301 is a write/read address line (column line), 30
2 is data cA (?te#A) for writing and reading. The write and read speeds can be approximately calculated as C70, y, and y, where cT is the conversion conductance of rGSIT. G of IGB'IT of the present invention? Since the bipolar transistor 1 is close to the current level, writing and reading can be performed at least one order of magnitude faster than the memory cell based on the MOS FET lc. FIG. 15 shows three S I'Ts of the present invention, 31
It is a memory cell using 5.316.317, and 311
．． 312 C write, read address line, 31
3.314 is a data read line and a write line. In this circuit, although the gate capacity of the SIT 316 is stored in memory, it is desirable that the gate capacity of these three gates be large, and since the 316 does not affect the operating speed much, a conventional IGSIT may be used. IGF
It may be ET.

FIG. 16 shows the IG SIT of the present invention in a static R
This is an example of application to an AM memory cell.

321 is an address line, 322 is a data read line, 32
3 is a data write line, 324 to 329 are I of the present invention.
GSIT. In particular, 324. determines the operating speed.
For SITs 325, 328, and 329, each capacitance such as the gate capacitance is preferably set to be small, and gm is also set to be large. 326.327 may be a conventional SIT or a conventional MOS FET. With the configuration shown in Figure 16, ff
The write and read speed is about one order of magnitude faster than the previous MO5FET configuration ('+ can be performed.RAM
Of course, the circuit configuration of Iζ is not limited to these. or,
Although the circuit was constructed mainly using an n-channel SIT, it goes without saying that a P-channel SIT may also be used. FIG. 17 shows an example of a static RAM memory cell in which the IG SET of the present invention is configured in a complementary manner. Compared to the one shown in FIG. 16, since it has a complementary configuration, the electric power consumption is extremely low, and has been reduced to about 1/10. 331
is an address line, 332 is a data read line, 333 is a data write line, and 334 to 339 are IGs of the present invention.
It is SIT.

The SIT of the present invention can be used not only for such RAM but also for RO
It can be applied to M (Read Only Memory), soft registers, and non-volatile memories equipped with 7$ play gates.

The IG SIT and the memory integrated circuit using the same described above can all be manufactured using conventional crystal assisted crystal technology, diffusion technology, ion implantation technology, and microfabrication technology.

In the IG SIT of the present invention, the gate electrode is formed with an insulating layer interposed between the narrow semiconductor region that is to become the channel near the source, and the region from the channel to the drain is a high resistivity region, which is essentially a depletion layer. The carrier drifts. By configuring like this,
The gate capacitance can be made sufficiently small, the drain-to-substrate capacitance can be made sufficiently small, and the conversion conductance can be made large (because it is possible to make it possible to operate at extremely low power and high speed. Its manufacturing is also a matter of course. Combined with this, when applied to storage devices, it brings extremely remarkable performance improvements, and its industrial value is extremely large.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are operating characteristic diagrams of an example of a structure of a static induction transistor, FIGS. 2 to 6 are sectional views of a planar structure of an IG SIT according to an embodiment of the present invention, respectively.
7 to 10 are cross-sectional views showing the structure of a notched gate type IGSIT according to an embodiment of the present invention, and FIGS. 11 to 13 are cross-sectional views showing the structure of a notched gate type IGSIT according to another embodiment of the present invention. Cross-sectional view showing the structure, Fig. 14, 1st
Figure 5 is a circuit diagram of an example of a dynamic RAM memory cell configured with IG SIT, Figure 16 is a circuit diagram of an example of a static RAM memory cell using IG SIT,
FIG. 17 is a circuit diagram of an example of a complementary IG SIT static RAM memory cell. ! Hall 4W! j Figure 6''' Figure 5 Figure 7, 5wJ Figure 9 *y'0WI iri 4'' Figure 1/Figure Al1g Figure 72 Figure 3

Claims (1)

[Claims] At least some of the intersection points of the matrix consisting of the required number of 7 trace column lines and the required number of write/read row lines are of high impurity density (conductivity of opposite conductivity type adjacent to the source region consisting of the jn region). Furthermore, one high resistivity region of the opposite conductivity type and the same conductivity type is interposed between the source region and the drain region consisting of a high impurity density region of the same conductivity type, and the surface of the portion near the source is A gate electrode is provided on the top via an insulating film, and in the main operating region, the high resistivity and opposite conductivity type region always becomes a depletion layer, and the impurity density and various rules are selected to exhibit unsaturated current-voltage characteristics. A memory cell including a small number (one at least) of static induction transistors is arranged, and at least one gate of the static induction transistor is connected to the row line or the column line directly or through another element. What is claimed is: 1. A semiconductor memory device characterized in that at least a portion of the semiconductor memory device includes