JPS60194561A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the cut-off frequency without the reduction in the amount of accumulated charges by a method wherein only the base thickness immediately under a detection transistor is reduced. CONSTITUTION:A P-layer 10 of a P-N-P-N cell constitutes the emitter of a load transistor Q5(Q6), and a P-layer 20 constitutes the bases of detection and holding transistors Q1(Q2) and Q3(Q4). Besides, the P-layer 10 connects with a terminal W on one side and diffuses to the neighborhood of a buried layer 40 on the other side. The P-layer 20 i.e. the bases of the detection and holding transistors diffuses to the neighborhood of the buried layer 40 as a whole. However, only the section 201 immediately under the emitter terminal S of the detection transistor Q1(Q2) is away from the buried layer 40 and is formed more thinly than the other base sections 202 and 203. As a result, the requirement for reduction in base thickness in order to increase the cut-off frequency and the requirement for increase in base thickness in order to improve the yield and to reduce the amount of accumulated charges can be satisfied at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device comprising a bipolar memory, particularly to the structure of an ECLRAM.

Prior Art and Problems Conventionally, in a semiconductor memory device such as a bipolar static RAM, the time tAA (addrs+ss
access time ) and the time tww (write pulse
In order to improve the characteristics of width), the base thickness of the entire transistor constituting the device has been made thinner.

This is because in order to increase the read/write operation speed of a semiconductor memory device, it is necessary to increase the blocking layer wave number f of the detection transistor constituting the sense circuit, and if the base thickness of the entire transistor is made thinner, fr generally increases. .

However, if the base layer is made too thin, even the slightest crystal defect in the emitter region, which is formed with extremely high concentration, will immediately cause a short circuit between the emitter and collector of the detection transistor, resulting in a decrease in yield. Therefore, in order to improve the yield of semiconductor memory devices, the base thickness should be increased to prevent the above-mentioned short circuit from occurring. However, if the base thickness is increased, as mentioned above, the interruption frequency fr will be lowered, and the read/write The problem is that the speed is slow.

Furthermore, in a RAM using a saturated cell, for example, a saturated PNPN cell, the collector region around the base is generally formed with a low concentration, and charges tend to accumulate in this low concentration region. Therefore, the thinner the base thickness of a RAM that has saturated cells with this tendency is made in an attempt to increase the cut-off wave number f7, the larger the volume of the collector region with low concentration will be, and the more it will be accumulated there. The amount of charge also increases. As the amount of accumulated charge increases, the amount of accumulated charge that must be removed when writing data also increases, and the write characteristics deteriorate. Therefore, writing characteristics are improved by increasing the base thickness and reducing the amount of accumulated charge that must be removed. However, there is a problem in that increasing the base thickness lowers the interruption frequency fr of the detection transistor and slows down the operating speed of the transistor.

OBJECTS OF THE INVENTION An object of the present invention is to meet the demand for thinning the base thickness in order to increase the wave number of the blocking layer, to improve the yield, and to reduce the amount of accumulated charge by thinning only the base thickness immediately below the detection transistor in a semiconductor memory device. The objective is to simultaneously satisfy the demand for increasing the base thickness in order to reduce the thickness of the base.

According to the present invention, in a semiconductor memory device in which the emitters of a detection transistor and a holding transistor are connected to a bit line and a hold line, respectively, a common base region of the detection transistor and the holding transistor is provided in a semiconductor layer on the surface of the substrate. A semiconductor memory device is provided, wherein an emitter region of both transistors is formed in the base region, and a base portion directly below the emitter of the detection transistor is formed thinner than other base portions. provided.

Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.

FIG. 1 is a sectional view of a first embodiment of a semiconductor memory device according to the present invention applied to a PNPN cell.

The device shown in FIG. 1 has an N-type epitaxial layer (
A semiconductor layer) 60 is formed, and terminals W, S, B, H, and C, which are electrodes, protrude from the upper surface of the semiconductor layer. These terminals are the terminals of a static cell having a flip-flop as shown in FIG. Specifically, as shown in the PNPN cell circuit of FIG. 4, it is composed of a load transistor QB, a detection transistor Qr -Qt composed of a number of Q multi-emitter transistors, and a holding transistor Q3 +Q.

Terminal W is connected to word line W, S is connected to left and right bit lines be and br.
, H is connected to the hold line, and B is connected to C, respectively.

On the other hand, inside the semiconductor memory device in FIG. 1, two layers 10, 20 and eight layers 3o are formed above the broken line, and a buried layer 40 is formed below the broken line. Also, in Figure 1,
Corresponding to Fig. 4, load PNP) transistor Qll
(Qa) NPN) transistor Q+ for detection and holding
(Qt) and Qs (Qa) and each terminal W, S, B
, H, and C are shown by dashed lines. As can be seen from this dashed line, the second layer 10 has a load transistor Q
The emitter of Il(Qa) is formed in two layers 20 by sensing and holding transistors Q+ (Q, ) and Q, (Q, ).
Each constitutes the base of

Then, P7iilO is connected to the terminal W on one side, and diffuses to the vicinity of the buried layer 4o on the other side.

Further, the base of the second layer 20, that is, the detection and holding transistor, is generally diffused to the vicinity of the buried layer 4o.

However, only the portion 201 directly below the emitter terminal S of the detection transistor Q, (Q,) is formed away from the buried layer 4o and thinner than the other base portions 202 and 203.

FIG. 2 is a sectional view showing a second embodiment of the semiconductor memory device according to the present invention.

The difference from the first embodiment shown in FIG. 1 is that the load transistor Q
The two layers 1° constituting the emitter of a (Qa ) and the detection and holding transistors Q+ (qt) and Qa (Qa
) is that only a portion 202 of the two layers 2o constituting the base is diffused to reach the buried layer 4o.

This is because the collector region of the load transistor Qa (Qa) has a particularly low concentration, for example, a lateral PNP.
) transistor is used, the volume of the low concentration collector region 30 (base region of the lateral transistor) is made as small as possible to reduce the amount of accumulated charge accumulated in the paste.

As described above, the embodiments shown in FIGS. 1 and 2 are based on the saturated type PN shown in FIG.
Although this is an example in which the present invention is applied to a PN cell, an example in which the present invention is applied to a diode load cell shown in FIG. 5 or an IIL cell shown in FIG. 6 as the same saturation type cell may also be considered.

In the case of FIG. 5 and FIG. 6, as in the case of FIG. The same effect can be achieved.

FIG. 7 is an example in which the semiconductor memory device according to the present invention is applied to an actual circuit.

In the circuit shown in Figure 4, the cell matrix is expressed in four digits, and one of the cells 6, 7, and 8.9 is selected by the horizontal word line W and the vertical bit line. be done. The horizontal word line W is selected by the X address decoder 1, and the vertical bit line is selected by the Y address decoder 2 through their respective driver circuits. 3 is a word line discharge circuit which has the function of rapidly lowering the word line; 5 is a write/read control circuit which flows current only to the bit line to be written or read;
Accordingly, the sense circuit 4 performs writing and reading.

Effects of the Invention As described above, according to the present invention, only the base thickness directly below the detection transistor can be made thinner, thereby meeting the demand for thinning the base thickness in order to increase the interruption frequency, improving yield, and accumulating charge. It is possible to simultaneously satisfy the demand for increasing the base thickness in order to reduce the volume.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of the fourth and second embodiments of the device of the present invention, respectively, FIG. 3 is a general circuit configuration diagram of the device of the present invention, and FIGS. 4 to 6 are A specific circuit configuration diagram of the device of the present invention applied to a PNPN cell, a diode load cell, and an IIL cell, respectively, and FIG. 7 is a circuit diagram showing an application example of the device of the present invention. l...Substrate, 10.20...P layer, 30...N layer, 40...buried layer, 201...thin part of second layer 20, 202.203...two layer 20 thick part of Patent applicant Fujitsu Co., Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi Figures 1-(Figure 3, Figure 4, Figure 5, Figure 6)

Claims (1)

[Claims] In a semiconductor memory device in which the emitters of a detection transistor and a holding transistor are connected to a bit line and a hold line, respectively, a base region shared by the detection transistor and the holding transistor is formed in a semiconductor layer on the surface of the substrate, and a base region is formed in the base region. A semiconductor memory device characterized in that emitter regions of both of the transistors are formed, and a base portion directly below the emitter of the detection transistor is formed thinner than other base portions.