JPS6127840B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a programmable read-only semiconductor memory device.

Programmable read-only semiconductor memory device
PROM (Programmable Read Only Memory)
There are fuse types and bond breaking types, and after mass production, information is written in according to the purpose of use.
It is used for reading only. The junction destruction type is
The PN junction is destroyed by a write current, and memory cells are usually formed in a matrix in an epitaxial layer on a semiconductor substrate, as well as transistors in peripheral circuits. Therefore, the base diffusion depth was the same for both peripheral circuit transistors and memory cells. The depth of this base diffusion is designed so that the base width is small with emphasis on the characteristics of the transistor in the peripheral circuit, so in memory cell transistors, the PN between the emitter and the base is Not only the junction but also the PN junction between the base and collector may be destroyed. In addition, in the configuration shown in FIG. 1, if the base-emitter PN junction of memory cells CL2 and CL4 among memory cells CL1 to CL6 has already been destroyed by writing, the memory cell CL
When selecting 1 and writing, the lines X1, Y1
Even if a write current is passed between them, memory cell CL5 may become conductive due to the thyristor action.
As a result, a current flows in the direction of the arrow, making it impossible to write to the selected memory cell CL1.

In this case, it is common practice to use the epitaxial layer as a common collector and row Y line, and to arrange a plurality of regions for configuring a plurality of memory cells and a plurality of emitter regions in the common collector.
As a result, a parasitic transistor effect occurs due to the base regions of adjacent cells and the common collector region between them.
For example, the PNP transistor Q2 shown in the thyristor equivalent circuit shown in FIG.
When the sum of the current gains of transistors Q1 and Q2 is equal to 1,
A switching action occurs as a PNPN four-layer diode, and this appears as the thyristor action described above. In this case, the conduction voltage due to the parasitic thyristor action becomes lower than the sum of the emitter-base reverse breakdown voltage (for example, about 7V) and the base-collector forward voltage (about 0.7V) required for writing to the memory cell. Almost all of the incoming current is bypassed.

Therefore, conventional PROMs have the disadvantage that desired information cannot be reliably written in some cases.

The present invention is a novel invention that improves the above-mentioned drawbacks, and its purpose is to suppress the thyristor action as described above without sacrificing the characteristics of the peripheral circuit transistors, thereby making it possible to reliably write to a semiconductor. The purpose is to provide a storage device.

In order to achieve this object, the semiconductor memory device of the present invention provides a junction structure in which a plurality of transistors constituting a memory cell and transistors of a peripheral circuit are formed in an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type. A destructive programmable read-only semiconductor memory device characterized in that the base depth of a transistor constituting a memory cell is formed deeper than the base depth of a transistor constituting a peripheral circuit. Examples are described below in detail.

FIG. 3 is an explanatory diagram of main parts of an embodiment of the present invention,
An N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and a transistor is formed in this epitaxial layer 2. 3 is a P-type diffusion region for element isolation, and C1, B1, and E1 are peripheral regions. Circuit transistor collector, base, emitter, C2, B
2, E2 is the collector of the transistor of the memory cell,
The base and emitter are shown, and the transistors in the peripheral circuit have a base-collector breakdown voltage and current amplification ratio.For example, the depth of the base B1 is 2 [μ], and the base depth of the memory cell transistor is For example, the depth is set to 3 [μ]. Although not shown, the memory cell transistor column is configured in an array with a plurality of bases and emitters arranged in the row line common collector region C2, which is exactly the same as in general conventional memory devices of this type.

With this configuration, the current amplification factor h _FE of the memory cell transistor can be lowered, so that the sum of the current gain of the parasitic PNP transistor and the memory cell transistor in the circuit shown in Figure 2 is less than 1. As a result, write current bypass due to thyristor conduction as explained with reference to FIG. 1 does not occur, and therefore reliable writing is possible even in a state where adjacent memory cells have already been written. Furthermore, even if the junction between emitter E2 and base B2 is destroyed by a write current, the base B2/collector C2 junction is less affected by the heat generated at the time of destruction and is less likely to be destroyed, which improves the reliability of the read-only semiconductor memory device. can be improved.

Figure 4 shows the current amplification factor h _FE on the vertical axis, and shows the distribution of those that passed the writing test and those that did not, and a1 and a2 represent the base depth of the conventional example. The pass and fail distributions are shown when the value is about 1.8 [μ], and the writing yield was about 57 [%] due to the influence of the parasitic transistor due to the high _hFE . Also, b1 and b2 are according to the embodiment of the present invention, and show the distribution of pass and fail when the base depth _is 2.4 [μ]. was approximately 89%.
That is, as in the present invention, by making the base of the transistor in the memory cell deeper than the base of the transistor in the peripheral circuit, h _FE is lowered, thereby ensuring that writing is performed.

As mentioned above, in order to suppress the current leakage due to the parasitic thyristor action, it is sufficient to make the total current gain of the NPN transistor for the storage cell and the parasitic PNP transistor pairs between the bases of the adjacent storage cells smaller than 1, and this purpose can be achieved. If that's all you need, there are various measures you can take. This means that the h _FE of the parasitic PNP transistor can be lowered. In order to lower h _FE , it is necessary not only to increase the base depth as in the above embodiment, but also to decrease the emitter depth and adjust the relationship between the emitter, base, and collector impurity concentrations.
Various measures are possible, such as changing the facing area of the emitter and collector. However, none of these measures is practical at all compared to the measure of making the base of the memory cell transistor deeper than the base of the peripheral circuit transistor as in the above embodiment. That is,
First, the strategy of adjusting the relationship between impurity concentrations is as follows:
It has a large effect on other characteristics of the transistor, such as the breakdown voltage of the junction, and the range in which it can be changed is narrow, so it is not very effective. Shallowing the emitter of a memory cell/transistor will lead to failure of the emitter-base junction due to alloying of the electrode metal into the emitter region even during normal operation other than during write operations. It is impossible to make the emitter shallower, which has already been shallowed to near the limit for operation, because this emitter-base junction breakdown will occur frequently. Changing the emitter-collector opposing area of a memory cell transistor or a parasitic PNP transistor is effective in improving memory cell transistors, which have a close-packed pattern for higher integration density.
This leads to changes in the shape or arrangement pattern of transistors, which inevitably leads to a reduction in integration density. Increasing the base width of the parasitic PNP transistor is also effective in reducing _hFE , but this means increasing the storage cell-to-transistor spacing, which has a very large negative effect on lowering the integration density.

In this way, in addition to the method of making the base of the memory cell transistor deeper than the peripheral circuit transistor as in the present invention, there are various methods for suppressing the adverse effects caused by the parasitic thyristor action, but none of them compare with the present invention. It lacks practicality. Furthermore, according to the present invention, it is possible to prevent malfunctions in which even the base-collector junction is destroyed during writing. The reason why the base depth of the memory cell transistor is determined in comparison with the peripheral circuit transistor in the present invention is that in practice, in PROM, both transistors are built in the same epitaxial layer, and after writing This is because, compared to a memory cell array that functions simply as a diode array, peripheral circuit transistors cannot be placed very close to the bottom of the collector because the characteristics near the base-collector junction affect the transistor characteristics. Furthermore, it is also necessary to make the base of peripheral circuit transistors as shallow as possible in order to improve operating speed. Conversely, even if the base of the memory cell/transistor is as deep as or shallower than the base of the peripheral circuit transistor, write failures due to parasitic thyristor action can be suppressed by sufficiently widening the spacing between adjacent cells, but this As mentioned above, this is unrealistic since the density becomes extremely low. In other words, the reason why the base depths of both transistors are defined as in the present invention is not only to prevent writing failures, but also to prevent base-collector junction breakdown during writing, emitter-base junction breakdown during normal operation, and peripheral circuits. This is because the most excellent effect can be obtained in achieving various objectives such as improving the operating speed of the transistor, securing the collector breakdown voltage, and increasing the integration density.

As explained above, the present invention improves integration density and operation by making the bases of transistors constituting memory cells deeper than the bases of transistors constituting peripheral circuits in a junction-destructive programmable semiconductor memory device. This has the advantage of lowering the h _FE of the transistors constituting the memory cell while minimizing the adverse effect on speed, thereby preventing the write current from flowing around due to the thyristor action, thereby ensuring reliable writing. Further, as described above, since the base-collector junction of the transistor constituting the memory cell is prevented from being destroyed, there is an advantage that reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the bypass current due to thyristor action during writing, FIG. 2 is an equivalent circuit including a parasitic transistor of a memory cell, FIG. 3 is an explanatory diagram of the main part of an embodiment of the present invention, and FIG. FIG. 6 is an explanatory diagram of the distribution of write passes and fails by h _FE in the conventional example and the embodiment of the present invention.

Claims (1)

[Claims] 1. In a junction-destructive programmable read-only semiconductor memory device in which a plurality of transistors constituting a memory cell and peripheral circuit transistors are formed in an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type. A semiconductor memory device characterized in that the base depth of a transistor constituting a memory cell is deeper than the base depth of a transistor in a peripheral circuit.