JPH0685199A - Memory cell - Google Patents

Abstract

PURPOSE: To shorten a memory cell in write time, by a method wherein the control region of a first transistor connected to the conductor region of a second transistor and the control region of the second transistor region connected to the conduction region of the first transistor are connected together with a third transistor. CONSTITUTION: A PNML or a PNMR is possessed of a common control region or a base in common with a corresponding SCR intrinsic PNP transistor. The base held in common is made to serve as the collector of the intrinsic NPN transistor. The emitter region of the PNM transistor serves as the collector of the PNP transistor. The common region is made to serve as the base of the NPN transistor. The base of the PNM transistor is connected to its collector. By this setup, this CTS cell is much smaller in size than a conventional SBD clamp-type CTS cell and much lessened in write time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell, and particularly to a semiconductor memory array, which is suitable for application to a complementary bipolar transistor memory cell array.

[0002]

The complementary transistor switch (CTS) cell of US Pat. No. 3,863,229 is a conventional high performance transistor memory cell. Basically, this CTS cell is shown in FIG.
, A pair of cross-coupled PNPN (silicon controlled rectifying element or SCR) switching elements. When the SCR turns on and saturates, it can only be turned off by reducing its control gate junction voltage to turn off the intrinsic transistor of the SCR. However, the CTS cell of FIG. 4 is written through the Schottky barrier diodes (SBD) SL and SR. Since this CTS cell is written via the SBD, pulling BL or BR low will not affect the cell. Instead, either BL or BR is pulled high enough to supply a sufficient base (control gate) voltage to turn on the "off" NPN transistor and to increase the base (control gate) voltage of the "on" PNP transistor. Lower this "on" PN
By turning off the P-transistor, the cell state switches. Turning on the "off" NPN transistor and turning off the "on" PNP transistor results in the "on" SCR turning off and "off".
The SCR turns on. The time required to switch the steady state of the SCR depends on the time required to discharge the charged and saturated capacitor. Therefore,
Writing a cross-coupled SCR cell is difficult and the write time is relatively long.

In order to reduce the write time, the SCR of each CTS cell has an SBD, which is across the second PN junction, ie between the control gates of the SCR (the bases of the two intrinsic complementary transistors). Since the base of the intrinsic PNP transistor is one of the current conducting terminals (its collector) of the intrinsic NPN transistor, and conversely the current conducting terminal of the intrinsic PNP transistor is the base of the intrinsic NPN transistor, the SBD completely turns on the SCR. To prevent this from happening, which results in an "on" SCR true NPN
Prevents saturation of transistors and intrinsic PNP transistors. We refer to these SBDs as "clamping" SBDs because they prevent saturation of the SCR by clamping the on voltage of the collector in each intrinsic transistor to its base voltage.

While the clamping SBD prevents saturation and correspondingly prevents the SCR turn-off time from increasing, the clamping SBD occupies a significant portion of the CTS cell area. Since a larger number of memory cells can be arranged in the same chip area, a smaller RAM cell is more suitable. Minimizing both write time and cell size is a major goal in RAM chip design.

FIG. 5 is a conventional clamp type CTS shown in FIG.
A physical property cross section of a cell, showing a spatial relationship in one half of a general cell, for example, PL, NL, SBCL
And SL are shown. Each PNPN switching element (SC
R) indicates area 100, area 102, and area 10 in this order.
4 and a region 106. The intrinsic PNP transistor is an emitter 100, a base 102 and a collector 10.
It consists of 4. The intrinsic NPN transistor is the collector 102,
It is composed of the base 104 and the emitter 106. The clamping SBD is formed by the metal portion 108 being in direct contact with the n region 102. The P region 104 provides a guard ring surrounding the clamping SBD to isolate the Schottky junction and prevent unwanted parasitic effects.
Finally, the transfer SBD is the collector reach through area 110.
Is partially isolated from the cell, and its junction is formed by direct contact of the metal part BL to the diffusion region 112. All cell areas under the metal part 108 forming the clamping SBD were needed for the SBD.

US Pat. No. 4,635,228 states that the clamping SBD can be eliminated to produce a much smaller CTS cell. In US Pat. No. 4,635,228, instead of using a clamping SBD in the cell as schematically shown in FIG. 6, a cross-coupled SCR of cells is used.
It teaches clamping the cell supply voltage to a level approximately equal to the turn-on voltage of the SCR with a diode across it. However, this cell, called an unclamped cell, requires a much longer write time (as expected).

In an unclamped CTS cell, the cell's SCR can saturate, which puts each intrinsic transistor of the "on" SCR into deep saturation, resulting in longer write times than the clamped cell. As a result, the junction capacitance of the "on" SCR is high compared to the "on" SCR in the clamped CTS cell. Since the junction capacitance is high, the electric charge stored in each junction capacitor is large. Switching a unclamped cell requires first discharging the junction capacitor and turning off the "on" SCR. As a result, for the same write current, switching the clamped cell requires more time than switching the unclamped cell.

Soft error susceptibility results firstly from a reduction in the supply voltage of the unclamped cell and secondly by modifying the transistor characteristics to improve the write time of the unclamped cell. Therefore, even if the unclamped cell does not saturate, if the voltage across the SCR is sufficiently close to the turn-on voltage of the SCR, the unclamped cell supply voltage will be maintained near the turn-on voltage of the SCR. However, if the unclamped cell supply voltage is close to the turn-on voltage of the SCR, even lower levels of noise will confuse the cell.

Another approach used to reduce unclamped write time has been to weaken the current gain of the intrinsic transistor of each SCR. Lowering the current gain of the intrinsic transistor makes writing unclamped cells much easier because less write current is needed to overcome the "on" SCR. Thus, more current is supplied to damp the charge stored in the junction capacitor. However, further easing the writing of unclamped cells has an undesirable effect. That is, the cells are more easily disturbed and confused, so that the stability is lowered and the influence of the soft error is further increased. The soft error is generation of erroneous data in the memory cell, which is not caused by a physical defect in the cell, and does not occur normally. Soft errors are caused, for example, by alpha particles that penetrate the charged PN junction and discharge it.

Thus, RAM designers sacrifice performance at the expense of density and either use conventional unclamped CTS cells with smaller cell sizes and slower operating speeds, or sacrifice performance at the expense of density. Conventional clamp type CT with large cell size and faster operation speed
You are forced to use S cells.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the write time for high density, high performance memory cells.

Another object of the present invention is to improve the stability of high density memory cells without compromising write performance.

Yet another object of the present invention is to improve noise immunity of high density, high performance memory cells.

Yet another object of the present invention is to improve the soft error rate in high density, high performance memory cells.

Still another object of the present invention is to shorten the write time of a high-density and high-performance memory cell, improve the stability of the cell, improve the noise margin of the cell, and improve the soft error rate. is there.

[0016]

In order to solve such a problem, the present invention provides a random access memory (RA).
M) A memory cell in the array is provided with a pair of cross-coupled switching elements and a data transfer means for coupling the pair of cross-coupled switching elements to a pair of complementary bit lines, each switching element being of the first type. First transistor, a second transistor of the second type, a control region of the first transistor coupled to the first conduction region of the second transistor, and a first conduction region of the first transistor. A control region of the second transistor coupled to the region, and a third region connected between the control region of the first transistor and the control region of the second transistor.
And a third transistor of the form

Further, in the present invention, a pair of cross-coupled silicon controlled rectifiers (SCRs), a PN-metal (PNM) transistor coupled across the PN junction in each SCR, and the first SCR as a complementary bit line. A Schottky barrier diode (SBD) coupled to
And a Schottky barrier diode (SBD) for coupling the SCR of the above to the complementary bit line.

[0018]

To achieve the various objects described above, the present invention provides a clamped complementary transistor switch (CTS) memory cell which uses a PN-metal (PNM) transistor to clamp saturation. A pair of PNPN switching elements (silicon controlled rectifying element or SC
R) is cross-coupled to store the data. The second PN junction of each SCR is clamped by the PNM transistor. The base of each PNM transistor is connected to its collector.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

The preferred embodiment of the present invention is a CTS cell clamped by a pair of lateral PNM (Shockkey) transistors as shown in FIG. Each PNM transistor, PNML or PNMR (PNM on the left side of the figure is PNML, PNM on the right side is P
NMR) shares a common control region or base with the corresponding intrinsic PNP transistor of the SCR. This shared base is also the collector of the intrinsic NPN transistor. The emitter region of each PNM transistor is the collector of the PNP transistor. This shared area is the base of the NPN transistor. Each PNM
The base of the transistor is connected to its collector.

FIG. 2 shows the PNM-clamp type CTS of the present invention.
It is a physical expression or layout of the cell. FIG. 3 is a physical representation of a section taken along the line AA of the cell of FIG. The trench 120 isolates the left half 122 of the cell from the right half 124 of the cell and also from adjacent cells (not shown). Since the left half 122 and the right half 124 of the cell are identical, the physical properties of one half of this cell apply to the other half of the cell as well. Each SCR is an emitter region 126 of a PNP transistor, a PNP base and NPN.
It is characterized by a collector region 128, a PNP collector and NPN base region 130 and an NPN emitter region 132. Bit line SBD indicated by symbols SL and SR
Is formed by the metal contact portion 134 directly contacting the N-epi region 136. N-epi region 136 is isolated from the SCR by N + subcollector reach-through region 138. Furthermore, the bit lines SBD 140 are isolated by a p + guard ring 142 surrounding each bit line SBD 140.

The clamp type PNM transistor of each half of the cell is a lateral transistor, and its emitter is P.
It is formed by the NP collector / NPN base region 130, and its base is the PNP base / NPN collector region 1.
28, the collector 144 of which is formed by the metal contact portion 146 making direct contact with the PNP base / NPN collector region 128.
This same metal contact 146, which forms the collector 144 of the PNM transistor, contacts the N + subcollector reachthrough region 138 and connects the transistor base 128 of the PNM to its collector 144.

A metal line (not shown) connecting between PNM collector metal stud 146 and stud 148 to p-type polysilicon (poly) layer 150 in one half of the cell.
Thus, the left and right halves 122 and 124 of the cell are wired together, ie cross-coupled. Poly 150 is the PNP collector and NPN base region 1 of the other half of the cell.
I am in contact with 30. A metal line (not shown) connects the data line DL to the two NPN emitters 15
Connect to 2. Another metal line (not shown) connects the word line WL to the stud 156 which is connected to the PNP emitter via the p-type poly 154.

The memory cells of the present invention can be used in bipolar or BiCMOS SRAMs suitable for clamped CTS cells or unclamped CTS cells. In particular,
A PNM-clamp type CTS cell is described in US Pat. No. 4,598,3.
The memory cells disclosed in No. 90, "Random Access Memory Using Complementary Transistor Switch (CTS) Memory Cells" can be substituted.

Although the present invention has been shown and described based on the preferred embodiments thereof as described above, various changes may be made in the detailed structure without departing from the spirit and scope of the present invention.

[0026]

Since the CTS cell of the present invention uses the PNM transistor for clamping, the cell size is much smaller than that of the conventional SBD clamp type CTS cell which has comparable write performance. In addition, the clamping current means that the cross-coupled SCR is clamped and out of saturation further resulting in a reduction in junction capacitance. Due to the reduced junction capacitance compared to unclamped cells, unclamped C according to the prior art
The write time for PNM-clamp CTS cells is further improved over the write time for TS cells.

Furthermore, the PNM-clamp CTS cell has a soft error rate and noise immunity equal to or better than the conventional clamp CTS cell. Thus, PNM-clamped CTS cells can achieve both high performance and stability, are slightly larger in size than unclamped cells, and are significantly larger in size than conventional clamped CTS cells. Get smaller.

[Brief description of drawings]

FIG. 1 is a schematic connection diagram of a PNM-clamp type cell according to a preferred embodiment of the present invention.

FIG. 2 is a top view showing the physical properties of the PNM-clamp type cell of FIG.

FIG. 3 is a sectional view showing the physical properties of the cell in the preferred embodiment of FIG.

FIG. 4 is a connection diagram schematically showing a conventional clamp type CTS cell.

5 is a cross-sectional view showing the physical properties of the conventional clamp type CTS cell of FIG.

FIG. 6 is a connection diagram schematically showing a conventional unclamped CTS cell.

[Explanation of symbols]

120 ... trench, 122 ... left half of cell, 124
... right half of cell, 126 ... emitter region of PNP transistor, 128 ... base region of PNP and collector region of NPN, 130 ... collector region of PNP and NP
N base area, 132 ... NPN emitter area, 1
34, 146 ... Metal contact part, 136 ... N-epi region, 138 ... N + subcollector reach-through region, 140 ... Bitline SBD, 142 ... P + protection ring, 144 ... PNM transistor collector,
148, 156 ... stud, 150, 154 ... p-type polysilicon layer, 152 ... NPN emitter stud.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Frank Day Jeans 17 Kings Drive, Wallkill, 12589, New York, United States 12589 (72) Inventor Glen A Ritter New York, USA 12533, Hopewell Jianxyon , Art Dee 3, 15 Hootx Run (72) Inventor William F. Steinson, New York, USA 12540, Lagrangville, 18 Shearrott Drive

Claims (9)

[Claims] 1. A memory cell in a random access memory (RAM) array comprising a pair of cross-coupled switching elements and a data transfer means for coupling the pair of cross-coupled switching elements to a pair of complementary bit lines. Each of the switching elements comprises a first transistor of a first type, a second transistor of a second type, and a first transistor of the first transistor coupled to a first conduction region of the second transistor. A control region, a control region of the second transistor coupled to the first conduction region of the first transistor, and a control region of the first transistor and a control region of the second transistor. And a third transistor of a third type. 2. The third transistor is PN-metal (P
The memory cell according to claim 1, wherein the memory cell is an NM) transistor. 3. The memory cell of claim 2, wherein the control region of the PN-metal (PNM) transistor is coupled to the first conductive region of the first transistor. 4. The memory cell according to claim 3, wherein the first transistor is an NPN transistor and the second transistor is a PNP transistor. 5. The data transfer means comprises a cross-coupled switching element and a pair of Schottky barrier diodes (SBD) connected between the pair of complementary bit lines. 4. The memory cell according to item 4. 6. The first conductive region of the PNP transistor is a conductive region of the PN-metal (PNM) transistor, and the control region of the PN-metal (PNM) transistor is a control region of the PNP transistor. The memory cell according to claim 4, wherein: 7. The base of the PNP transistor is the N.
5. The memory cell according to claim 4, wherein the memory cell is a collector of a PN transistor, and the base of the NPN transistor is a collector of the PNP transistor. 8. A pair of cross-coupled silicon controlled rectifiers (SCRs) and a PN connected across the PN junction in each SCR.
A metal (PNM) transistor, a first Schottky barrier diode (SBD) for coupling the SCR to the complementary bit line, and a second Schottky barrier diode (SBD) for coupling the SCR to the complementary bit line. A memory cell comprising: 9. The memory cell of claim 8, wherein the base of each PNM transistor is connected to its collector.