JP2755979B2 - High-speed bipolar memory cell - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates generally to bipolar memory cells,
Specifically, the present invention relates to a bipolar memory cell for switching a load to improve a writing speed characteristic.

[Background of the Invention]

A bipolar memory cell is a circuit that can store information in a low current standby mode and write or read information from the cell in a larger current mode.

Many current bipolar memory cells consist of a pair of cross-coupled multi-emitter transistors that operate as latches, such as transistors 2 and 4 shown in FIG. The bases 6, 8 of these transistors are cross-coupled to their respective collectors 10, 12. The first emitters 14, 16 of each transistor are standby current drain lines
Connected to 17. The second emitter 18 of one transistor is connected to the first bit line 20, and the second emitter 22 of the second transistor 4 is connected to the second bit line 24. The collectors of both transistors are also connected to row select line 26 through load PNP transistors 28 and 30.

This load provides the non-linear resistance needed to maintain a reasonable cell differential voltage in both the low current standby mode and the high current read / write mode. IEDM
86, pp. 468-471, Ogiue, Odaka, Iwabuchi and Uchida, "Technical Improvement for High-Speed ECL RAM"
In the prior art load arrangement described in US Pat. The emitters 3 of the first and second PNP transistors 28, 30 used in this arrangement, also shown in FIG.
2, 34 are connected to the selection line 26. The collector 36 of the first PNP transistor is the base 6 of the first multi-emitter transistor 2 and the base 3 of the second PNP transistor 30
8 and the collector 10 of the second multi-emitter transistor 4. The second PNP transistor 30 is similarly connected. In this arrangement, either half of the cells operates as an SCR latch, a latch commonly referred to as a thyristor latch. This is PNP
Also, when the collector / base region of the NPN transistor is saturated, a large amount of charge is accumulated in the form of a diffusion capacitor in the PNP transistor. This cell device, like the other prior art devices described below,
It is characterized by the basic charge accumulation problem in the base region of P and the collector region of a multi-emitter NPN transistor. The stored charge occurs in the epitaxial (epi) region of the cell. Due to this charge accumulation, the write pulse width becomes longer, and the write recovery time of the cell becomes longer. To write the opposite data into the cell, the holes injected into the epi or collector region of the multi-emitter transistor are removed from the blocking side of the cell and the cell is conducting or writing. It must be supplied to the seldom side.

Another method for eliminating the charge accumulation shown in FIG.
The load is provided by Schottky diodes 40,42. Each Schottky diode has a resistance of 300-500 ohms 4
They are connected in series with 4, 46 in parallel with resistors 48, 50 of 20K-100K ohms each. Cell 10 in standby mode
Use a 0K ohm resistor to hold the latch and read 30
Done through a 0 ohm resistor. When reading a half cell, the 100K ohm resistor is transparent. This cell provides fast write times, but is sensitive to alpha particles.

Immunity to alpha particles is an absolute requirement in high-speed RAM. Alpha particles come from almost any material used to make high-speed RAM. Temporary alpha particles were thought to come from the ceramic used to install high-speed RAM. Therefore, as a solution, it has been attempted to coat the die with polyimide thickly. It was later demonstrated that alpha particles could be generated in aluminum or other materials used to make RAM. The solution must be sought in the design of the part itself, since alpha particles are generated in the material from which the product is made. Historically, parts designed to be insensitive to alpha particles also make writing relatively difficult. You need to overcome this flaw to get the best RAM speed. An effort to resolve this alpha particle problem is shown in FIG. This is taken from the Ogiue article mentioned above. In this design, large tantalum oxide Ta ₂ O ₅ capacitors 52, 54 are placed in parallel with each Schottky diode. However, this design has drawbacks that require very high standby current and integration of capacitors 52,54.

A more recent effort to overcome this deficiency is disclosed in U.S. Pat. No. 4,580,244, shown in FIG. In this design, the collector-base junctions of the PNP load transistors 28, 30 are NPN transistors 5 operating in reverse mode.
Clamped by 6,58. That is, the base of each transistor 56, 58 is connected to the collector and acts as a diode. The NPN transistors 56,58 function to steal current from the combined lateral PNP transistors 28,30, effectively stealing base current and reducing β of this transistor. Therefore, according to this design, the accumulated charge is reduced, and writing is facilitated. In other words, the circuit of FIG. 4 has a substantially β lowering function, and basically lowers the emission efficiency of the PNP emitter. However, the charge accumulation problem remains because the SCR must continue to latch the cells to operate.

As described above, in the standby mode, a trickle current is injected to withstand alpha particles, and a memory cell that can be distinguished so as to facilitate writing during reading using a larger reading current is required.

[Summary of the Invention]

Accordingly, it is an object of the present invention to provide an improved ECL memory cell.

Another object is to provide a memory cell with a reduced write pulse width.

Yet another purpose is that the multi-emitter transistor is loaded by the PNP when the cell is in standby and is insensitive to alpha particles, and functions effectively in a different form when the cell is sliding so that the cell is The object is to provide a cell that is easy to write when being read.

In particular, it is an object of the present invention to combine both properties of a PNP load cell and a diode load cell to achieve both fast write times and immunity to alpha particles.

In summary, a first latch is shown in FIG. 5 where the base is cross-coupled to the other collector to form a typical latch.
And a switched load diode cell comprising a second multi-emitter NPN transistor. The anode of the PN diode is coupled to the select line through a load resistor, and the cathode is coupled to the collector of each associated multi-emitter transistor. The emitter of the parasitic lateral PNP transistor associated with the PN diode is coupled to the select line through the same load resistor, and the collector is connected to the base of the associated multi-emitter transistor. A relatively low resistive load of about 500Ω is connected between the common node of the emitter of the parasitic lateral PNP transistor and the anode of the PN diode and the select line.
This completes the switched load diode cell. According to the present invention, in part, the parasitic PNP β greatly attenuates with the current, and if the PNP β (β _PNP ) is very small, almost zero when the collector current does not flow, the parasitic PNP transistor is a PN diode. It is based on nothing different.

(Here, β means the current amplification factor of the transistor.) The design goal is to reduce β _PNP extremely small at a large current (read current) so that the β product (β _PNP × β _NPN ) is greater than 1. It is to make it smaller. In the standby mode, only the standby current flows through the standby emitter of any one of the multi-emitter transistors, and β _PNP × β _{NPN STBY} is much larger than 1. Thus, for small standby currents, the cell behaves exactly like a PNP load cell. However, when the cell is being read, the cell is effectively a resistor using a diode load cell.

The above design goals are realized based on the knowledge that β of PNP greatly decreases with current. In addition, when the cell is in standby, a current, preferably between about 1 and 10 μA, flows through the standby emitter. If a read mode is desired, a read current, preferably between 0.5 and 1 mA, is passed through the other emitter. A multi-emitter transistor that can have different β due to different functions of the emitter is used. To obtain these βs, either increase the base width and / or increase the doping for low β read emitters, and increase the base for high β standby emitters. Either the width is reduced and / or the doping is reduced. This change can be achieved by local injection into the outer region, i.e. in the region defining the base for the read emitter. By using this high-low β method,
The requirements for the β product are very easily fulfilled.

The advantage of this design is that it is alpha-resistant during sleep (data retention) of the cell where trickle currents flow through the cell, and efficiently differentiates cells during read-out of the cell to facilitate writing. Is to give. According to this design,
The NPN and PNP being read are not effectively saturated. In other words, PNP and NPN collector
The epi region of the base junction does not store charge and does not saturate. This function is due to the fact that the β of PNP is greatly reduced at large currents and that two NPs with essentially different β
It is the result of working effectively with N-transistors.
If enough current is applied to the bit line, β becomes two β
The product (β _PNP × β _NPN ) drops below 1, the PNP and NPN transistors do not saturate, no charge is stored, and writing is easily performed. Unsaturated PNP
By providing a 500 ohm resistor in series with the transistor, the cell appears to be PN for read and write purposes.
Provides a view of a diode load cell.

The reduction of β, which is essential for efficient write operation in combination with a PNP transistor, is achieved by providing a bit line emitter with a wider base width and / or higher doping than the standby emitter base. Note that Far larger reading /
As a result of providing a low β bit line emitter to which the write current is supplied, the product of β of PNP and β of NPN during read / write is less than one.

The objects, features and advantages of the present invention will become apparent from the following description based on the accompanying drawings.

〔Example〕

The memory cell according to the invention shown in FIG. 5 is suitable for being manufactured as a monolithic integrated circuit. Vertical NP
The emitter 70 of the N transistor 72 is connected to the standby current drain line 74. A current source 76 is connected to the standby current drain line 74 in a known manner. The read emitter 78 of the multi-emitter transistor 72 is connected to the bit line 80. The other multi-emitter transistor 82 of the cell also includes first and second emitters 84,86. The standby emitter 84 is also connected to the standby current drain line 74 and the read emitter 86 is connected to another bit line 88. PN diode 20
The cathode of 0 is connected to the collector of NPN transistor 82. The anode of the PN diode 200 is connected to a row select line 102 through a resistor 100 (preferably about 500 ohms). The base 90 of the NPN transistor 82 is connected to the collector 92 of the PNP parasitic transistor 94. Multi-emitter NP
The collector 96 of the N transistor 82 is a PNP parasitic transistor 94
The emitter 99 of the PNP parasitic transistor 94 is connected to the anode of the PN diode 200. The base 90 of the multi-emitter NPN transistor 82 is a parasitic PNP
In addition to the collector 92 of transistor 94, a cross-coupled multi-emitter NPN transistor 7 is known in the art.
The second collector 104 is also connected. This collector 104
Is the base 106 of the parasitic lateral PNP transistor 108 and PN
It is also connected to the cathode of the diode 210. The base of the multi-emitter vertical NPN transistor 72 is a parasitic PNP
Connected to the collector 112 of the transistor 108, the emitter 114 of the parasitic PNP transistor 108 is connected to the anode of the PN diode 210, and the load resistance 116 (the value of which is preferably 500
Ω) to the selection line 102.

As is well known in the art, when a logic low signal appears on the bit line 88 and a logic high signal appears on the bit line 80, the multi-emitter NPN transistor 82 is turned on due to the voltage applied to the base, and other cells are turned on. Is turned off. NP is on when the low and high signals on bit lines 88 and 80 are removed.
Current source 7 through standby emitter 84 of N transistor 82
The small current from 6 keeps the latched state. When the signals on bit lines 88 and 80 are inverted, ie, bit line 88 goes high and bit line 80 goes low, transistor 82 turns off and transistor 72 turns on. When these high and low signals are removed, the latched state is maintained by a small current from current source 76 through emitter 70 of transistor 72 which is on.

The advantages of the present invention will become more apparent from FIGS. 6A and 6B. These drawings show the vertical NPN transistor 72, P
N diode 210 and its parasitic lateral PNP transistor 10
8 and how the half-cell, including resistor 116, is monolithically integrated into the novel structure to accommodate the fast write pulse width. As shown in Figure 6A, the integrated structure is P ^-
Start manufacturing from silicon substrate 120. An N ⁺ buried layer 122 that functions as a buried collector for the vertical device is formed in the substrate 120, and an N ^- epitaxial layer 124 is grown on the N ⁺ buried layer 122. The resistor 116, the lateral PNP transistor 108 and the vertical NPN transistor 72 are arranged adjacent to each other as shown. This portion of the monolithic integrated circuit is electrically isolated from the rest of the chip by oxides or grooves 128,130. Figures 6A and 6B
From the figures, those skilled in the art will appreciate that various diffusions and implantations may be used to form these devices. For details of this process, see L. Volak and G. Brown's application entitled "High-Performance Bipolar Structure" filed and filed concurrently with the United States on April 11, 1988, US Serial Number
180,626).

Specifically, the resistor 116 is limited by omitting a portion of the silicide layers 132, 134 in the region 116. This resistor 116 is connected to a PN diode 210 through a conductive silicide layer 134.
Anode and emitter 11 of parasitic lateral PNP transistor 108
4 and connected to. The P region 136 defining the parasitic anode and the emitter is formed outside the P poly layer 138 by boron diffusion. The base region 106 of the parasitic lateral transistor 108 exists adjacent to the emitter region 136. N regions 140, 240 and 250 that provide the base contact for the PNP transistor are N poly regions 1
Arsenic diffusion is formed outside of 42, 242 and 252. It can be seen that this base region 106 is common to the collector regions 104 and 124 of the two-emitter vertical NPN transistor 72 and provides the necessary connections (see also FIG. 5). The PN diode 210 is connected to the PNP transistor 108
Is formed by the emitter-base junction. Collector region of parasitic PNP transistor 108
112 and 110D are formed in the same manner as the PNP emitter 136 and are connected to the standby emitter 70 of the multi-emitter transistor 72 and the base regions 110SB and 110D of the data read emitter 78. These base areas (110SBB
And 110D) are both formed by locally injecting a P-type material,
The ion implantation dose and energy are varied to give different β. It will be apparent that the base depth of the data emitter 78 is sufficiently thicker, i.e., deeper than the base associated with the standby emitter 70, to obtain a modified beta which is important for the functioning of this device. (Alternatively, this can also be achieved by making the doping of the base below the data emitter region 78 higher than the base below the standby emitter 70.) The contact to the emitter regions 70, 78 This is done through the N poly layers 144, 146 as shown in FIG. 6B. The necessary contact of the base region of the multi-emitter transistor 72 is made by the P-poly region 148.

As mentioned above, the circuits shown in FIGS. 5, 6A and 6B
It exhibits mixed characteristics of PNP load cells and diode load cells. As apparent from FIG. 6A, the emitters 70 and 78 of the multi-emitter transistor 72 are connected to the base 11 of the inner emitter 78.
A different β is provided by making 0D thicker than the outer emitter 70 with a thin base 110SB. Outer emitter 70 has a high β with its thin base 110SB. Two transistors having substantially different β, or a NP having a parasitic PNP transistor 108 and an emitter 78
By providing sufficient current to the bit line in read and write modes (preferably 1 mA selected), the product of β of NPN and β of parasitic PNP, since β of the N transistor drops significantly at high currents. It becomes smaller than 1. Therefore, writing is easy because the parasitic PNP transistor 108 and the NPN transistor 72 do not saturate. Since there is a 500 ohm resistor 116 in series with the emitter 114 of the non-saturated parasitic lateral PNP transistor 108, a PN diode is loaded in series with the NPN transistor 72 so that writing to this cell is easy.

The PN diodes shown at 200 and 210 in FIG.
6A can be incorporated into the structure of FIG. 6A using any of the structures shown in FIG. For example, FIG. 7A shows the formation of a PN diode by adding a metal contact 150 on a P ⁻ -type region 152 formed in the Nepi layer 124. In FIG. 7B, a diode is defined by using a P ⁺ poly region 154 on a P ⁻ type region 152. In FIG. 7C, the P region 152 and the N ⁺ region 156
A metal contact 150 is provided thereon to form the PN diode of the inverting transistor. Neither of these structures is compatible with the products and processes shown in FIGS. 6A and 6B.

From the above description, it can be seen that a bipolar memory cell is provided that has improved write characteristics for faster write times, has faster write recovery time, and is highly insensitive to alpha particles. Let's do it. Many modifications can be devised by those skilled in the art from the specification to the above-described embodiment.

Other refinements of the invention are modifications of the embodiments that will become apparent to those skilled in the art from this specification. Accordingly, the invention is not limited except as by the appended claims.

[Brief description of the drawings]

FIGS. 1, 2, 3 and 4 are circuit diagrams showing prior art solutions to memory cells, FIG. 5 is a circuit diagram of a preferred embodiment of the present invention, FIG. FIG. 7 is a schematic diagram of a PN diode that can be employed in the structure of FIG. 6; 2,4,72,82 Multi-emitter NPN transistor 14,16,70,84 First (standby) emitter 17,74 Standby current drain line 18,22,78,86 Second (read ) Emitter 20,88 First bit line 24,80 Second bit line 26,102 Row selection line 28,30 Load PNP transistor 40,42 Schottky diode 44,46,100,116 Load resistance 52, 54 Capacitor 56,58 NPN transistor 74 Current source 94,108 Parasitic PNP transistor 120 P ^- silicon substrate 122 N ⁺ layer 124 N ^- layer 128,130 Oxide or trench 132 ...... silicide layer 136 ...... P regions 138 and 148 ...... P poly layer 140,240,250 ...... N regions 142,242,252 ...... N poly regions 144, 146 ...... N poly layer 150 ...... metal layer 152 ...... P ^- region 154 ...... P ⁺ Poly layer 156 …… N ⁺ area

Claims (7)

(57) [Claims] 1. A first and second multi-emitter NPN transistor (72,82), each of which is a read emitter (78,86) coupled to a first or second bit line. Standby current line (7
4) coupled to the standby emitter (70,84), collector (104,96), and the other multi-emitter transistor (8
A first and a second multi-emitter NPN transistor (72,82) having a base (110,111) cross-coupled to said collector (96,104) of said second multi-emitter; The collector (104) and the base (1) of the transistor (72)
A first PNP transistor (108) having a base (106) and a collector (112) respectively coupled to the emitter (99) and the collector (96) of the second multi-emitter transistor (82) And the base (11
The base (98) and collector (9
2) a bipolar memory cell comprising a second PNP transistor (94) having first and second resistors (116, 100), which have first and second ends respectively. Having the first
Are coupled to a row select line (102), and each of the second ends is coupled to an emitter of the first and second PNP transistors (108, 94), respectively. Each of the PNP transistors (108, 94) has a relatively low current gain for the read mode current and a relatively high current gain for the standby mode, and during the read mode, Each of the PNP transistors (108, 94) has a PN formed by its emitter-base junction.
Functioning as a diode (210,200), the multi-emitter transistor (72,82) when the standby emitter (70,84) conducts standby current
Is loaded by the first or second PNP transistor (108,94) in series with the first or second resistor (116,100), where β _PNP × β _NPN >1; And a pair of the first multi-emitter transistor (72) and the first PNP transistor (108) and a pair of the second multi-emitter transistor (82) and the second PNP transistor (94). To increase the resistance to alpha particles, and when the read emitter (78,86) conducts a read current,
The multi-emitter transistor (72,82) is loaded by the PN diode (210,200) in series with the first or second resistor (116,100), wherein β _PNP × β
_NPN <1, which condition prevents the latching of the bipolar memory cell and causes the first and second resistors (116, 10
0) has a resistance large enough to maintain the state of the unlatched bipolar memory cell,
In order to shorten the writing time, the transistor (72,8
2,108,94) have a resistance low enough to prevent saturation of either of the bipolar memory cells.
A high speed bipolar memory cell which operates as a load switching cell. 2. The first and second PNP transistors (10).
8. The bipolar memory cell according to claim 1, wherein each of said NPN transistors is a lateral PNP transistor parasitic to said PN diode. 3. The bipolar memory cell of claim 1, wherein each of said first and second resistors has a value of about 500 ohms. 4. The bipolar memory cell according to claim 1, wherein the value of the read current is 0.5 to 1 mA, and the standby current is 1 to 10 μA. 5. The multi-emitter NPN transistor (72,
2. A bipolar memory according to claim 1, wherein said memory device (82) exhibits a lower current gain in connection with said read emitter (78,86) than in connection with said standby emitter (70,84). cell. 6. The multi-emitter NPN transistor (72,
2. A bipolar memory cell according to claim 1, wherein (82) has a greater base width in relation to said read emitter (78,86) than in relation to said standby emitter (70,84). . 7. The multi-emitter NPN transistor (72,
2. A bipolar memory as claimed in claim 1, wherein (82) has a more highly doped base associated with said read emitter (78,86) than associated with said standby emitter (70,84). cell.