CA1152646A - Memory cell for a static memory and static memory comprising such a cell - Google Patents
Memory cell for a static memory and static memory comprising such a cellInfo
- Publication number
- CA1152646A CA1152646A CA000342353A CA342353A CA1152646A CA 1152646 A CA1152646 A CA 1152646A CA 000342353 A CA000342353 A CA 000342353A CA 342353 A CA342353 A CA 342353A CA 1152646 A CA1152646 A CA 1152646A
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- Prior art keywords
- regions
- transistors
- collector
- memory cell
- diodes
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/10—SRAM devices comprising bipolar components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Abstract
ABSTRACT
A memory cell, destined in particular to be integrated in a static memory in large numbers, comprising a semiconductor body having two transistors with cross-coupled base and collector regions. A load-element is formed by p-n diodes of which at least one of the anode and cathode regions consist of polycrystalline silicon. The collector regions of the transistors are conduct-ively connected to those regions of the diodes which are of the same conductivity type as the collector regions.
A memory cell, destined in particular to be integrated in a static memory in large numbers, comprising a semiconductor body having two transistors with cross-coupled base and collector regions. A load-element is formed by p-n diodes of which at least one of the anode and cathode regions consist of polycrystalline silicon. The collector regions of the transistors are conduct-ively connected to those regions of the diodes which are of the same conductivity type as the collector regions.
Description
~lSZ646 .. _ "Memory cell for a static memory and static memory com-prising such a cell".
The invention relates to a static memory cell, par-ticularly destined to be integrated in a static memory in large numbers, comprising a semiconductor body having two transistors with cross-coupled base and collector regions, the collector regions being connected to a load element comprising a diode. The invention further relates to a stat-ic memory having such a memory cell.
The memory cells may be formed, for example, by generally known flip-flop circuits in which the collectors can be connected, via the load elements~ to a common line (for e~ample supply) and in which ~irst emitter regions are connected in common to~ for example, a current source and second emitter regions are connected to read/write lines.
~or a stable ~lip-flop it is necessary that the loop gain in the meta stable point be larger than 1. Start-ing from a current-voltage ~aracteristic of the emitter-base junction ic = Io exp (kTbe ) it can be found out that it follows ~rom this condition that the impedance ~ of the lead elements must be larger than kqi~ where k is Boltzmann's constant, T is the absolute temperature, q is the elementar~T
quantity o~ charge and i is the current.
During operation, for reading the cell a comparative-ly large read current, for ~xample, 1 m~ is used in con-; nection with the access time. With these large read current~, a load element having a comparatively small resistance couldbe used. Xn the stand-by condition in which the cell is not read but in which information should remain stored, a CUl'-rent which is as small as possible is conveycd through the cell rOr reasons o~ dissipation. T~c contraclictory require-ments are i~posed upon the load element, namely a low im-pedance in connection with the comparatively large read cur-rents and a high impedance in connect;ion with the comparati-vely small stand-by currents. In practice the impedance o~
'~
~5Z646 16-10-1979 -2- P~N 9314 the load element can be chosen to be so that a ratio read current/stand-by current of approximately 5 can be obtained when linear resistors are used.
L~rger values for this ratio are desired for ob-vious reasons but usually they cannot be realised when alinear resist~r is used as a load element, in particular because technologically very large resistors are difficult to make accurately and inter alia because with large resis-tances the read currents are restricted by the available usual supply voltages.
A memory cell having a non-linear load element, namely a resistor with a parallel arra3~ged diode, is described in the article "A 1024 - Bit ECL RAM with 15-ns Access Time " by Ronald Rathbone et al., published in IEEE International Solid State Circuits Conference 1976, pp.188/189. The stand-by current may have a comparat:Lvely ; low value (15 /uA). When reading the cell, the greater part of the current can be passed through the diode so that a higher value can be choscn for the resistor and hence a lower value for the stand-by current than in the absence of the diode. In the article by A. Hotter et al "A high-speed low power 4096 x 1-Bit bipolar RAM" published Oll the I~FE International Solid State Circuits Conference 1978, ; Digest of Technical Papers, ~.98/~9, it is stated that a 25 ratio read current/stand-by current of approximately 10 can be obtained by using such a load element. It is moreover stated in this article that, by connecting a pnp transistor across the load element, a further reduction o~ the stand~
by current (4 /uA) and hence of the dissipation can be ob-30 tained while maintaining the short access time~ as a result of which it is possible _ter aLia to considerably increase the number of memory cells in a semiconduc-tor body without detrimental reslllts of a corresponding irlcL~ase of the dissipation.
Due to the ai)ove-me3ltioned stabi:Lity condition~
the ratio read current/stal~d-by curreIlt in these cell alsG
cannot be c~osen arbitrarily large.
A further disadvantage o~ resista3lce elements is ~lS2646 that they occupy comparatively much space in the semicond1c-tor body and that the more so according as the resistance value is higher. Reduction of the resistance elements is often difficult in connection with the electrical properties of other circuit elements or it makes the process of manu-facturing the memory device extra complicated. United Stated Patent Specification 3,585,412 describes a flip~lop circuit using as load elements Schottky diodes connected in the reverse direction which behave as resistors but occupy little space as compared with usual resistance elements.
However, these diodes show the above-described disadvantages of linear resistance elements. Moreover, as a result of the provision of a Schottky diode with the desired reverse voltage characteristic, the manufacturing process of the device generally becomes considerably more complicated.
It is an object of the invention to provide a memory cell of the kind described in the opening paragraph in which the ratio read current~stand-by current rnay be larger than in known cells of this type.
A further object of the invention is to provide a memory cell which has a compact construction and can be manufactured simultaneously by means of the usual process steps.
The invention is based inter alia on the reCOgnitio of the fact that a large ratio read current/stand-by current can be obtained when per brancll of the memory cell the voltage amplification dVce , at least within the current dvbe -voltage range in ~hich it should be possible to operate the device, is entirely or at least substantially entirely independent of` the value of the electrical current. The in-vention is furthermore based inter alia Oll the recogni1;ion ol the f`act that such a currellt-independent voltage am-plification can be obtained by using a rectif`ying junction as a load element the current-voltage characteristic oI
which :in the for~ard direction comprises a ~actor exp.
(~V/rl~T)~ where m 1.
~ memory cell according to the invention is ~15Z646 characterized in that the load element comprises a p-n diode of which at least one of the anode and cathode re-gions is of polycrystalline silicon and in which the col-lector regions of the transistors are conductively con-nected to those regiolls of the diodes which are of the sameconductivity type as the collector regions.
Experiments have demonstrated that p-n diodes consisting entirely or partly of polycrystalline material comprise an exponential factor qV/mkT in their forward character~stic, where m is larger than 1.
This quantity m is a non-ideality factor which re-presents the deviation of this type of diodes with res-; pect to usual monocrystalline diodes. Probably as a result Or intor alia the short life of minority charge carrier.s, m (which in monocrystalline diodes can be assumed to besubstantially equal to 1) is larger than 1 and can be varied around m = ~ within a certain range by the way of manufacture. It can be found out in a simple manner that when such a diode is used as a load element~ the voltage a~plification dVce is substantially equal to m and hence dV
be is substantially independent of the current. Since the range within which this applies extends over a large num-ber of decades, a very low value may be chosen for the stand-by c~rrent while nevertheless the stability condition is satisfied. As a result of this the dissipation in the cell can be maintained very small.
Since resistors are not necessary, the dimensicns of each cell can be made very small so that the cell is particularly suitable for being integrated in a memory in large numbers. Moreover, as will become apparcnt from the description of the figures, the diodes can be manufac~
tured by means of process steps ~Jhich are conventionally used in semiGonductor technology.
For the voltage difference ~ V between t]le col~
lectors~of the transistors it ho]ds in the stabl~ state to an approximation that ~ V -- q ll~ ~ (at least in the usual case in ~rhicl ~ ~ 10 and rn ~ 1.5), where ~ is the ~52646 current amplification of the transistors. The factor m of the diod0s should be so large that ~ V is sufficiently large to maintain the stability o the cell with a given value of possible disturbances. In a fa~ourable embodiment, therefore, diodes are used as load elements in which a voltage difference between the collectors of the transis-tors of at least 150 mV and preferably between 200 mV and 400 mV exists. Large voltage differences of, for example, 500 to 600 mV are preferably avoided because in this case the conductive transistor is saturated (bottomed) so that, as a result of charge storage, the write velocity of the cell is reduced. Very favourable results have been obtained in a construction with diodes in which ~ V was approximate-ly 250 mV. In usual transistors in which the current ampli-fication factor ~ is between approximately 10 an~ 100,diodes are used with an m-factor which is approximately equal to 2. Diodes in which m is smaller than 1,5 are pre-.~! ferably avoided because the voltage difference between the collectors and hence the difference in logic levels n between the two stable states then becomes too small in many cases.
In an important embodiment the diodes on either sideof the p-n junction consist of polycrystalline silicon material. As will become apparent from the description Of the figures, the diodes can be manufactured simul-taneously with the provision of active zones in the mono-crystalline semicond~ctor body via a previously grown polycrystalline silicon layer of a conduccivity type which is opposite to that of the said active ~ones. In another embodiment which can be manufactured substantially entirely by means of standard methods, only one of the anode and cathode regions of the diodes is formed by polycrystalline silicon material, while the other region is formed at least substantially by a monocrystalline part of the semiconductor body which has a higher doping conccntration~ for e~ample 10 times higher, than the polycrystalline part of the diodc.
Thc properties of these diodes do not differ much from those of polycrystalline diodes since the greater part of the ~L152646 .
injected charge carriers is injected, by the monocrystalline part of the diode, into the polycrystalline part where the recombination rate is comparatively high as a result of the concentration difference in doping. Advantageously the recombination rate can be increased by providing a metal layer above the ~-n junction.
A first important embodiment of a memory cell in accordance with the invention is characterized in that the transistors comprise two emitter regions which are co~lected to a supply line and two emitter regions which are con-nected to read/write lines and in which the collector regions are connected together via the said p-n junctions.
This cell which inter alia has the advantage that the way of operation is very simple, in principle needs 4 lines, namely two supply lines or word lines and two read/write lines.
A second important embodiment of a memory cell in accordance with the invention which, as compared with the above-mentioned construction, is operated in a slightly more complicated manner but which has the advantage that in principle only three lines per cell are required, is characteri~ed in that the transistors each comprise only one emitter region which is connected to the emitter region of the other transistor and the collector regions are connected to separate read/write lines via the said ~-n diodes serving as load elements. A semiconductor memory comprising a semiconductor body having a surface-adjacent matrix of such memory cells arranged in rows and columns is characterized in that the surface has a system of crossing conductor tracl~s which form the said read/write lines and which are connected to p-n junctions in the rows ~nd columns, respectively, o~ memory cells.
A particularly compact integration due to the ~act that the emitter regions per cell are common, can be ob-tained iIl a preferred embodiment which is charactcri~edin that tlle trans:istors are formed by inverted transistors in which7 viewed on the sur~ace, the baHe region is situated below the collector region and the emitter region is ~52646 16~ 197g -7- PHN 9314 situated below the base region of each transistor, and in which the semiconductor body comprises a number of juxta-posed, mutually separated strip-shaped regions of the first conductivity type which extend parallel to the rows or columns in the semiconductor body and form common emitter regions of the transistors belonging to the same row or column. A further favourable embodiment which presents impor-tant advantages both because the transistors themselves may be very small and because the ~-n junctions do not require any extra process steps, is characterized in that the surface of the semiconductor body has an insulating layer which, at the area of the transistors, shows windows wllich define the base regions of the transistors and which are closed by a layer of polycrystalline silicon deposited in the windows and on the insulatlng layer and showing the same conductivity -type as the base regions, the collector regions being situated below parts of the polycrystalline silicon layer of which the conductivity type has been changed b~-doping, said parts extending over the insulating layer and 20. forming there the sa.id p-n junctions with parts the con-ductivity type of which has not been changed by doping.
The invention will now be described i.n greater detail.
with reference to a few embod:iments and the accompanyil~g drawing, in which Fig. 1 is a circuit diagram of a known flip-flop memor~7 cell;
Fig. 2 is a circuit diagram of a lip-flop-memory cell according to the invent:ion;
Fig. 3 is a plan view of a part of a memor~r cell according to the invention;
Fig. 4 is a cross-sectional vi.ew of tlle levice shown in Fig. 3 talen on t~e line I~J I~';
Fig. ~ is a plan view of a part of another cmbodime]lt;
of a memory matrix according to thc invention;
Fig. 6 is a sectional v:iew o:t this dc~i.ce ta~e on th~ line VI-~7~;
Fig~ 7 is an clcctric diaglan1 of a part of a memory ~ccordirlg to anothcr embodimerlt of t;hc inven1:ion;
Fig. 8 is a plan view of a part of a memory according to the diagram of Fig. 7;
which is on the same sheet as Fig. 7, Fig. 9,/is a sectional view taken on the lines IX-IX
of Fig. 8; which is on the same sheet as Fig. 7 Fig. 10Jis a sectional view taken on the line X-X
of Fig. 8;
Figs. 11 to 13 are sectional views of a transistor used in the memory shown in Fig. 8 during a few stages of the manufacture thereof;
Fig. 14 is a plan view of a further embodiment of a memory cell in accordance with the invention;
It is to be noted that the figures are diagrammatic and are not drawn~; to scale.
Fig. 1 shows the circuit diagram of a static memory cell of a known type having t~o transistors T1 and T2 the base and collector regions 1 and 2, respectively, of which S are interconnected crosswise. The collectors 2 are connected, via load elements 3, to a supply line 4 which in the case o~
a memory is used as a word line. The transistors each com-; 20 prise two emitter regions 5 and 6, the emitter regions 5 ; being connected to the (word) line 7 and the emitter regions 6 being connected to the write/read lines 8 and 9. In the most conventional known constructions the load elements 3 simply consist of resistors.
During~ operation, a comparatively large current i is passed through the cell for reading in connection with a desired reading velocity, and a emaller current is passed in the stand-b~ condition to restrict the dissipation. These different current values lead to different desired vallaes for the impedances 3~ as will become apparent hereinafter.
The starting requirement is that in the metastable point per branch it should hold for a stable flip-~lop circuit for the gain factor dV d~J
d~ l~e dVb ( 1 ) where ~ Vc and ~ Vb are voltage variations at 1;he collector and the base regions, respectivel-y. For t;he emittcr-base junctio1l of the transistors T1, T2 the diode equation ~S2646 (kT ) (2) holds to an approximation, wherein ic is the collector cur-rent, q the elementary quantity of charge, Vbe is the for-ward voltage across the emitter-base junction, 1 is Boltzmann's constant and T is the absolute temperature.
From equation (2) it can be derived that with a voltage variation . Vbe for the current variation i it holds that:
~ic = kT ~ Vbe : 10 For the case in which the elements 3 simply consist of resistors having resistance values R, it follows from equations (1) and (3) that:
R ~ kT (4) The minimum value of R hence depends on the current and 5 that in that sense that with a large current a small re-sistance will suffice, whereas with a small i the resis-. tance R should be large.
Since furthermore in practice the voltage differencebetween the collectors of the transistors usually is pre-20 ferably at least 100 to 150 mV, the ratio between the readcurrent and the stand-by current will usualLy be only low (srnaller t~Lan 10).
It is known that the dissipation can be reduced, as already described in the preamble, by uslng a non-linear 25 resistance eleD1ent which can be obtained, f'or e~:ample, by connecting a diode parallel across the resis-tor as is shown in Fig. 1 irL broken lines. With such a non-linear resis-tance element in which the di.fferential resistanc~ decreases when the value of the current increases, a considerable improve~ent 30 in the ratio read current~stand-by current CaJl be effected.
However, a f'urther increase of the read curre~t/stalld-by current would often be desired..
~ rom thc point of vi ew c-~ packing density, further resistance elemen-ts having large resi.stance values are 35 undesired d1le to the comparati.vely l.arge space thcy use to occupy- in tl1.e semicon.ductor bocly.
Fig ~ shows a circuit diagraln of a fli.~ `lop oell accordin~ to t'he inven';:i.onc Insl;oad of res:i.stors 3 the ce:Ll ~526~6 - 10 - PHN. 9314 comprises load elements consisting mainly of diodes 11 the cathodes of which are connected to collector regions 2 of the transistors Tl and T2 and the anodes are connected to the word line 4 so that during operation the diodes are forward-biassed. In order to obtain a sufficiently large impedance which, on the basis of the stability condition imposed in equation (1), should be larger than that of the emitter-base junction, at least one of the anode and cathode regions of the diodes 11 is made of polycrystalline silicon.
This type of diodes shows a current-voltage characteristic which (within a certain range) can be described by id = Io exp ~ (5), where _ > 1. It can be found out in a simple manner that in this case it holds for the amplification from equation (1) that ~ Vce = m Within the current-voltage range wherein the diode equation (5) applies, the voltage gain a Vce is substantially ~ Vbe independent of the current and is larger than 1, so that the stability condition at the metastable point the loop gain should be larger than 1 is satisfied. Because the range within which this applies generally is very large (5 to 6 decades), the current can be varied over a large range, which means that the read current can be very large (1 mA) and the stand-by current very small and can even be selected to be in the order of magnitude of 1 mA while the cell nevertheless remains stable.
When a current 1 is passed through the conductive transistor and the current gain ~ of the transistors shows a usual value (for example at least 20), a current of substantially i/~3 which forms the base current for the conductive transistor flows through the diode 11 which is connected to the non-conductive transistor. It can be derived from equation (5) that the voltage difference ~ V
between the collector regions 2 of the transistors is equal to mkT in ~ , and hence (at least in 1 order) q `i~ ~b4b is substantially not dependent on the current. The ~oltage differellce a v should be so large that with a given value o~ noise the cell nevertheless remains stable. With a given value of the current gain factor ~ , therefore, diodes 11 are used having such a factor m that ~ V is at least approximately 150 mV and preferably at least approximately 200 mV. An upper limit of preferred values of the quantity m is determined inter alia by the velocity of the memory cell. The conductive transistor which is saturated can be-come bottomed at a large voltage difference, for example,a voltage difference of 500 to 600 mV~ so that the writing velocity is reduced. Therefore, the rn-factor of the diodes 11 preferably has at most such a value that, at a given value of ~ , the voltage difference ~ V between the col-lector regions 2 is at most 500 mV. ~a~rourable resultshave been obtained in practical constructions with diodes having an m-~actor of at least 1.3 and approximately equal to 2 in transistors having a ~ in the order of magnitude between 30 and 100, so that a voltage difference ~ V was 20 built up of approximately 150 to 250 mV.
Figs. 3 and 4 are a plan view and a sectional view, respectively, of a part of a practical embodiment o~ a memory in accordance with the inve~tion. The device com-prises a semiconductor body 12 o~ a conventional construct-ion consisting o* a ~ type substrate 13 and an n-type epitaxial layer 14 adjoining the upper surface 15. A number of islands 16 are formed in the epitaxial layer and are arranged in groups of two which comprise the transistors of a memory cell. Within the epitaxial layer the islands 16 are bounded by insulation regions 17 ~hich in th-s case are formed by p~type zones prov-ided in the la~-er 14 but which, O:r course, may also consist of insul~ting material~ for example, silicon oxideS sunl~ in the semi-conductor body and obtained b~ Local oxidation of the epitaxial layer 14. T~le islands 1~ themselves constitute with the highly doped buried n-type 3ayers 18 a-t the inter~ace between the epi*ax-ial la~er and the substrate and ~ith the hi~hly doped n-type collector contact zone 1~ t-he collcctor rcgiolls o-` lhe ~;2646 t6~10-197~ ~12- PHN 9314 transistors. In the usual manner the base regions in the form of tle ~-type surface zones 20 and the emitter regions in the forn1 of the n~type surface zones 21 and 22 are provid~
ed in the isl~lds 16 by means of diffusion or ion implan-tation. The surface 15 is covered with an insulating layer23 having windows to provide contacts with the emitter base and collector regions of transistors.
It is to be noted that the transistors in Fig. 3 are shown only very diagrammatically. For example, the 10 buried layers 18 are not shown and the contours of the emit-ter regions 21 and 22 and the collector contact zones 20 which coincide substantially with the ContDUrS of the con-tacts between said regions and the ~ord lines and the read~
write lines are not shown either.
A pattern of conductor tracks 24 of p-type poly-crystalline silicon is formed on the oxide layer 23, which tracks change into collector connections 26 of n-type poly-crystalline silicon via the ~-n junctions 25 forming the load elements of the flip-flop, as described with reference 20 to Fig. 2. The tracks 24 form one of the word lines of the memory corresponding to the lines 4 in Fig. 2. The word lines corresponding to the lines 7 in ~ig. 2 are formed by the conductor trachs 27 which are connected to the emit-ter regions 22 and, as the collector connection 26, may be 25 constructed from n-type polycrystalline s:ilicon. The e~litter regions 22 are connected to read/write lines 28, 29 extend-ing in the column direction. These lines may be constructed in a second layer of wiring, for exatnple of Al, which is insulated electrically from the lines 24, 27 by an inter-30 mediate oxide layer~ The crossing connections 30 betweenthe base reg:ions 20 and the collector regions 16 oI the transistors may also be malluI`actured in this layer of ~iring, The polycrystalline si]icon material of the word 35 lines 24 and 27 is formed in known manncr by decomposition of SiM4 at low pres~ure (appro~imate7y 0.~ mm Ilgj at a temperature of approximately 61~o C. l`he g~rowth rate was appro~imately 100 ~/mill~ In these circums-taIIces~ polycrys-.... .. .
~5Z646 16-10~1979 _13_ PHN 9314 talline silicon material was obtained the factor m of ~hich was approximately equal to 2. Ho~ever, the process condi-tions may be varied such that the polycrystalline materiaJ
differs more or less from monocrystalline silicon, for example, by changing the growth rate so that the ~rain size and the concentration of trapping centres and hence also the m factor changes. In general it may be said that the various process parameters can simply be chosen by those skilled in the art in such manner that diodes having pro-perties which are most favourable for a given application areobtained.
Figs. 5 and 6 are a plan view and a sectional view, respectively, of a modified embodiment of the above-described memory matrix. Only one memory cell of the ~latri~
1~ is shown in these figures but it will be obvious that a memory ~atrix of memory cells as shown in Fig. 5 can be ob-tained in the same manner as in t;he preceding embodiment.
Furthermore, in the~e figures the same reference numeral3 are used for correspo~ding components as in the preceding embodimcnt.
In contrast with the preceding embodiment, only one of the anode and cathode regions is of polycrystalli~e silicon, while the other region i~ formed at least sub~
stantially by a monocrystalline part of the semiconductor-25 body. For this purpose9 the polycrystalline word lines 24are situated immediately above the collector regions 16 and, at the area of windows in the o~ide layer 23, adjoin the collector regions 16 of the transistors, The poly-crystalline paths 24 which ,as in the precedin~ embodiment, are of the ~-condllctivity type9 f`orm the ~n junctions 31 wit;h the collector regions 16 substantially at the area of the interface bet~een the polycrystalline ~nd the mono--crystalline rn~terial~ These p-n junckions~ e the ~n diodes 11 in the precedin~ embodilrlent5 for~n the load elcmentc ; 35 of t;he memory elements. In ordcr to obtain a suita1~lc gain, for this purpose the doping concelltrLltion on the mono-crystalline cathode side of the dio~e is chosen to ~c hi~hcr~
prefc-~ral~1y at least 10 ~ bigher, tilall 011 thc polycrystal~-inc :~52646 anode side. At least for the purpose for which they are used here, the characteristics of such diodes prove to have substantially the same propcrties as diodes containing both an anode and a cathode pf polycrystalline silicon. An explanation for this is that at the given concentration difference between the anode and the cathode, the greater part (for example 90%) of the current across the diode is formed by charge carriers (electrons) which are injected into the polycrystalline paths 24 from th.e collector 16 and, in particu.lar as a result of the recombination centres present there to a comparatively large extent, disappear again by recombination. The desired concentration difference can be obtained in a very simple manner by providing, at the area of the ~-n diodes 31, a highly doped low-ohmic collector contact zone 19 which is usual in conventional circuits and has a doping concentration of 10 - 10 1 atoms/cm3 and choosing the doping concentration of the po-lycrystallin.e paths 24 to b~ between approximately 10and 1019.
Since the word lines 24 are situated immediately above the collector contact windows in the oxide layer, the dimensions of the cell can be particularly small.
In those cases in which it is important for the resistance in the word lines to be kept low, a laycr of a 25 readily conductive material, for example alumini.u~, may be provided on the polycrystalline paths 24. However, the word lines may also be substantially entirely of aluminium a~ld also comprise only locally strips of polycrystalline silicon in which -the ~-n junction is formed. Fig. 14 is a 30 diagrammatic plan view of such a modified embodiment. The word lines are shown diagrammatically by a line WL and are fo~ed by tracks of Al extending Prom the left to the right above the semiconductor body. The p-n diodes 25 are formed in strips 24, 26 oP polycrystalline silicon extendi.ng only 35 het~een the collector contacts 190 Thcse strips compr:~se a ~-typc portion 2~ which is co~ acted wi-th tne Al stri~
WL, and an n-type porcion 26 which is connected to the collector con.tac-t æone 19 and is insulated from the ~ord ~52646 line WL by an insulating layer of, for example, silicon oxide.
In the memory device described so far~ each cell comprises at least four address lines, namely two bit/read lines and two word lines which also ensure the supply of the cell. The following embodiment relates to a memory in which the supply of the memory cells is provided at least partly by one of the bit lines so that only th~ee lines per cell will suff`ice instead of four and hence a further reduction of the space which the memory occupies in the semicon~uctor body can be obtained.
Known memory cells of this type having only three address lines are described inter alia in the article "A four device bepilar memory cell" by Raymond Ao Heald, published :in IEEE International Solid State Circuits Conference, 1978, pp 102-103. These kno~in memory cells comprise as load elements in the collector tracks of the cross-coupled inverter transistors complemelltary transis-tors which are of the ~ t~pe, so transistors of the 20 pnp-type.
.
According to the invention, poly-poly ~-n diodes or poly-mono p-n diodes are used as load elements the ~orward characteristic of which comprises a factor exp (qV/mkT) wheren1 is larger than 1, so tha-t again a particularly simple and compact configuration can be obtained.
Fi~. 7 shows a circuit diagram of a part of a mat;rix configuratioll. The trans:istor~s T1 T8 each comprise only one single emit-ter since the supply lines also fulfil at least partly the function of` bit lines. The supply line XL1 X I2 etc. connects the esnitters of the cells of` a word to a current; source 40, 41. The word lines ~ I con-nect ~he anodes of the diode~ D1, D3, D~, D7 ~o vo~tage sources V~ , V , etc. The lire5 Y .~ g Y2 etc. connect in the same manner the cells column-~wise to the ~oltage sources Vy , Vy etc. The Y lines are Inoreover connectcd to read means 2 42s 43~ which f`or simplicity are shown as ammeters .
The device may be operated~ f`or cxc~mple~ as Iol30ws:
1~52646 16-10-197~ -16- PHN 9314 Stand-by: In the quiescent state the voltages Vx and Vy are assumed to be equal. The cells are in one of the two stable states. For example, when the cell with the transistors T1 and T2 and the diodes D1 and D2 is chosen as an example, much or little current passes through the diode D1, dependent on that position, namely a base cur-rent (to T2) or a collector current (to T1).
Writin~: Assuming the cell to be in that condition in which the transistor T1 conveys curr~nt, the cell may be set in a different state by increasing Vx and simultaneou~s-ly reducing Vy , so that the collector current through T
is increased and the base current to T1 is reduced, res-pectively. With a given voltage variation the base current to T1 becomes so small that the transistor T1 is cut off for lack of sufficient amplification. The transistor T2 will become conductive. For the right-hand neighbouring cell (T3~ T4) only Vx is increased and for the neighbourin~
cell (T57 T6) only Vy is increased. With a suitable choice of the voltage variatlon this half selection is insufficient to switch said cells. It is not necessary to increase the currents IX ~ IX ~ etc. during writing, but the velocity of writing can be increased by it.
Readin~ Because uporl reading a given cell the other cells in the same colurnn also provide a contribution to the overall current through the Y lines~ it is advantageous to give th0 selected row much more current than the other rows, by means o:~ the current sources 40, 41 etc. The informatio may ther be read by finding out via the means 42 whether a comparatively low base current flows through the relevant Y
line or a high collector current. This differerlce may be extra emphasized by mak:ing Vx h-igher than ~y.
In prir.ciple a whole row is read simultaneously but it may be ensured by means of a post-selection that the infol-mation of only o~e cell ema~ates.
Th~ ~oltage dif~erence ~ V wllich is to be arJplied betweeIl the associated ~L and y lirJes for writing infor-m~tion in a givelL cell ~ill dep-nd both on the factor ln and on ~ D the t~hle be10~Y 9 for various ~alucs of f~
` 1152646 16-10-197~ -17- PHN 9314 and m = 2, the associated values of ~ V are recorded obtained from computer simulations.
~ ~V (mV) These values prove substantially to satisfy the 10 general equation:
av = q ln ~ - 2 q ln 2~
to be determined analytically.
For a specific value of ~ of approximately 30, this voltage is approximately 52 mV. For writing, in which each 15 time the condition of one single cell may be flipped over, a voltage ~ a v is applied to the x and ~ line. 40 mV may be chosen, for example, for this ~ V. Writing may therefore b~ carried out as follows.
Write "1" Vx1 = +4 m~, VY1 = -40 mV - ~ T2 conducts 20 Write "0" Vx1 ~ o mV, VY1 = ~40 mV - ~ T1 conducts.
~ ig~ 8 and Figs. 9 and 10 are a plan view and sectional views, respectively, of a part of a semiconductor device having a matrix of the above-described memory cells.
The device comprises a semiconductor body 45 of the usual 25 composition having a substrate 46 of ~-type silicon and a layer 47 of n-type silicon deposited thereon. ~ n~mbcr of islands 49 separated from each other by p-type zones 48 are formed in said epitaxial layer and, in the plan ~iew shown in ~ig. 8, extend from the left to the right. Highly doped 3~ buried n-type zones 50 corresponding to the address lines XL1, XL2 etc., of the transistors of the memory cells, to be operated inversely, are provided between the islands 49 and the substrate 46. I`he ~-type ~ones 51 are provided in the n~typc- islands and forrn the base zones of the transis-35 tors T1, T27 T3 etc.~ and the n-type surface zo-nes 52 are provided in the ~-type zones 51 and form the collectors of the transistors. It is to be noted that -the transistors of the memory cells associaled with a conln1o}l word line ~L
~52646 16_10-1979 -1~- PHN 9314 are provided in a common island due to the~act that the transistors are used inversely, the lowermost n-type region 50 serving as emitter and the uppermost n-type region 52 serving as collector region. In addition to im-portant other advantages, said inversion permits a par-ticularly compact structure of the memory matrix since, unlike in the preceding embodiments, all transistors are provided in a separate island. As shown in the sectional views of ~igs. 9 ar,d 10, highly doped n-type zones 70 are furthermore provided in the islands 49 and surround the base zones 51 and, by way of example, extend from the surface down to the buried zones 50. In known mamler the current gain of t~e inverse transistors can be improved by mea~s of said zones, while in addition parasitic lateral action between the base regions can be avoided.
The buried zones (50, XL) can be contacted in known manner at the edge of the islands 49 beyond the part of the semiconductor device shown in the figures, ~,hich is shown diagrammatically in Fig. 8 by thc connection wires 53.
-2G Apart from the contacts 53 ~or the emitter regions 50, the transistors T1, T2, T3, etc., ol1ly comprise a window in the oxide layer 5~ which covers the epitaxial layer 47.
Via this aperture, re~erenced 55 in Fi~. $, both the ~ase zones 51 and the collector zones 52 are provided with an 25 electric connection~ These co~mections are denoted by reference numerals 56 and 57, respectively, and are formed by layers o~ p~type and n-type silicon, respectively, deposited in the windows 55 and on the oxide layer 54. The way in which this type o~ transistor can be marlufactured 30 will be described hereinafter.
The collector colmections 57 change into p type siiiCon paths 59 via the p-n junctions 58. The n-type silicon connections 57s at least in ;o rar as they are not situated in the windows 55 in the o~icle layer 54 im-35 mecliately abo~-e the coJlector rc~ions 57~ and the ~-t~lpe silicon paths 59 are again o~ a polycrystalline structure .50 that the p-n junctiQ~s 58 wllich correspond to the diodes D in the circuil dia~ram o~ . 7, S~10~ a characteristic ~lSZ646 -19- PHN. 9314 which makes them suitable to serve simply as collector load elements.
The polycrystalline paths 57, 59 are covered with an insulating layer 60 obtained by deposition from the gaseous phase or by partial oxidation of polycrystalline silicon material. Conductor tracks 61 are provided on the oxide layer 60 and extend in the column direction of the matrix and are connected, ~ia windows 62, to the ~-type silicon tracks 59 of one of the diodes in each cell. The paths 61 which correspond to the Y-lines in the circuit diagram shown in Fig. 7 and which are shown diagrammatically only in the plan view, may be, for example, of Al. In the same manner, the p-type paths 59 which as anodes are associated with the other diodes in the cells are connected by Al paths 63 extending in the row direction transversely to the column direction of the matrix. These paths which correspond to the X lines in Fig. 7 and which are shown diagrammatically only in Fig. 8, cross the Y lines 61 and may be electrically insulated herefrom by an intermediate layer 64 of, for example, silicon oxide or aluminium oxide or any other sutiable dielectric.
In Fig. 8 the contacts between the XL lines and the ~-type polycrystalline silicon material 59 are denoted by dots.
The polycrystalline silicon may also be used to form the crossing connections between the collector and base regions of the two transistors in a cell. Because the poly-crystalline silicon above the collector region of one transistor is n-type and the`silicon 56 above the base region of the other transistor is p-type so that, in the case in which these two polycrystalline layers 56, 57 adjoin each other (see Fig. 13) and form a parasitic ~-n junction 65, a metal connection 66, for example of Al, is provided on the polycrystalline silicon and interconnects these two parts 56, 57 of different conductivity types and, in the present embodiment, shortcircuits the parasitic p-n junction 65.
For the manufacture of the semiconductor structure, /
.~
- 20 - PHN. 9314 generally known techniques may be used substantially en-tirely which need not be further described here. For the manufacture of the transistors, reference is made in par-ticular to Applicants' Canadian Patent 1,093,702 -January 13, 1981 (PHN 8601) the contents of which is incor-porated in this application by reference. Figs. 11-13 show a few stages of the manufacture of such a transistor. Fig.
11 is a sectional view of a part of the semiconductor body in which the transistor is to be provided after the n-type epitaxial layer 47 has been provided on the ~-type substrate 46 with the buried n-type layer 50 between the substrate and the layer 47 and the island insulation not shown in the drawing. The aperture 55 is formed in the oxide layer 54 on the surface of the semiconductor body by means of known photo-lithographic methods. The aperture 55 which defines the base zone of the transistor is then closed again by means of the layer 67 of silicon which on the surface of the epi-taxial layer 47 shows a monocrystalline or polycrystalline structure and on the oxide layer 54 shows a polycrystalline structure. Paths or tracks which correspond to the poly-crystalline conductor pattern 56, 57 shown in the plan view of Fig. 8 may be formed from the silicon layer 67. The remaining parts of the silicon layer may be removed by etch-ins or be converted into silicon oxide by oxidation.
The remaining silicon layer 67 may then be doped with a ~-type impurity, for example boron, by means of diffusion or by ion implantation methods. At the area of the aper-tures 55 in the oxide layer 54 the boron also penetrates into the epitaxial layer 47 and forms there the ~-type base zone 51 (Fig. 12). The silicon layer 67 is then partly covered with a masking layer 68 which extends partly in the aperture 55 and further above those parts of the layer 67 which are to form the p-type polycrystalline paths 59.
The exposed part of the poLycrystalline layer 67 is then doped with an n-type impurity for example phosphorus, by means of implantation. At the area of the aperture 55 in the oxide layer the impurity diffuses in the semiconductor body and forms there the _-type collector zone 52, Fig. 13.
~lSZ646 The p-n junction 69 between the base zone 51 and the collcctor ~2 e~tends into the layer 67 and divides said layer into an n-type portion 57 and a p-type portion 56 forming a collector connection and a base connection, respectively. Simultaneously with the p-n j~nction 69 the p-n junctions ~8 serving as load elements are formed between the n-type collector comlections 57 and the p-type strips By deposition from the gaseous phase or by oxidation of the polycrystalline silicon strips, the oxide layer 60 may then be provided after which the Al paths XL and Y may be formed in the usual manner.
It will be ob~ious that the invention is not restrict-ed to the embodiments described but that many variations are possible to those skilled in the art without departing ~rom the scope of this invention.
For example~ the conductivity types of the va~ious zones and regions may be reversed, pn~-transistors being used instead of n7~n-transistors.
In order to obtain a higher packing density all the emitter regions in the last example could be connected to one common current source~ Not muc~ changes for writing.
Upon reading, however, the overall interference contribution is mucll larger than the signal. In order nevertlleless to be 25 ab:Le to read, a dynamic read amplifier may be used. The operation then becomes as follows: If` all the ~ lines are kept constant~ the interference contribution is unknown but is constant. By increasing vx1 by a certain voltage, too small to change the condition of the connected cells, a ~ current increase in ~ will be vis:il~le, if T2 conducts ("1") and no current change if T1 conducts ("1")- So the readin~
amplil`ier should be sensitive to small variations super-impo~ed on an -unknown - large direct current.
Reading of the cells in the rirst embodiment may also ,~.
be done in known manncr via a dioae col1necte~l to the collector of` the trarlsistc,rs.
The invention relates to a static memory cell, par-ticularly destined to be integrated in a static memory in large numbers, comprising a semiconductor body having two transistors with cross-coupled base and collector regions, the collector regions being connected to a load element comprising a diode. The invention further relates to a stat-ic memory having such a memory cell.
The memory cells may be formed, for example, by generally known flip-flop circuits in which the collectors can be connected, via the load elements~ to a common line (for e~ample supply) and in which ~irst emitter regions are connected in common to~ for example, a current source and second emitter regions are connected to read/write lines.
~or a stable ~lip-flop it is necessary that the loop gain in the meta stable point be larger than 1. Start-ing from a current-voltage ~aracteristic of the emitter-base junction ic = Io exp (kTbe ) it can be found out that it follows ~rom this condition that the impedance ~ of the lead elements must be larger than kqi~ where k is Boltzmann's constant, T is the absolute temperature, q is the elementar~T
quantity o~ charge and i is the current.
During operation, for reading the cell a comparative-ly large read current, for ~xample, 1 m~ is used in con-; nection with the access time. With these large read current~, a load element having a comparatively small resistance couldbe used. Xn the stand-by condition in which the cell is not read but in which information should remain stored, a CUl'-rent which is as small as possible is conveycd through the cell rOr reasons o~ dissipation. T~c contraclictory require-ments are i~posed upon the load element, namely a low im-pedance in connection with the comparatively large read cur-rents and a high impedance in connect;ion with the comparati-vely small stand-by currents. In practice the impedance o~
'~
~5Z646 16-10-1979 -2- P~N 9314 the load element can be chosen to be so that a ratio read current/stand-by current of approximately 5 can be obtained when linear resistors are used.
L~rger values for this ratio are desired for ob-vious reasons but usually they cannot be realised when alinear resist~r is used as a load element, in particular because technologically very large resistors are difficult to make accurately and inter alia because with large resis-tances the read currents are restricted by the available usual supply voltages.
A memory cell having a non-linear load element, namely a resistor with a parallel arra3~ged diode, is described in the article "A 1024 - Bit ECL RAM with 15-ns Access Time " by Ronald Rathbone et al., published in IEEE International Solid State Circuits Conference 1976, pp.188/189. The stand-by current may have a comparat:Lvely ; low value (15 /uA). When reading the cell, the greater part of the current can be passed through the diode so that a higher value can be choscn for the resistor and hence a lower value for the stand-by current than in the absence of the diode. In the article by A. Hotter et al "A high-speed low power 4096 x 1-Bit bipolar RAM" published Oll the I~FE International Solid State Circuits Conference 1978, ; Digest of Technical Papers, ~.98/~9, it is stated that a 25 ratio read current/stand-by current of approximately 10 can be obtained by using such a load element. It is moreover stated in this article that, by connecting a pnp transistor across the load element, a further reduction o~ the stand~
by current (4 /uA) and hence of the dissipation can be ob-30 tained while maintaining the short access time~ as a result of which it is possible _ter aLia to considerably increase the number of memory cells in a semiconduc-tor body without detrimental reslllts of a corresponding irlcL~ase of the dissipation.
Due to the ai)ove-me3ltioned stabi:Lity condition~
the ratio read current/stal~d-by curreIlt in these cell alsG
cannot be c~osen arbitrarily large.
A further disadvantage o~ resista3lce elements is ~lS2646 that they occupy comparatively much space in the semicond1c-tor body and that the more so according as the resistance value is higher. Reduction of the resistance elements is often difficult in connection with the electrical properties of other circuit elements or it makes the process of manu-facturing the memory device extra complicated. United Stated Patent Specification 3,585,412 describes a flip~lop circuit using as load elements Schottky diodes connected in the reverse direction which behave as resistors but occupy little space as compared with usual resistance elements.
However, these diodes show the above-described disadvantages of linear resistance elements. Moreover, as a result of the provision of a Schottky diode with the desired reverse voltage characteristic, the manufacturing process of the device generally becomes considerably more complicated.
It is an object of the invention to provide a memory cell of the kind described in the opening paragraph in which the ratio read current~stand-by current rnay be larger than in known cells of this type.
A further object of the invention is to provide a memory cell which has a compact construction and can be manufactured simultaneously by means of the usual process steps.
The invention is based inter alia on the reCOgnitio of the fact that a large ratio read current/stand-by current can be obtained when per brancll of the memory cell the voltage amplification dVce , at least within the current dvbe -voltage range in ~hich it should be possible to operate the device, is entirely or at least substantially entirely independent of` the value of the electrical current. The in-vention is furthermore based inter alia Oll the recogni1;ion ol the f`act that such a currellt-independent voltage am-plification can be obtained by using a rectif`ying junction as a load element the current-voltage characteristic oI
which :in the for~ard direction comprises a ~actor exp.
(~V/rl~T)~ where m 1.
~ memory cell according to the invention is ~15Z646 characterized in that the load element comprises a p-n diode of which at least one of the anode and cathode re-gions is of polycrystalline silicon and in which the col-lector regions of the transistors are conductively con-nected to those regiolls of the diodes which are of the sameconductivity type as the collector regions.
Experiments have demonstrated that p-n diodes consisting entirely or partly of polycrystalline material comprise an exponential factor qV/mkT in their forward character~stic, where m is larger than 1.
This quantity m is a non-ideality factor which re-presents the deviation of this type of diodes with res-; pect to usual monocrystalline diodes. Probably as a result Or intor alia the short life of minority charge carrier.s, m (which in monocrystalline diodes can be assumed to besubstantially equal to 1) is larger than 1 and can be varied around m = ~ within a certain range by the way of manufacture. It can be found out in a simple manner that when such a diode is used as a load element~ the voltage a~plification dVce is substantially equal to m and hence dV
be is substantially independent of the current. Since the range within which this applies extends over a large num-ber of decades, a very low value may be chosen for the stand-by c~rrent while nevertheless the stability condition is satisfied. As a result of this the dissipation in the cell can be maintained very small.
Since resistors are not necessary, the dimensicns of each cell can be made very small so that the cell is particularly suitable for being integrated in a memory in large numbers. Moreover, as will become apparcnt from the description of the figures, the diodes can be manufac~
tured by means of process steps ~Jhich are conventionally used in semiGonductor technology.
For the voltage difference ~ V between t]le col~
lectors~of the transistors it ho]ds in the stabl~ state to an approximation that ~ V -- q ll~ ~ (at least in the usual case in ~rhicl ~ ~ 10 and rn ~ 1.5), where ~ is the ~52646 current amplification of the transistors. The factor m of the diod0s should be so large that ~ V is sufficiently large to maintain the stability o the cell with a given value of possible disturbances. In a fa~ourable embodiment, therefore, diodes are used as load elements in which a voltage difference between the collectors of the transis-tors of at least 150 mV and preferably between 200 mV and 400 mV exists. Large voltage differences of, for example, 500 to 600 mV are preferably avoided because in this case the conductive transistor is saturated (bottomed) so that, as a result of charge storage, the write velocity of the cell is reduced. Very favourable results have been obtained in a construction with diodes in which ~ V was approximate-ly 250 mV. In usual transistors in which the current ampli-fication factor ~ is between approximately 10 an~ 100,diodes are used with an m-factor which is approximately equal to 2. Diodes in which m is smaller than 1,5 are pre-.~! ferably avoided because the voltage difference between the collectors and hence the difference in logic levels n between the two stable states then becomes too small in many cases.
In an important embodiment the diodes on either sideof the p-n junction consist of polycrystalline silicon material. As will become apparent from the description Of the figures, the diodes can be manufactured simul-taneously with the provision of active zones in the mono-crystalline semicond~ctor body via a previously grown polycrystalline silicon layer of a conduccivity type which is opposite to that of the said active ~ones. In another embodiment which can be manufactured substantially entirely by means of standard methods, only one of the anode and cathode regions of the diodes is formed by polycrystalline silicon material, while the other region is formed at least substantially by a monocrystalline part of the semiconductor body which has a higher doping conccntration~ for e~ample 10 times higher, than the polycrystalline part of the diodc.
Thc properties of these diodes do not differ much from those of polycrystalline diodes since the greater part of the ~L152646 .
injected charge carriers is injected, by the monocrystalline part of the diode, into the polycrystalline part where the recombination rate is comparatively high as a result of the concentration difference in doping. Advantageously the recombination rate can be increased by providing a metal layer above the ~-n junction.
A first important embodiment of a memory cell in accordance with the invention is characterized in that the transistors comprise two emitter regions which are co~lected to a supply line and two emitter regions which are con-nected to read/write lines and in which the collector regions are connected together via the said p-n junctions.
This cell which inter alia has the advantage that the way of operation is very simple, in principle needs 4 lines, namely two supply lines or word lines and two read/write lines.
A second important embodiment of a memory cell in accordance with the invention which, as compared with the above-mentioned construction, is operated in a slightly more complicated manner but which has the advantage that in principle only three lines per cell are required, is characteri~ed in that the transistors each comprise only one emitter region which is connected to the emitter region of the other transistor and the collector regions are connected to separate read/write lines via the said ~-n diodes serving as load elements. A semiconductor memory comprising a semiconductor body having a surface-adjacent matrix of such memory cells arranged in rows and columns is characterized in that the surface has a system of crossing conductor tracl~s which form the said read/write lines and which are connected to p-n junctions in the rows ~nd columns, respectively, o~ memory cells.
A particularly compact integration due to the ~act that the emitter regions per cell are common, can be ob-tained iIl a preferred embodiment which is charactcri~edin that tlle trans:istors are formed by inverted transistors in which7 viewed on the sur~ace, the baHe region is situated below the collector region and the emitter region is ~52646 16~ 197g -7- PHN 9314 situated below the base region of each transistor, and in which the semiconductor body comprises a number of juxta-posed, mutually separated strip-shaped regions of the first conductivity type which extend parallel to the rows or columns in the semiconductor body and form common emitter regions of the transistors belonging to the same row or column. A further favourable embodiment which presents impor-tant advantages both because the transistors themselves may be very small and because the ~-n junctions do not require any extra process steps, is characterized in that the surface of the semiconductor body has an insulating layer which, at the area of the transistors, shows windows wllich define the base regions of the transistors and which are closed by a layer of polycrystalline silicon deposited in the windows and on the insulatlng layer and showing the same conductivity -type as the base regions, the collector regions being situated below parts of the polycrystalline silicon layer of which the conductivity type has been changed b~-doping, said parts extending over the insulating layer and 20. forming there the sa.id p-n junctions with parts the con-ductivity type of which has not been changed by doping.
The invention will now be described i.n greater detail.
with reference to a few embod:iments and the accompanyil~g drawing, in which Fig. 1 is a circuit diagram of a known flip-flop memor~7 cell;
Fig. 2 is a circuit diagram of a lip-flop-memory cell according to the invent:ion;
Fig. 3 is a plan view of a part of a memor~r cell according to the invention;
Fig. 4 is a cross-sectional vi.ew of tlle levice shown in Fig. 3 talen on t~e line I~J I~';
Fig. ~ is a plan view of a part of another cmbodime]lt;
of a memory matrix according to thc invention;
Fig. 6 is a sectional v:iew o:t this dc~i.ce ta~e on th~ line VI-~7~;
Fig~ 7 is an clcctric diaglan1 of a part of a memory ~ccordirlg to anothcr embodimerlt of t;hc inven1:ion;
Fig. 8 is a plan view of a part of a memory according to the diagram of Fig. 7;
which is on the same sheet as Fig. 7, Fig. 9,/is a sectional view taken on the lines IX-IX
of Fig. 8; which is on the same sheet as Fig. 7 Fig. 10Jis a sectional view taken on the line X-X
of Fig. 8;
Figs. 11 to 13 are sectional views of a transistor used in the memory shown in Fig. 8 during a few stages of the manufacture thereof;
Fig. 14 is a plan view of a further embodiment of a memory cell in accordance with the invention;
It is to be noted that the figures are diagrammatic and are not drawn~; to scale.
Fig. 1 shows the circuit diagram of a static memory cell of a known type having t~o transistors T1 and T2 the base and collector regions 1 and 2, respectively, of which S are interconnected crosswise. The collectors 2 are connected, via load elements 3, to a supply line 4 which in the case o~
a memory is used as a word line. The transistors each com-; 20 prise two emitter regions 5 and 6, the emitter regions 5 ; being connected to the (word) line 7 and the emitter regions 6 being connected to the write/read lines 8 and 9. In the most conventional known constructions the load elements 3 simply consist of resistors.
During~ operation, a comparatively large current i is passed through the cell for reading in connection with a desired reading velocity, and a emaller current is passed in the stand-b~ condition to restrict the dissipation. These different current values lead to different desired vallaes for the impedances 3~ as will become apparent hereinafter.
The starting requirement is that in the metastable point per branch it should hold for a stable flip-~lop circuit for the gain factor dV d~J
d~ l~e dVb ( 1 ) where ~ Vc and ~ Vb are voltage variations at 1;he collector and the base regions, respectivel-y. For t;he emittcr-base junctio1l of the transistors T1, T2 the diode equation ~S2646 (kT ) (2) holds to an approximation, wherein ic is the collector cur-rent, q the elementary quantity of charge, Vbe is the for-ward voltage across the emitter-base junction, 1 is Boltzmann's constant and T is the absolute temperature.
From equation (2) it can be derived that with a voltage variation . Vbe for the current variation i it holds that:
~ic = kT ~ Vbe : 10 For the case in which the elements 3 simply consist of resistors having resistance values R, it follows from equations (1) and (3) that:
R ~ kT (4) The minimum value of R hence depends on the current and 5 that in that sense that with a large current a small re-sistance will suffice, whereas with a small i the resis-. tance R should be large.
Since furthermore in practice the voltage differencebetween the collectors of the transistors usually is pre-20 ferably at least 100 to 150 mV, the ratio between the readcurrent and the stand-by current will usualLy be only low (srnaller t~Lan 10).
It is known that the dissipation can be reduced, as already described in the preamble, by uslng a non-linear 25 resistance eleD1ent which can be obtained, f'or e~:ample, by connecting a diode parallel across the resis-tor as is shown in Fig. 1 irL broken lines. With such a non-linear resis-tance element in which the di.fferential resistanc~ decreases when the value of the current increases, a considerable improve~ent 30 in the ratio read current~stand-by current CaJl be effected.
However, a f'urther increase of the read curre~t/stalld-by current would often be desired..
~ rom thc point of vi ew c-~ packing density, further resistance elemen-ts having large resi.stance values are 35 undesired d1le to the comparati.vely l.arge space thcy use to occupy- in tl1.e semicon.ductor bocly.
Fig ~ shows a circuit diagraln of a fli.~ `lop oell accordin~ to t'he inven';:i.onc Insl;oad of res:i.stors 3 the ce:Ll ~526~6 - 10 - PHN. 9314 comprises load elements consisting mainly of diodes 11 the cathodes of which are connected to collector regions 2 of the transistors Tl and T2 and the anodes are connected to the word line 4 so that during operation the diodes are forward-biassed. In order to obtain a sufficiently large impedance which, on the basis of the stability condition imposed in equation (1), should be larger than that of the emitter-base junction, at least one of the anode and cathode regions of the diodes 11 is made of polycrystalline silicon.
This type of diodes shows a current-voltage characteristic which (within a certain range) can be described by id = Io exp ~ (5), where _ > 1. It can be found out in a simple manner that in this case it holds for the amplification from equation (1) that ~ Vce = m Within the current-voltage range wherein the diode equation (5) applies, the voltage gain a Vce is substantially ~ Vbe independent of the current and is larger than 1, so that the stability condition at the metastable point the loop gain should be larger than 1 is satisfied. Because the range within which this applies generally is very large (5 to 6 decades), the current can be varied over a large range, which means that the read current can be very large (1 mA) and the stand-by current very small and can even be selected to be in the order of magnitude of 1 mA while the cell nevertheless remains stable.
When a current 1 is passed through the conductive transistor and the current gain ~ of the transistors shows a usual value (for example at least 20), a current of substantially i/~3 which forms the base current for the conductive transistor flows through the diode 11 which is connected to the non-conductive transistor. It can be derived from equation (5) that the voltage difference ~ V
between the collector regions 2 of the transistors is equal to mkT in ~ , and hence (at least in 1 order) q `i~ ~b4b is substantially not dependent on the current. The ~oltage differellce a v should be so large that with a given value o~ noise the cell nevertheless remains stable. With a given value of the current gain factor ~ , therefore, diodes 11 are used having such a factor m that ~ V is at least approximately 150 mV and preferably at least approximately 200 mV. An upper limit of preferred values of the quantity m is determined inter alia by the velocity of the memory cell. The conductive transistor which is saturated can be-come bottomed at a large voltage difference, for example,a voltage difference of 500 to 600 mV~ so that the writing velocity is reduced. Therefore, the rn-factor of the diodes 11 preferably has at most such a value that, at a given value of ~ , the voltage difference ~ V between the col-lector regions 2 is at most 500 mV. ~a~rourable resultshave been obtained in practical constructions with diodes having an m-~actor of at least 1.3 and approximately equal to 2 in transistors having a ~ in the order of magnitude between 30 and 100, so that a voltage difference ~ V was 20 built up of approximately 150 to 250 mV.
Figs. 3 and 4 are a plan view and a sectional view, respectively, of a part of a practical embodiment o~ a memory in accordance with the inve~tion. The device com-prises a semiconductor body 12 o~ a conventional construct-ion consisting o* a ~ type substrate 13 and an n-type epitaxial layer 14 adjoining the upper surface 15. A number of islands 16 are formed in the epitaxial layer and are arranged in groups of two which comprise the transistors of a memory cell. Within the epitaxial layer the islands 16 are bounded by insulation regions 17 ~hich in th-s case are formed by p~type zones prov-ided in the la~-er 14 but which, O:r course, may also consist of insul~ting material~ for example, silicon oxideS sunl~ in the semi-conductor body and obtained b~ Local oxidation of the epitaxial layer 14. T~le islands 1~ themselves constitute with the highly doped buried n-type 3ayers 18 a-t the inter~ace between the epi*ax-ial la~er and the substrate and ~ith the hi~hly doped n-type collector contact zone 1~ t-he collcctor rcgiolls o-` lhe ~;2646 t6~10-197~ ~12- PHN 9314 transistors. In the usual manner the base regions in the form of tle ~-type surface zones 20 and the emitter regions in the forn1 of the n~type surface zones 21 and 22 are provid~
ed in the isl~lds 16 by means of diffusion or ion implan-tation. The surface 15 is covered with an insulating layer23 having windows to provide contacts with the emitter base and collector regions of transistors.
It is to be noted that the transistors in Fig. 3 are shown only very diagrammatically. For example, the 10 buried layers 18 are not shown and the contours of the emit-ter regions 21 and 22 and the collector contact zones 20 which coincide substantially with the ContDUrS of the con-tacts between said regions and the ~ord lines and the read~
write lines are not shown either.
A pattern of conductor tracks 24 of p-type poly-crystalline silicon is formed on the oxide layer 23, which tracks change into collector connections 26 of n-type poly-crystalline silicon via the ~-n junctions 25 forming the load elements of the flip-flop, as described with reference 20 to Fig. 2. The tracks 24 form one of the word lines of the memory corresponding to the lines 4 in Fig. 2. The word lines corresponding to the lines 7 in ~ig. 2 are formed by the conductor trachs 27 which are connected to the emit-ter regions 22 and, as the collector connection 26, may be 25 constructed from n-type polycrystalline s:ilicon. The e~litter regions 22 are connected to read/write lines 28, 29 extend-ing in the column direction. These lines may be constructed in a second layer of wiring, for exatnple of Al, which is insulated electrically from the lines 24, 27 by an inter-30 mediate oxide layer~ The crossing connections 30 betweenthe base reg:ions 20 and the collector regions 16 oI the transistors may also be malluI`actured in this layer of ~iring, The polycrystalline si]icon material of the word 35 lines 24 and 27 is formed in known manncr by decomposition of SiM4 at low pres~ure (appro~imate7y 0.~ mm Ilgj at a temperature of approximately 61~o C. l`he g~rowth rate was appro~imately 100 ~/mill~ In these circums-taIIces~ polycrys-.... .. .
~5Z646 16-10~1979 _13_ PHN 9314 talline silicon material was obtained the factor m of ~hich was approximately equal to 2. Ho~ever, the process condi-tions may be varied such that the polycrystalline materiaJ
differs more or less from monocrystalline silicon, for example, by changing the growth rate so that the ~rain size and the concentration of trapping centres and hence also the m factor changes. In general it may be said that the various process parameters can simply be chosen by those skilled in the art in such manner that diodes having pro-perties which are most favourable for a given application areobtained.
Figs. 5 and 6 are a plan view and a sectional view, respectively, of a modified embodiment of the above-described memory matrix. Only one memory cell of the ~latri~
1~ is shown in these figures but it will be obvious that a memory ~atrix of memory cells as shown in Fig. 5 can be ob-tained in the same manner as in t;he preceding embodiment.
Furthermore, in the~e figures the same reference numeral3 are used for correspo~ding components as in the preceding embodimcnt.
In contrast with the preceding embodiment, only one of the anode and cathode regions is of polycrystalli~e silicon, while the other region i~ formed at least sub~
stantially by a monocrystalline part of the semiconductor-25 body. For this purpose9 the polycrystalline word lines 24are situated immediately above the collector regions 16 and, at the area of windows in the o~ide layer 23, adjoin the collector regions 16 of the transistors, The poly-crystalline paths 24 which ,as in the precedin~ embodiment, are of the ~-condllctivity type9 f`orm the ~n junctions 31 wit;h the collector regions 16 substantially at the area of the interface bet~een the polycrystalline ~nd the mono--crystalline rn~terial~ These p-n junckions~ e the ~n diodes 11 in the precedin~ embodilrlent5 for~n the load elcmentc ; 35 of t;he memory elements. In ordcr to obtain a suita1~lc gain, for this purpose the doping concelltrLltion on the mono-crystalline cathode side of the dio~e is chosen to ~c hi~hcr~
prefc-~ral~1y at least 10 ~ bigher, tilall 011 thc polycrystal~-inc :~52646 anode side. At least for the purpose for which they are used here, the characteristics of such diodes prove to have substantially the same propcrties as diodes containing both an anode and a cathode pf polycrystalline silicon. An explanation for this is that at the given concentration difference between the anode and the cathode, the greater part (for example 90%) of the current across the diode is formed by charge carriers (electrons) which are injected into the polycrystalline paths 24 from th.e collector 16 and, in particu.lar as a result of the recombination centres present there to a comparatively large extent, disappear again by recombination. The desired concentration difference can be obtained in a very simple manner by providing, at the area of the ~-n diodes 31, a highly doped low-ohmic collector contact zone 19 which is usual in conventional circuits and has a doping concentration of 10 - 10 1 atoms/cm3 and choosing the doping concentration of the po-lycrystallin.e paths 24 to b~ between approximately 10and 1019.
Since the word lines 24 are situated immediately above the collector contact windows in the oxide layer, the dimensions of the cell can be particularly small.
In those cases in which it is important for the resistance in the word lines to be kept low, a laycr of a 25 readily conductive material, for example alumini.u~, may be provided on the polycrystalline paths 24. However, the word lines may also be substantially entirely of aluminium a~ld also comprise only locally strips of polycrystalline silicon in which -the ~-n junction is formed. Fig. 14 is a 30 diagrammatic plan view of such a modified embodiment. The word lines are shown diagrammatically by a line WL and are fo~ed by tracks of Al extending Prom the left to the right above the semiconductor body. The p-n diodes 25 are formed in strips 24, 26 oP polycrystalline silicon extendi.ng only 35 het~een the collector contacts 190 Thcse strips compr:~se a ~-typc portion 2~ which is co~ acted wi-th tne Al stri~
WL, and an n-type porcion 26 which is connected to the collector con.tac-t æone 19 and is insulated from the ~ord ~52646 line WL by an insulating layer of, for example, silicon oxide.
In the memory device described so far~ each cell comprises at least four address lines, namely two bit/read lines and two word lines which also ensure the supply of the cell. The following embodiment relates to a memory in which the supply of the memory cells is provided at least partly by one of the bit lines so that only th~ee lines per cell will suff`ice instead of four and hence a further reduction of the space which the memory occupies in the semicon~uctor body can be obtained.
Known memory cells of this type having only three address lines are described inter alia in the article "A four device bepilar memory cell" by Raymond Ao Heald, published :in IEEE International Solid State Circuits Conference, 1978, pp 102-103. These kno~in memory cells comprise as load elements in the collector tracks of the cross-coupled inverter transistors complemelltary transis-tors which are of the ~ t~pe, so transistors of the 20 pnp-type.
.
According to the invention, poly-poly ~-n diodes or poly-mono p-n diodes are used as load elements the ~orward characteristic of which comprises a factor exp (qV/mkT) wheren1 is larger than 1, so tha-t again a particularly simple and compact configuration can be obtained.
Fi~. 7 shows a circuit diagram of a part of a mat;rix configuratioll. The trans:istor~s T1 T8 each comprise only one single emit-ter since the supply lines also fulfil at least partly the function of` bit lines. The supply line XL1 X I2 etc. connects the esnitters of the cells of` a word to a current; source 40, 41. The word lines ~ I con-nect ~he anodes of the diode~ D1, D3, D~, D7 ~o vo~tage sources V~ , V , etc. The lire5 Y .~ g Y2 etc. connect in the same manner the cells column-~wise to the ~oltage sources Vy , Vy etc. The Y lines are Inoreover connectcd to read means 2 42s 43~ which f`or simplicity are shown as ammeters .
The device may be operated~ f`or cxc~mple~ as Iol30ws:
1~52646 16-10-197~ -16- PHN 9314 Stand-by: In the quiescent state the voltages Vx and Vy are assumed to be equal. The cells are in one of the two stable states. For example, when the cell with the transistors T1 and T2 and the diodes D1 and D2 is chosen as an example, much or little current passes through the diode D1, dependent on that position, namely a base cur-rent (to T2) or a collector current (to T1).
Writin~: Assuming the cell to be in that condition in which the transistor T1 conveys curr~nt, the cell may be set in a different state by increasing Vx and simultaneou~s-ly reducing Vy , so that the collector current through T
is increased and the base current to T1 is reduced, res-pectively. With a given voltage variation the base current to T1 becomes so small that the transistor T1 is cut off for lack of sufficient amplification. The transistor T2 will become conductive. For the right-hand neighbouring cell (T3~ T4) only Vx is increased and for the neighbourin~
cell (T57 T6) only Vy is increased. With a suitable choice of the voltage variatlon this half selection is insufficient to switch said cells. It is not necessary to increase the currents IX ~ IX ~ etc. during writing, but the velocity of writing can be increased by it.
Readin~ Because uporl reading a given cell the other cells in the same colurnn also provide a contribution to the overall current through the Y lines~ it is advantageous to give th0 selected row much more current than the other rows, by means o:~ the current sources 40, 41 etc. The informatio may ther be read by finding out via the means 42 whether a comparatively low base current flows through the relevant Y
line or a high collector current. This differerlce may be extra emphasized by mak:ing Vx h-igher than ~y.
In prir.ciple a whole row is read simultaneously but it may be ensured by means of a post-selection that the infol-mation of only o~e cell ema~ates.
Th~ ~oltage dif~erence ~ V wllich is to be arJplied betweeIl the associated ~L and y lirJes for writing infor-m~tion in a givelL cell ~ill dep-nd both on the factor ln and on ~ D the t~hle be10~Y 9 for various ~alucs of f~
` 1152646 16-10-197~ -17- PHN 9314 and m = 2, the associated values of ~ V are recorded obtained from computer simulations.
~ ~V (mV) These values prove substantially to satisfy the 10 general equation:
av = q ln ~ - 2 q ln 2~
to be determined analytically.
For a specific value of ~ of approximately 30, this voltage is approximately 52 mV. For writing, in which each 15 time the condition of one single cell may be flipped over, a voltage ~ a v is applied to the x and ~ line. 40 mV may be chosen, for example, for this ~ V. Writing may therefore b~ carried out as follows.
Write "1" Vx1 = +4 m~, VY1 = -40 mV - ~ T2 conducts 20 Write "0" Vx1 ~ o mV, VY1 = ~40 mV - ~ T1 conducts.
~ ig~ 8 and Figs. 9 and 10 are a plan view and sectional views, respectively, of a part of a semiconductor device having a matrix of the above-described memory cells.
The device comprises a semiconductor body 45 of the usual 25 composition having a substrate 46 of ~-type silicon and a layer 47 of n-type silicon deposited thereon. ~ n~mbcr of islands 49 separated from each other by p-type zones 48 are formed in said epitaxial layer and, in the plan ~iew shown in ~ig. 8, extend from the left to the right. Highly doped 3~ buried n-type zones 50 corresponding to the address lines XL1, XL2 etc., of the transistors of the memory cells, to be operated inversely, are provided between the islands 49 and the substrate 46. I`he ~-type ~ones 51 are provided in the n~typc- islands and forrn the base zones of the transis-35 tors T1, T27 T3 etc.~ and the n-type surface zo-nes 52 are provided in the ~-type zones 51 and form the collectors of the transistors. It is to be noted that -the transistors of the memory cells associaled with a conln1o}l word line ~L
~52646 16_10-1979 -1~- PHN 9314 are provided in a common island due to the~act that the transistors are used inversely, the lowermost n-type region 50 serving as emitter and the uppermost n-type region 52 serving as collector region. In addition to im-portant other advantages, said inversion permits a par-ticularly compact structure of the memory matrix since, unlike in the preceding embodiments, all transistors are provided in a separate island. As shown in the sectional views of ~igs. 9 ar,d 10, highly doped n-type zones 70 are furthermore provided in the islands 49 and surround the base zones 51 and, by way of example, extend from the surface down to the buried zones 50. In known mamler the current gain of t~e inverse transistors can be improved by mea~s of said zones, while in addition parasitic lateral action between the base regions can be avoided.
The buried zones (50, XL) can be contacted in known manner at the edge of the islands 49 beyond the part of the semiconductor device shown in the figures, ~,hich is shown diagrammatically in Fig. 8 by thc connection wires 53.
-2G Apart from the contacts 53 ~or the emitter regions 50, the transistors T1, T2, T3, etc., ol1ly comprise a window in the oxide layer 5~ which covers the epitaxial layer 47.
Via this aperture, re~erenced 55 in Fi~. $, both the ~ase zones 51 and the collector zones 52 are provided with an 25 electric connection~ These co~mections are denoted by reference numerals 56 and 57, respectively, and are formed by layers o~ p~type and n-type silicon, respectively, deposited in the windows 55 and on the oxide layer 54. The way in which this type o~ transistor can be marlufactured 30 will be described hereinafter.
The collector colmections 57 change into p type siiiCon paths 59 via the p-n junctions 58. The n-type silicon connections 57s at least in ;o rar as they are not situated in the windows 55 in the o~icle layer 54 im-35 mecliately abo~-e the coJlector rc~ions 57~ and the ~-t~lpe silicon paths 59 are again o~ a polycrystalline structure .50 that the p-n junctiQ~s 58 wllich correspond to the diodes D in the circuil dia~ram o~ . 7, S~10~ a characteristic ~lSZ646 -19- PHN. 9314 which makes them suitable to serve simply as collector load elements.
The polycrystalline paths 57, 59 are covered with an insulating layer 60 obtained by deposition from the gaseous phase or by partial oxidation of polycrystalline silicon material. Conductor tracks 61 are provided on the oxide layer 60 and extend in the column direction of the matrix and are connected, ~ia windows 62, to the ~-type silicon tracks 59 of one of the diodes in each cell. The paths 61 which correspond to the Y-lines in the circuit diagram shown in Fig. 7 and which are shown diagrammatically only in the plan view, may be, for example, of Al. In the same manner, the p-type paths 59 which as anodes are associated with the other diodes in the cells are connected by Al paths 63 extending in the row direction transversely to the column direction of the matrix. These paths which correspond to the X lines in Fig. 7 and which are shown diagrammatically only in Fig. 8, cross the Y lines 61 and may be electrically insulated herefrom by an intermediate layer 64 of, for example, silicon oxide or aluminium oxide or any other sutiable dielectric.
In Fig. 8 the contacts between the XL lines and the ~-type polycrystalline silicon material 59 are denoted by dots.
The polycrystalline silicon may also be used to form the crossing connections between the collector and base regions of the two transistors in a cell. Because the poly-crystalline silicon above the collector region of one transistor is n-type and the`silicon 56 above the base region of the other transistor is p-type so that, in the case in which these two polycrystalline layers 56, 57 adjoin each other (see Fig. 13) and form a parasitic ~-n junction 65, a metal connection 66, for example of Al, is provided on the polycrystalline silicon and interconnects these two parts 56, 57 of different conductivity types and, in the present embodiment, shortcircuits the parasitic p-n junction 65.
For the manufacture of the semiconductor structure, /
.~
- 20 - PHN. 9314 generally known techniques may be used substantially en-tirely which need not be further described here. For the manufacture of the transistors, reference is made in par-ticular to Applicants' Canadian Patent 1,093,702 -January 13, 1981 (PHN 8601) the contents of which is incor-porated in this application by reference. Figs. 11-13 show a few stages of the manufacture of such a transistor. Fig.
11 is a sectional view of a part of the semiconductor body in which the transistor is to be provided after the n-type epitaxial layer 47 has been provided on the ~-type substrate 46 with the buried n-type layer 50 between the substrate and the layer 47 and the island insulation not shown in the drawing. The aperture 55 is formed in the oxide layer 54 on the surface of the semiconductor body by means of known photo-lithographic methods. The aperture 55 which defines the base zone of the transistor is then closed again by means of the layer 67 of silicon which on the surface of the epi-taxial layer 47 shows a monocrystalline or polycrystalline structure and on the oxide layer 54 shows a polycrystalline structure. Paths or tracks which correspond to the poly-crystalline conductor pattern 56, 57 shown in the plan view of Fig. 8 may be formed from the silicon layer 67. The remaining parts of the silicon layer may be removed by etch-ins or be converted into silicon oxide by oxidation.
The remaining silicon layer 67 may then be doped with a ~-type impurity, for example boron, by means of diffusion or by ion implantation methods. At the area of the aper-tures 55 in the oxide layer 54 the boron also penetrates into the epitaxial layer 47 and forms there the ~-type base zone 51 (Fig. 12). The silicon layer 67 is then partly covered with a masking layer 68 which extends partly in the aperture 55 and further above those parts of the layer 67 which are to form the p-type polycrystalline paths 59.
The exposed part of the poLycrystalline layer 67 is then doped with an n-type impurity for example phosphorus, by means of implantation. At the area of the aperture 55 in the oxide layer the impurity diffuses in the semiconductor body and forms there the _-type collector zone 52, Fig. 13.
~lSZ646 The p-n junction 69 between the base zone 51 and the collcctor ~2 e~tends into the layer 67 and divides said layer into an n-type portion 57 and a p-type portion 56 forming a collector connection and a base connection, respectively. Simultaneously with the p-n j~nction 69 the p-n junctions ~8 serving as load elements are formed between the n-type collector comlections 57 and the p-type strips By deposition from the gaseous phase or by oxidation of the polycrystalline silicon strips, the oxide layer 60 may then be provided after which the Al paths XL and Y may be formed in the usual manner.
It will be ob~ious that the invention is not restrict-ed to the embodiments described but that many variations are possible to those skilled in the art without departing ~rom the scope of this invention.
For example~ the conductivity types of the va~ious zones and regions may be reversed, pn~-transistors being used instead of n7~n-transistors.
In order to obtain a higher packing density all the emitter regions in the last example could be connected to one common current source~ Not muc~ changes for writing.
Upon reading, however, the overall interference contribution is mucll larger than the signal. In order nevertlleless to be 25 ab:Le to read, a dynamic read amplifier may be used. The operation then becomes as follows: If` all the ~ lines are kept constant~ the interference contribution is unknown but is constant. By increasing vx1 by a certain voltage, too small to change the condition of the connected cells, a ~ current increase in ~ will be vis:il~le, if T2 conducts ("1") and no current change if T1 conducts ("1")- So the readin~
amplil`ier should be sensitive to small variations super-impo~ed on an -unknown - large direct current.
Reading of the cells in the rirst embodiment may also ,~.
be done in known manncr via a dioae col1necte~l to the collector of` the trarlsistc,rs.
Claims (20)
1. A memory cell destined in particular to be integrated in a static memory in large numbers, comprising a semiconductor body having two transistors with cross-coupled base and collector regions, the collector regions being connected to a load element comprising a diode, characterized in that the load element comprises a p-n diode of which at least one of the anode and cathode regions is of polycrystalline silicon and in which the collector regions of the transistors are conductively con-nected to those regions of the diodes which are of the same conductivity type as the collector regions.
2. A memory cell as claimed in Claim 1, charac-terized in that the current-voltage characteristic of the diodes comprises an exponential term (), where q is the elementary quantity of charge, V is the voltage, k is Boltzmann's constant and T is the absolute temperature, and in which m is such that at room temperature during operation a voltage difference of at least 150 mV is present between the collectors.
3. A memory cell as claimed in Claim 2, charac-terized in that diodes are used in which the voltage differ-ence between the collectors is between 150 and 500 mV.
4. A memory cell as claimed in Claim 2 or 3, char-acterized in that m is at least approximately 1.3.
5. A memory cell as claimed in Claim 2, charac-terized in that the quantity m is at least approximately 1.5 and preferably at least approximately 2.
6. A memory cell as claimed in Claim 1, 2 or 3, characterized in that the diodes on either side of the p-n junction consist of polycrystalline silicon material.
7. A memory cell as claimed in Claim 1, charac-terized in that only one of the anode and cathode regions is of polycrystalline silicon material by a monocrystalline part of the semiconductor body, the doping concentration in PHN. 9314 the said other monocrystalline region of the diode being higher than the doping concentration in the polycrystalline region of the diode.
8. A memory cell as claimed in Claim 7, charac-terized in that the doping concentration in the monocrystal-line region of the diode is at least approximately 10 x higher than in the polycrystalline region.
9. A memory cell as claimed in Claim 1, charac-terized in that the collectors of the transistors are con-nected to a first supply line via the diodes serving as load elements and the emitter regions are connected to a second supply line.
10. A memory cell as claimed in Claim 9, charac-terized in that the transistors each comprise a second emitter region which is connected to a read/write line.
11. A semiconductor device comprising a matrix system of memory cells as claimed in Claim 9, characterized in that the semiconductor body for each memory cell com-prises two juxtaposed mutually insulated surface-adjoining island-shaped regions of one conductivity type which are bounded on their lower side by a substrate of the second conductivity type, the island-shaped regions, which each form a collector region of a transistor, having a surface zone of the second conductivity type which forms the base region of the associated transistor and is provided again with at least a surface zone of one conductivity type which forms the said emitter region of the transistor, the sur-face of the semiconductor body being covered with an insu-lating layer having a track of polycrystalline silicon of the second conductivity type which via the said p-n junc-tions and via windows in the insulating layer, is connected to the collector regions of the transistors.
12. A semiconductor device as claimed in Claim 11, characterized in that the track of polycrystalline silicon is situated above the contact windows of the collector regions and with the collector regions forms a junction between polycrystalline and monocrystalline silicon material substantially coinciding with the said p-n junctions.
13. A semiconductor device as claimed in Claim 12, PHN. 9314.
characterized in that at the area of the contact windows the collector regions have a highly doped surface zone of one conductivity type which has a higher doping concentra-tion than the part of the collector regions surrounding said zone.
characterized in that at the area of the contact windows the collector regions have a highly doped surface zone of one conductivity type which has a higher doping concentra-tion than the part of the collector regions surrounding said zone.
14. A semiconductor device as claimed in Claim 12 or 13, characterized in that metal tracks are provided on the polycrystalline silicon at least above the contact windows of the collector regions.
15. A semiconductor device as claimed in Claim 11, characterized in that at the area of the contact windows in the insulating layer the collector regions of the transis-tors are conductively connected to parts of the track of polycrystalline silicon of one conductivity type which, via the said p-n junctions, change into portions of the second conductivity type situated beside the contact windows.
16. A memory cell as claimed in Claim 1, charac-terized in that each transistor comprises only an emitter region which is connected to the emitter region of the other transistor and the collector regions are connected to separate read/write lines via the said p-n diodes serving as load elements.
17. A semiconductor device comprising a semiconductor body having a surface-adjoining matrix of memory cells arranged in rows and columns as claimed in Claim 16, characterized in that the surface has a system of crossing conductor tracks forming the said read/write lines which are connected to p-n junctions in the rows and columns, respectively, of memory cells.
18. A semiconductor device as claimed in Claim 17, characterized in that the transistors are formed by inverted transistors in which, viewed on the surface, the base region is situated below the collector region and the emitter region is situated below the base region of each transistor, the semiconductor body having a number of juxtaposed mutually separated strip-shaped regions of the first conduc-tivity type extending parallel to the rows or columns in the semiconductor body and forming a common emitter region of the PHN. 9314.
transistors belonging to the same row or column.
transistors belonging to the same row or column.
19. A semiconductor device as claimed in Claim 17, characterized in that the surface of the semiconductor body has an insulating layer which at the area of the transis-tors comprises windows which define the base regions of the transistors and which are closed by a layer of polycrystal-line silicon which is deposited in the windows and on the insulating layer and is of the same conductivity type as the base regions, the collector regions being situated below parts extending over the insulating layer and the conducti-vity type of which has been changed by doping and forming the said p-n junctions there with a part the conductivity type of which has not been changed by doping.
20. A semiconductor device as claimed in Claim 19, characterized in that the crossing connections between the collector and base regions in each memory cell are also formed by parts of the polycrystalline silicon layer in which p-n junctions are situated which are short-circuited by an overlying metal layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NLAANVRAGE7812463,A NL188721C (en) | 1978-12-22 | 1978-12-22 | SEMICONDUCTOR MEMORY CIRCUIT FOR A STATIC MEMORY. |
| NL7812463 | 1978-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1152646A true CA1152646A (en) | 1983-08-23 |
Family
ID=19832117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000342353A Expired CA1152646A (en) | 1978-12-22 | 1979-12-20 | Memory cell for a static memory and static memory comprising such a cell |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4322821A (en) |
| JP (1) | JPS5840341B2 (en) |
| AU (1) | AU530153B2 (en) |
| CA (1) | CA1152646A (en) |
| DE (1) | DE2950906C2 (en) |
| FR (1) | FR2444992A1 (en) |
| GB (1) | GB2038091B (en) |
| IT (1) | IT1193349B (en) |
| NL (1) | NL188721C (en) |
| SE (1) | SE438569B (en) |
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|---|---|---|---|---|
| US4622575A (en) * | 1981-10-27 | 1986-11-11 | Fairchild Semiconductor Corporation | Integrated circuit bipolar memory cell |
| US4488350A (en) * | 1981-10-27 | 1984-12-18 | Fairchild Camera & Instrument Corp. | Method of making an integrated circuit bipolar memory cell |
| US4543595A (en) * | 1982-05-20 | 1985-09-24 | Fairchild Camera And Instrument Corporation | Bipolar memory cell |
| US4624863A (en) * | 1982-05-20 | 1986-11-25 | Fairchild Semiconductor Corporation | Method of fabricating Schottky diodes and electrical interconnections in semiconductor structures |
| US4551070A (en) * | 1983-12-23 | 1985-11-05 | The Nash Engineering Company | Noise control for conically ported liquid ring pumps |
| US4737836A (en) * | 1983-12-30 | 1988-04-12 | International Business Machines Corporation | VLSI integrated circuit having parallel bonding areas |
| JPS61501061A (en) * | 1984-01-12 | 1986-05-22 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Bipolar static random access memory cell |
| JPH0418798Y2 (en) * | 1985-06-08 | 1992-04-27 | ||
| US5087956A (en) * | 1985-10-25 | 1992-02-11 | Hitachi, Ltd. | Semiconductor memory device |
| JPS6295843U (en) * | 1985-12-03 | 1987-06-18 | ||
| JPS62218022A (en) * | 1986-03-19 | 1987-09-25 | Inoue Japax Res Inc | Electric discharge machine |
| JPS6379373A (en) * | 1986-09-24 | 1988-04-09 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US4864539A (en) * | 1987-01-15 | 1989-09-05 | International Business Machines Corporation | Radiation hardened bipolar static RAM cell |
| US5151387A (en) * | 1990-04-30 | 1992-09-29 | Sgs-Thomson Microelectronics, Inc. | Polycrystalline silicon contact structure |
| DE69324864T2 (en) * | 1992-08-21 | 1999-10-07 | St Microelectronics Inc | A method of manufacturing a vertical type semiconductor memory structure, and the structure of the method |
| JP5269428B2 (en) | 2008-02-01 | 2013-08-21 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| TWI758077B (en) * | 2021-01-21 | 2022-03-11 | 凌北卿 | Non-volatile memory device having pn diode |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1524873B2 (en) * | 1967-10-05 | 1970-12-23 | Ibm Deutschland | Monolithic integrated storage cell with low quiescent power |
| DE1574651C3 (en) * | 1968-03-01 | 1976-01-02 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithically integrated flip-flop memory cell |
| US3585412A (en) * | 1968-08-27 | 1971-06-15 | Bell Telephone Labor Inc | Schottky barrier diodes as impedance elements |
| US3573758A (en) * | 1969-02-27 | 1971-04-06 | Ibm | Non-linear impedance means for transistors connected to each other and to a common power source |
| US3626390A (en) * | 1969-11-13 | 1971-12-07 | Ibm | Minimemory cell with epitaxial layer resistors and diode isolation |
| DE2041507A1 (en) * | 1970-08-21 | 1972-02-24 | Horst Henn | Solid-state memory for binary information |
| US3849675A (en) * | 1973-01-05 | 1974-11-19 | Bell Telephone Labor Inc | Low power flip-flop circuits |
| US3886531A (en) * | 1974-02-11 | 1975-05-27 | Texas Instruments Inc | Schottky loaded emitter coupled memory cell for random access memory |
| JPS53108776A (en) * | 1977-03-04 | 1978-09-21 | Nec Corp | Semiconductor device |
-
1978
- 1978-12-22 NL NLAANVRAGE7812463,A patent/NL188721C/en not_active IP Right Cessation
-
1979
- 1979-09-28 FR FR7924263A patent/FR2444992A1/en active Granted
- 1979-12-18 DE DE2950906A patent/DE2950906C2/en not_active Expired
- 1979-12-19 SE SE7910457A patent/SE438569B/en not_active Application Discontinuation
- 1979-12-19 JP JP54165466A patent/JPS5840341B2/en not_active Expired
- 1979-12-19 IT IT28197/79A patent/IT1193349B/en active
- 1979-12-19 US US06/105,357 patent/US4322821A/en not_active Expired - Lifetime
- 1979-12-19 GB GB7943741A patent/GB2038091B/en not_active Expired
- 1979-12-20 CA CA000342353A patent/CA1152646A/en not_active Expired
- 1979-12-20 AU AU54040/79A patent/AU530153B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| DE2950906C2 (en) | 1986-04-03 |
| US4322821A (en) | 1982-03-30 |
| FR2444992A1 (en) | 1980-07-18 |
| IT7928197A0 (en) | 1979-12-19 |
| SE7910457L (en) | 1980-06-23 |
| JPS5840341B2 (en) | 1983-09-05 |
| GB2038091B (en) | 1983-07-20 |
| IT1193349B (en) | 1988-06-15 |
| AU530153B2 (en) | 1983-07-07 |
| DE2950906A1 (en) | 1980-07-10 |
| GB2038091A (en) | 1980-07-16 |
| NL188721B (en) | 1992-04-01 |
| SE438569B (en) | 1985-04-22 |
| JPS5587385A (en) | 1980-07-02 |
| FR2444992B1 (en) | 1983-11-25 |
| AU5404079A (en) | 1980-06-26 |
| NL7812463A (en) | 1980-06-24 |
| NL188721C (en) | 1992-09-01 |
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