JPH01194461A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a base parasitic resistance and to shorten a writing time by enhancing the impurity concentration of an N-type epitaxial layer to become the base region of a P N P transistor higher than that of an N-type epitaxial layer on the periphery of a memory cell, and reducing the resistivity of a part to become the base region of the transistor in a P N P load memory. CONSTITUTION:An N-type impurity is additionally implanted in high concentration to a whole N<-> type epitaxial layer by limiting to a memory cell of the P N P load memory cell of a semiconductor memory as an impurity high concentration region 22a. An N<-> type epitaxial layer 22 remains without enhancing its concentration in the N P N transistor 27 of a peripheral circuit S except a memory cell M. Thus, the resistivity of the region 22a is low, the base parasitic resistance 26 of the P N P transistor 1 of the cell M is reduced, and saturation of the N P N transistor 3 associated with the transistor 1 and an inverter at the time of reading is decreased. Accordingly, the writing time of this semiconductor memory is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a random access memory using bipolar transistors.

[Conventional technology]

FIG. 5 is a circuit diagram showing a known pnp load memory cell, for example, from Japanese Patent Laid-Open No. 50-38428. In the figure, 1.2 is a pnp transistor, 3.4 is a multi-emitter nprl transistor, and prz:+ The base of transistor 1 is connected to the collector of npnl- transistor 3, while the collector of pnp transistor 1 is connected to npn'
One inverter 5 is connected to the base of the l-transistor 3. Further, another inverter 5 is configured by connecting another set of pnp transistor 2 and npn transistor 4 in the same manner. By cross-connecting these two sets of inverters 5, a flip-flop circuit serving as a pnp load memory cell is constructed.

FIG. 6 is a circuit diagram showing the main parts of a memory circuit using the above-described pnp load memory cell, and in the figure, 6a,
6b is a pnp load memory cell having the above configuration, 7.8 is a constant current source for retaining information in the memory cell, 9.10 is a read/write transistor, and 11.12 is a read/write constant current source. . 13 and 14 are bit line pairs, each of which connects the npn transistor 3 of each memory cell 5a, 5b.
It is connected to one emitter of a, 4a, 3b, and 4b. 15.16 is word line, 17.18 is word line 15
．． 16 drive transistor.

19 is an output circuit, which includes read/write transistors 9,
Connected to 10 collectors. Although FIG. 6 shows a memory cell array configuration of two rows and one column to simplify the following explanation, it is actually configured with a larger number of memory cells.

FIG. 7 is a cross-sectional view showing the vertical structure of one inverter 5 in the memory cell shown in FIG. An n+ buried layer 21 is formed,
A collector electrode (not shown) is connected to this. 22
is an n- type epitaxial layer formed on a part of the n+ buried layer 21 and providing a base region of the pnp transistor 1;
A p-type diffusion region 23a serving as the emitter region of the pnp transistor 1 and another p-type diffusion region 23b serving as the collector region of the pnp transistor 1 and the base region of the npn transistor 3 are formed in a part of the upper region. ing. Further, above the p-type diffusion order tg23b, an n+ type diffusion region 24, which becomes two emitter regions of the npn transistor 3, is formed. Reference numeral 25 denotes an isolation oxide film that insulates and isolates the memory cell portion from other peripheral circuits. In addition,
In the figure, a pnp transistor 1 is shown in correspondence with an n-type epitaxial layer 22 and p-type diffusion regions 23a and 23b.
It shows the shape of. 26 is the pnp transistor 1
is the base parasitic resistance of Although not shown, the vertical structure of the other inverter 5 consisting of the pnp transistor 2 and npnl transistor 4 in FIG. 5 is also the same as that described above.

FIG. 8 is a diagram showing the relationship between potentials during reading and writing of the memory circuit of FIG. 6, and the reading and writing operations of the memory circuit will be described below with reference to this diagram.

In FIG. 6, in memory cell 6a, transistor 1a
, 3a are on, transistors 2a and 4a are off, and in memory cell 6b, transistors 2b and 4b are on.
is on, transistor 1b.

3b is in the off storage state. Reading and writing information begins by first selecting memory cells 6a and 6b. The selection is performed by setting the word line to which the memory cell to be selected is connected to a higher potential than other word lines. Assuming that memory cell 6a is selected and memory cell 6b is not selected, word line 1
The potential of word line 5 is set to be higher than that of word line 16. At this point, due to the above-described storage state, the node N of the memory cell 6a has a higher potential than the node N1a, and the potential of the high potential node N2a is the same as that of the word line 15.
The potential of the low potential node "1a" is lower than the word line 15 by the base-emitter potential difference VBE (approximately 0.8 V) of the transistor 1a.
The node N1b of the memory cell 6b has a higher potential than the node N2b, and the potential of the high potential node N1b is approximately equal to the potential of the word line 16, and the potential of the low potential node N1b
The potential of 2b is lower than the word line 16 by 1-the base-emitter amount localization difference VBE (about 0.8 V) of transistor 2b. Information held by the memory cells 6a and 6b is held by a constant current source 7.8.

When reading the information of the selected memory cell 6a from the above state, the base potential V 1 of the read/occupy transistor 9.10 is set to be between the potentials of the node N1a and the node N2a. Regarding the bit line 13, the transistor 3a,
Since transistors 3b and 9 form emitter-coupled logic for constant current 11Ti11, at this time transistors 3a and 3b
, 9, only the current of the transistor 3a having the highest base potential is supplied as the current of the constant current source 11. on the other hand,
With respect to bit line 14, the base of transistor 0 °
The potential is the highest, and the current of the constant current source 12 is the transistor 1
Supplied by 0. Then, the output circuit 19 detects which of the read/write transistors 9 and 10 current is flowing through, and the information of the memory cell 6a is outputted to the outside in accordance with the detection.

On the other hand, when writing inverted information of the information held at the time of reading into the memory cell 6a, that is, when the transistor a,
3a off, transistor 2a.

When transistor 4a is turned on, the base potential VR of read/write transistor 9 is higher than node N2a, and the base potential of read/write transistor 0 is lower than node N2a.

is set to At this time, regarding the bit line 13, the transistor 9 has the highest base potential, and the bit line 1
Since the transistor 4a is the transistor 4a, the transistor 2a is turned on when the transistor 4a is turned on, and the node N2a changes from a high potential to a low potential. Further, when the transistor 3a of the memory cell 6a is turned off, the transistor a is also turned off, and the potential of the node N1a changes from a low potential to a high potential.

Therefore, the potentials of nodes "1a" and "2a" are inverted as shown in FIG. 8, and inverted information is written.

[Problem to be solved by the invention]

Conventional semiconductor memory devices use pnp load memory cells with the above configuration, which has the advantage that the memory size is smaller than in the case of memory cells that use high resistance elements as load elements of the inverter 5. However, the reason is as follows. Therefore, there is a problem that the writing time (indicated by the symbol TW in FIG. 8) becomes longer. That is, in the memory cell 6a of FIG. 6, the transistors la and 3a are on during reading, but at this time the base of the npn transistor 3a is turned on.
The collector is forward biased.

The magnitude of the bias is equal to the collector-base voltage (approximately 0.8 V) of the pnp transistor 1a, which is a load element, and thereby increases the base current of the pnp transistor 1a flowing to the collector of the npn transistor 3a. The current amplification factor of the pnp transistor 1a is usually 1
0, and the current amplification factor of the npn transistor 3a is usually 1.
Since it is about 00, the npn transistor 3 at this time
The collector current of a becomes 1/10 or more of the current flowing through the entire memory cell 6a (the current ratio of each part in the above case is shown in the memory cell of FIG. 5), and this npn transistor 3a becomes deeply saturated. . Accordingly, the base current of the r+pn transistor 3a increases, and a large number of minority carriers (electrons) are injected into its base region. Therefore, in order to turn off the npn transistor 3a during writing, it is necessary to eliminate the minority carriers accumulated in the base region by recombination with holes, etc. However, due to the saturation described above, a large number of minority carriers exist. Because, npn
It takes a long time for the transistor 3a to turn off, which is a factor in improving the write time TW. In addition, another factor that deepens the saturation of the above-mentioned npn transistor 3a is the influence of the base parasitic resistance 26 of the pnp transistor 1 (corresponding to the pnp transistor 1a in FIG. 6) shown in FIG. . In other words, due to the voltage drop due to the collector current of the npn transistor 3a and the base parasitic resistance of the pnp transistor 1a, the forward bias between the base and collector of the npn transistor 3a becomes even larger, and the npn transistor 3a This is making the saturation even deeper. This means that in a pnp load memory, the greater the base parasitic resistance of the pnp transistor, the deeper the saturation of the npnl-transistor and the better the write time.

In a simulation conducted by the inventor, it was found that when the base parasitic resistance is doubled, the writing time also approximately doubles.

The present invention was made to solve these problems, and by reducing the resistivity of the base region of the pnρ transistor in the pnp load memory, the above-mentioned base parasitic resistance is reduced, and the write time is reduced. An object of the present invention is to obtain a semiconductor memory device that can shorten the time.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, the base of the pnp transistor is connected to the collector of the npnl-transistor, and the collector of the pnp transistor is connected to the collector of the npnl-transistor.
A semiconductor memory device in which a memory cell is a flip-flop circuit in which two sets of inverters connected to the base of a pn transistor are cross-connected, the impurity concentration of an n-type epitaxial layer serving as a base region of the pnp transistor , the impurity concentration is higher than that of the n-type epitaxial layer constituting the npn transistor around the memory cell.

[Effect]

In this invention, the resistivity of the base region of the pnp+- transistor constituting the load of the pnp load memory cell is reduced, and the parasitic resistance of the base is reduced.
caused by the collector current of the npn transistor combined with the np transistor and the base parasitic resistance,
The base-collector bias voltage drop of the npn transistor is suppressed, the saturation of the npn transistor during reading is reduced, and the write time is shortened accordingly.

[Example of fruit eggplant]

FIG. 1 is a cross-sectional view showing the vertical structure of a ρnp load memory cell and its peripheral circuit portion of a semiconductor memory device according to a first embodiment of the present invention, and the circuit configuration of the memory cell and the configuration of the memory circuit are Since this is the same as the case of the conventional device shown in FIGS. 5 and 6, illustration is omitted here. Further, in FIG. 1, parts designated by the same reference numerals as in FIG. 7 are completely the same as those in the conventional device shown in FIG. 7, or correspond to each other. In this embodiment, n-type impurities are additionally implanted at a high concentration into the entire n-type epitaxial layer only in the memory cell portion, thereby making this portion a high impurity concentration region 22a. npn transistor 2 of peripheral circuit S excluding memory cell portion M
7 (for example, transistors 9 and 10 in FIG. 6), the collector-emitter breakdown voltage VCED and the collector-emitter breakdown voltage VCED are
Base-to-base breakdown voltage V is 7V and 10vB, respectively.
Since it is necessary to ensure a concentration of O or more, the n-type epitaxial layer 22
The temperature remains unchanged without increasing to 81 degrees. On the other hand, in the memory cell part, the operating voltage range is clamped by its internal circuit, so the collector-emitter breakdown voltage V.

E, and collector-base breakdown voltage V. 8o may be about 3V, and there is no problem even if the entire n-type epitaxial layer is made into the high impurity concentration region 22a as described above. In FIG. 1, 28 is an npnl-transistor 27 of the peripheral circuit S.
29 is a p-type diffusion region which will be a base region, and 30 is an n'' type diffusion region which will be an emitter region.The number of digits of the impurity concentration of each region in the figure is as follows. It is as shown below.

N+ type 1m21: 102°/cm3N- type epitaxial layer 22: 1015/cm3 High impurity concentration Ij! ! 22a: 1016-1018/Cm3n+ type diffusion region 24: 1020/cm" In this semiconductor memory device, the resistivity of the high impurity concentration region 22a is low, and therefore the base parasitic resistance 26 of the pnp transistor 1 in the memory cell portion M is reduced. and this pnp transistor 1
The above-mentioned saturation at the time of reading of the npn transistor 3 forming an inverter is reduced. Therefore, the write time of this semiconductor memory device is shortened.

FIG. 2 is a cross-sectional view showing the vertical structure of an inverter portion in a pnp load memory cell according to a second embodiment of the present invention. By implanting n-type impurities into the entire region where the 10 base saturation occurs, this region is made into the impurity high i 12 degree region 22a. are the same.

FIG. 3 is a cross-sectional view showing the vertical structure of an inverter portion in a pnp load memory cell according to a third embodiment of the present invention. A high impurity concentration region 22a is formed by implanting n-type impurities into the upper region of the portion that will become the base region of the transistor 1. The other configurations and operations are the same as in the first embodiment.

FIG. 4 is a sectional view showing the vertical structure of an inverter portion in a pnp load memory cell according to a fourth embodiment of the present invention. Of the n-type epitaxial layer 22 in the memory cell portion, by increasing the amount of n-type impurity implanted only in the portion of the mixed layer 21 that also serves as the base region of the pnp transistor 1 that forms an inverter with the npn transistor 3, A high impurity concentration region 22a is formed in the lower region of the base region of the pnp transistor 1. That is, a large amount of n-type impurity implanted into the n+ buried layer 21 is driven by heat treatment such as epitaxial growth, so that the n+ buried layer 2
The high impurity concentration region 22a is formed by diffusion into a part of the n-type epitaxial layer 22 on top of the impurity layer 22a, and the other structure and operation are the same as in the first embodiment.

In the case of this embodiment, instead of locally increasing the amount of n-type impurity implanted into the n+ buried layer 21, the n-type impurity that forms the n+ buried layer 21 is diffused in that region. An n-type impurity having a large coefficient may be implanted. In this case, the n-type impurity with a large diffusion coefficient becomes n
It is diffused into a part of the - type epitaxial layer 22 to form a high impurity concentration region similar to the high impurity concentration region 22a.

In each of the above embodiments, a case has been described in which the base parasitic resistance of the ρnp transistor 1 in the memory cell portion is reduced by selectively implanting n-type impurities, but other means may be used as long as the parasitic resistance can be reduced. A similar effect can be obtained by using 19.

〔Effect of the invention〕

As described above, according to the present invention, since the base parasitic resistance of the pnp transistor constituting the load of the ρnp load memory cell is reduced, the collector current of the npn transistor combined with this pnp transistor and the base The bias voltage drop between the base and collector of the npn transistor, which is caused by the parasitic resistance, is suppressed to a low level, and the saturation of the nprr transistor during reading is reduced accordingly, which has the effect of shortening the write time.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a pnp load memory cell showing one embodiment of the present invention, FIG. M2, FIG. 3 and FIG. 4 are sectional views of a pnpn load memory cell showing other embodiments of the invention, The figure is a circuit diagram of a pnp load memory cell, FIG. 6 is a circuit diagram showing the main part of a memory circuit using a ρnp load memory cell, and FIG. 7 is a circuit diagram of a pnp load memory cell in a conventional semiconductor memory device.
FIG. 8, which is a cross-sectional view of a p-load memory cell, is a diagram showing the relationship between each potential at the time of reading and writing in the memory circuit of FIG. 6. In the figure, 1 is a pnp transistor, 3 is an npn transistor, 22 is an n-type epitaxial layer, 22a is a high impurity concentration region, and 27 is a peripheral npn transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A flip-flop circuit in which two sets of inverters are cross-connected by connecting the base of a pnp transistor to the collector of an npn transistor and connecting the collector of the pnp transistor to the base of the npn transistor is used as a memory cell. In the semiconductor memory device, an n region serving as a base region of the pnp transistor
A semiconductor memory device characterized in that the impurity concentration of the type epitaxial layer is higher than the impurity concentration of the n type epitaxial layer constituting the npn transistor in the periphery of the memory cell.