JPS6079772A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area of a cross connection type semiconductor memory cell while increasing the speed of a semiconductor memory device and minimizing power consumption by using a transistor in place of load resistance in the semiconductor memory device employing the cell. CONSTITUTION:Double emitter transistors 11, 12 are cross-connected while transistors 51, 52 are used in place of conventional resistors as load, and a semiconductor memory cell is formed by the transistors 11, 12 and 51, 52. A plurality of the memory cells are arranged in a matrix shape, word lines 105 are connected to each cell while first current sources 112-115 are connected to one emitters in the transistors 11, 12 through digit lines 101-104, and second current sources 110, 111 are connected to the other emitters. Different voltage is applied to the word lines 105 on selection and on nonselection, selective currents are flowed through the first current sources 112-115 through the digit lines 101-104 on selection, and holding currents are flowed through the second current sources 110, 111 on nonselection.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device using cross-connected semiconductor memory cells in which a transistor is used as a load instead of a load resistor. It is.

As is well known, most of the bipolar type semiconductor memory cells that have been announced so far are composed of flip 70 tubes consisting of transistors 1 and 2 and resistors 3 and 4 which are cross-connected as shown in Figure 1. There is. The disadvantage of this type of cell is that the cell area is large due to the use of collector load resistors 3 and 4.

Furthermore, in order to perform high-speed operation and reduce power consumption, it is desirable to increase the current flowing through the memory cell when reading and writing, and to decrease it when information is being held. However, in the cell shown in Figure 1, the difference between the collector voltages of transistors 1 and 2 (that is, the voltage difference between binary information 1 and 0)
is determined by the current flowing through the cell x the load resistance, so it is impossible to change the value of the current flowing through the cell. Therefore, in order to change the cell current significantly, it is necessary to use a nonlinear load resistance as the load resistance 3°4 so that the difference in collector voltage between transistors 1 and 2 does not change even if the cell current value changes. .

Furthermore, when a semiconductor memory device is constructed by arranging conventional cells in a matrix as shown in FIG. 1, if so-called double selection occurs, in which two or more cells are selected simultaneously,
There was a risk that memory information would be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that has a smaller cell area, lowers power consumption, and prevents destruction of stored information due to double selection, thereby enabling stable operation. be.

The present invention includes first and second transistors of a first conductivity type, and third and fourth transistors having a second conductivity type different from the first conductivity type and each having at least two emitters.
a transistor, the base and collector of the first transistor are connected to the collector and base of the third transistor, respectively, the base and collector of the second transistor are connected to the collector and base of the fourth transistor, respectively, A plurality of semiconductor memory cells are arranged in a matrix in which the base and collector of the third transistor are connected to the collector and base of the fourth transistor, respectively, and the first and second semiconductor memory cells are arranged in a matrix.
the emitters of the transistors are connected to the word line, the first emitters of the third and fourth transistors are connected to the first current source via the digit line, and the second emitters of the third and fourth transistors are connected to the first current source via the digit line. is connected to a second current source,
Different voltages are applied to the word line when the semiconductor memory cell is selected and when it is not selected, and when the cell is selected, the selection current is passed through the first current source through the digit line, and when it is not selected, it is held in the second current source. It is characterized by the fact that it allows current to flow through it.

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 2 is a circuit diagram of a basic embodiment of a semiconductor memory cell used in the present invention. Compared to the conventional cell shown in Figure 1, the resistor 3.4 in Figure 1 is replaced by a PNP transistor 5).
It has been replaced by 1.52. Now, consider a state in which the transistor 11 is conductive and the transistor 12 is non-conductive. P.N.
P) DC amplification factor hFB(PN
When P) is O, that is, PNP) transistor 51.
When 52 acts merely as an emitter-to-base diode, the base current of transistor 11 is supplied from the emitter-to-base diode of transistor 52. On the other hand, the collector current of the NPN transistor 11 is supplied from a diode between the emitter and pace of the transistor 51. NPN) Since the DC amplification factor hF(NPN) of the transistor 11 is about 50 to 100, P
NP) The current flowing through the emitter-base diode of transistor 51 is 50 to 100 times the current flowing through the emitter-base diode of transistor 52, and the collector voltage of transistor 11 is 10 times higher than the base voltage.
It becomes about 0mV lower. Therefore, the base voltage of transistor 12 is J)1
The voltage difference is about 00mV, so the transistor 12
is off, transistor 11 is on, and the flip
A flop circuit can be constructed. A flip-flop circuit that does not operate as a transistor using the above method (that is, transistors 51 and 52 are PNP) can also be used as a memory cell circuit, but if the voltage difference between the base voltages of transistors 11 and 12 is about 100 mV, stable circuit operation cannot be achieved. There's a problem. Next, PNP) transistor 51゜520 DC amplification factor hFB (PNP) is larger than 0, and it is normal PNP.
) The case where it operates as a transistor will be described.

The base current of the transistor 11 that is on is supplied from the collector of the transistor 51 and the base of the transistor 52. Therefore, as explained earlier, PNP
), when the DC amplification factor hFl (PNP) of the F transistor is 0, the current flowing between the emitter and base of the transistor 52 decreases, and the base voltage of the transistor 11 becomes high. The voltage difference between the two becomes much larger, resulting in stable flip and four-way operation. )'ym (PNP) = 1/h
yii (NPN), all of the base current of the transistor 11 is supplied by the collector current of the transistor 51, and the collector voltage of the transistor 11 is about 0.4 to 0.6 V lower than the base voltage. However, the potential difference between the bases of transistors 11 and 12 is 0.4 to 0.
6 V can be obtained.

In addition, hFl (PNP) > 1/h in the active state
In the case of Fl (NPN), a transistor. 11 and 51 are saturated and hFl(PNP) = 1/hFl
Note that the operating point settles at the point where (NPN). As described above, it will be understood that the memory cell of the present invention in which the load resistor is replaced with a transistor operates in a highly stable manner.

FIG. 3 is a cross-sectional view of the semiconductor substrate of one embodiment of the portion within the dotted line of the memory cell in FIG. 300 is a P type substrate, 301 is an NW buried layer, and 302 is an N type epitaxial layer. 303, 304 are Pfi diffusion regions, 305, 3
06,307 is an N type diffusion region. 310 to 314 are aluminum wirings, and 320 is a silicon oxide film. PNP)
The transistor 51 is formed of regions 304, 302, and 303 (collector, base, and emitter, respectively), and has N P
N) Ray register 11 is area 302, 303°30
5t or 306 (collector, base respectively.

emitter). The memory cell O embodiment shown in FIG. 2 is constructed by interconnecting a pair of two transistors having such a structure with aluminum wiring.

As can be seen from the embodiment of FIG. 2, the voltage inside the memory cell is determined by the base voltage of the transistor 11 and the forward voltage of the collector voltage line PN junction.
Therefore, even if the current flowing through the cell is changed, the voltage will not change significantly. For example, even if the cell current is changed by a factor of 100 to 1000, the change in the base-collector voltage of the transistor 11 is about 100 to 150 mV. therefore,
The cell current is 10% when not selected and when selected (read/write).
Even when changed by a factor of 0 to 1000, the cell remains fully binary 0,1.
information can be held.

As mentioned above, this feature makes it possible to reduce power consumption and perform high-speed operation.

FIG. 4 shows an example of a play configuration of a semiconductor memory device according to the present invention. It should be noted that the method of configuring the memory array shown in FIG. 4 is an example, and it goes without saying that the memory cell of the present invention can be used to construct a wide variety of other memory arrays.

In the non-selected state, word lines 105 and 106 are all at a low level, for example -16VGC. At this time, the current flowing through the transistor on the conducting side of the cell, for example, the current flowing through the transistor 51.11 of the cell 201, is supplied from the emitter follower transistor 31 and flows into the current source 110. Due to this holding current, the collector of the transistor 11 becomes, for example, -2.4V, and the base of the transistor 11 becomes, for example, -1.9V. Therefore, the paired transistors 12 and 52 are maintained in a completely noff state.

To read, one of the Vx, for example vx□
to high level and word line 105 to high level, for example -0,
Set it to 8v. Digit lines 101 to 104 have cell N
PN) The emitters of transistors in the transistor meter and the read/write circuit are connected to form a kind of current switch, and current flows through transistors 23 to 30 as a result of comparison of the base voltages of the connected transistors. It is determined whether there is no flow or not, and reading is performed. for example,
Consider the case where word line 105 is at high level -0, SV is not, and transistors 51.11 are conductive. At this time,
The base voltage of transistor 1 is -1.0V, and the base voltage of transistor 2 is -1.5V. On the other hand, the voltage Vref70 is -1,35V during reading, 1,
Wo72. VW171 is at -1,75V. Further, in order to select a certain digit line, the base voltage V of the transistor connected to that digit line is set to a low level. For example, to select digit lines 101 and 102, the voltage 173 should be set to a low level of -1,75V, and the other voltages 173 should be set to a high level of -0,95V.

When each voltage is set as described above, the digit line 101
The voltage is determined by transistor 1 having the highest base voltage, and current flows from transistor 1 of cell 201 to current source 112. In the other selected digit line 102, the transistor 24 has the highest base voltage among the connected transistors, and therefore, current flows only from the transistor 24 to the current source 113. At this time, current flows through the load resistor 121 of the transistor 24, causing a voltage drop, and the information of the cell 1 is read out. cell 20
When the information of 1 is reversed, that is, when transistors 52 and 12 are conductive, a similar read operation causes transistor 23 to be conductive and transistor 24 to be non-conductive, so that the read voltage is taken out as a voltage drop across resistor 120. The read voltage is further amplified by a sense amplifier and taken out to the outside of the device.

During this read operation, digit lines 101 . , 102, the transistor 15 of the other cell 203 connected to
．． The base of 16 is set to -1,9V or -2,4V,
It is completely unrelated to the readout, and the information is transmitted to the current source 1.
11, information is not destroyed. On the other hand, the unselected digit line 103
, 104 is determined by the transistor 25.26, which has V,1 applied to its base at a high level -0,8V, and the current to the current source 114,115 flows through the transistor 25.26. . Therefore transistor 29
．． No voltage drop occurs across the load resistors 122 and 123 of No. 30, and no reading is performed.

For writing, Vx and V are the same as for reading.

1 bit to be written is selected.

For example, suppose that (i) the word line 105 is at a high level (=OV), the word line 105 is at a high level of -0,8V, and V,173 is at a low level of -1,75V. In the case of writing, the voltage Vref70 becomes a low level -1.75V.

On the other hand, one of Vwo72, V, and □71 becomes a high level -0,95V, and the other becomes a low level -1,75V, according to the information to be written. For example, cell 2
Consider a state in which transistor 11 of transistor 01 is conductive and transistor 12 is non-conductive. When vWo is at a high level and ■1□ is at a low level, current flows into the current sources 112 and 113 from the transistors 11 and 22, respectively. This state is the same as the read state, and the information in cell 201 is maintained as is. To write reverse information to the cell 201, Vwo should be set to a low level of -1.75V and ■W1 should be set to a high level of -0.95V. In the state before writing, the base voltage of the transistor 110 is -1, IV, and the base voltage of the transistor 12 is -1,6. Therefore, only the holding current flows through transistor 51.11 of cell 201. On the other hand, the base voltages of transistors 20, 22, and 24 connected to digit line 102 are all -1.75V, and the base of transistor 12 is -1.6V, so a stain current flows into current source 113 from transistor 12. .

When the transistor 12 becomes conductive, the collector current of the transistor 51 flows as the collector current of the transistor 12, and the base current of the transistor 11 no longer flows. For this purpose, the DC amplification factor of the PNP transistor must be hF,
l! (P), NPN) The DC amplification factor of the transistor is hFI
As B(N), hFl (P) >> 1/hF
l (N) usually holds true (usually hFil(P)
""' + hF shoulder (N) -50) ■R/IH>hF
B(P) must hold. However, the current source 112~
115, that is, the read/write current, and ■□ is the current of the current sources 110 and 111, that is, the holding current. It is preferable to increase the R/D in this way in order to reduce power consumption and significantly increase speed.

The storage device of the invention has the advantage that information is not destroyed even with double selection of storage cells during reading. In other words! If the storage cell of Figure @1 is used as a cell of the array of Figure 4, the information in the cell will be destroyed when vx□*vX2 go high at the same time. However, in the cell of the present invention, since the voltages at each part of the cell are determined almost independently of the current flowing through the cell, information is not destroyed even if 2+VX2 are selected at the same time. This also makes the operation of the memory cell of the present invention very stable.

Figure 5 shows an improved embodiment for faster operation. Reference numerals 61 and 62 are Schottky diodes, which prevent saturation of transistors 11, 51 and 12, 52, respectively, and enable high-speed operation. In this embodiment, the voltage difference between the binary information 0 and 1 is determined by the forward voltage of the cut-key diode.

Figure 6 is another embodiment of the present invention, in which a resistor 63 is further added to the embodiment of Figure 2 to stabilize the operation. As mentioned above, the internal voltage of the memory cell of the present invention does not depend on the current flowing through the cell, so the resistor 6
Since the value of 3 can vary widely, an epitaxial layer can be used as the resistor, and the resistor can be made small.

In addition, in the above, the double emitter transistor is NPN
Although the cell of the present invention has been described assuming a PNP type and a single emitter transistor, it goes without saying that the cell of the present invention can be similarly constructed with double emitter PNP and single emitter NPN transistors.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventionally widely used memory cell, FIG. 2 is a circuit diagram of an embodiment of the memory cell of the present invention, and FIG.
The figure is a cross-sectional view of an embodiment in which the memory cells of FIG. 2 are integrated;
FIG. 4 is a circuit diagram of one embodiment of a memory cell array using the memory cell of the present invention, FIG. 5 is a circuit diagram of another embodiment of the memory cell of the present invention, and FIG. 6 is a circuit diagram of a memory cell array of the present invention. FIG. 3 is a circuit diagram of yet another embodiment of the present invention. 11.12 is NPN) transistor, 51.52 is PNP
) is a transistor. Figure 1 Figure Z tail, Figure 3 Figure 4 S

Claims (1)

[Claims] 1. first and second transistors of a first conductivity type;
third and fourth transistors having a second conductivity type different from the first conductivity type and each having at least two emitters, the base and collector of the first transistor being connected to the third transistor; The base and collector of the second transistor are connected to the collector and base of the fourth transistor, respectively, and the base and collector of the third transistor are connected to the collector and base of the fourth transistor, respectively. A plurality of semiconductor memory cells each connected to a collector and a base thereof are arranged in a matrix, and emitters of the first and second transistors of the semiconductor memory cells are connected to each other.
the first emitters of the third and fourth transistors are connected to a word line, the first emitters of the third and fourth transistors are connected to a digit line, the digit line is connected to a first current source;
A fifth transistor of a second conductivity type is connected to a second current source, and a fifth transistor of a second conductivity type is connected to a second current source.
a transistor, the emitter of the fifth transistor is connected to the digit line, the base is connected to a reference voltage source, and when the semiconductor memory cell is selected, the first current source is selected from the semiconductor memory cell. When the semiconductor memory cell is not selected, a holding current is caused to flow from the single-conductor memory cell to the second current source, and the collector of the fifth transistor obtains a readout output. A semiconductor memory device characterized by and. 2. The semiconductor memory device according to claim 1, wherein the second current source is provided in common to a plurality of semiconductor memory cells.