JPS63104376A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enlarge a capacity between B-C in a memory cell and a hold voltage, by making an epitaxial layer in the memory cell part be smaller in thickness than the peripheral part of the memory cell part and forming guard rings on the periphery of a Shottky barrier diode. CONSTITUTION:In a random access memory in which bipolar transistors are used, a N-type epitaxial-layer 3 in a memory cell part M is made smaller in thickness than the peripheral circuit part S of the memory cell part M. Thus, N type impurities rise from a N<+> type embedded layer 2 and conjointly a junction capacity Cpi between base and collector in the memory cell part M can be increased. Together with the formation of an external base, a guard ring made of a P<+> type diffusion layer 19 of high impurity concentration is formed on the periphery of a Shottky barrier diode 9. Because this guard ring enables the parallel connection of the Shottky barrier diode 9 with PN junction diodes 19a and 19b, a forward voltage across the diode 9 and a hold voltage of the memory cell can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a random access memory using bipolar transistors.

[Conventional technology]

A structural cross-sectional view of a bipolar transistor memory cell according to the prior art is shown in FIG. FIG. 6 is its equivalent circuit diagram. In FIG. 5, a P-type substrate f, which is the first conductivity type,
An N-type buried layer (2) of the second conductivity type is formed on the il, and an N-type epitaxial layer (3) is formed on the N half-type buried layer (2). , a P+ type base diffusion region (4) is formed on the N− type epitaxial layer (3), and N0 type emitter regions (5a), (5b) are formed in the Pφ type base diffusion region (4). is formed.

Further, +71 and +81 are oxide films, and the elements are separated by an oxide film (8). Also, (6a) to (6e) are A
! In the wiring, (6g) is the collector, (6b), (6d)
is connected to the emitter, (6c) is connected to the base, and (6e) is connected to the positive word line. (9) is a Schottky barrier diode, and tlol is a resistor.

Figure 6 shows a diode clamp type memory cell with a multi-emitter transistor (l) for reading and writing stored information.
A load resistor (10a) and a Schottky barrier diode (9a) are connected to the collectors of la) and (llb), respectively.
A parallel connection body with a load resistor (10b) and a Schottky barrier diode (9b) are connected,
It constitutes a flip-flop. (6) is a positive side word line, and (12) is a negative side word line. These are connected to a constant current source (not shown in the figure) for memory retention, and draw a constant current from each memory cell.

Further, (13a) and (13h) are bit lines, which are multi-emitter transistors (l1m) and (llb
) is connected to one of the emitters. Also (14m
), (14b) are Schottky barrier diodes (9a
), (9b) junction capacitance C3BD, (15a), (
15b) is a multi-emitter transistor (lla), (
llb) base-collector junction capacitance CTC.

(16a) and (16b) are multi-emitter transistors (lla).

Pace-emitter junction of (llb) @ cTg 1 (
17a) + (17b) represents the junction capacitance c (hereinafter referred to as "collector-substrate junction capacitance") Crs between the collector of the multi-emitter transistor (lla), (llb) and the substrate ill.

Now, in Fig. 6, a multi-emitter transistor (l
Assume that la) is off and (llb) is on.

At this time, the potential of the collector node N of the multi-emitter transistor (lla) is set to vNl (11b), and the potential of the collector node M of the multi-emitter transistor (lla) is set to VM, and this is set as the first storage state. The potential difference between the passing collector nodes N and M (hereinafter referred to as the t-field voltage vH of the memory cell) is VN - VM
-0-: About 3r, and VN and VM are values determined by the voltage drop due to the 9-load resistance (10m) and (10b), respectively.

When α rays pass through the semiconductor in this state, electron-hole pairs are generated, but the electron-hole pairs generated in the depletion layer instantly flow into the P-type region, KS, and the N-type region, creating a noise current. becomes. If the charge generated by the entry of α rays is Q, then the potential level of the collector nodes N and M is instantaneously determined by the charge Q and the capacitance tc applied to the collector nodes N and M. However, c-crs+csBD+4ctc +2
It becomes CTE. At this time, when VH'<O, the magnitude relationship between the potentials of the collector nodes N and M is reversed from VN>VM to VH<VM, that is, the storage state of the memory cell is reversed. In order to maintain VH'>O even if an α ray enters and generates a charge, it is sufficient that vH-C>Q. That is, it is sufficient to increase the hold voltage vH and further increase the capacitance tC within the range allowed by the power consumption.

The hold voltage vH is clamped by the forward pressure of the Schottky barrier diodes (9g) and (9b) in Fig. 6, but in the past, a single Schottky barrier diode was used as the clamping diode. .

Furthermore, since the junction tC18m) and CTC of the capacitance C are connected in parallel to the load resistances (10m) and (10b) of the memory cell, they play the role of a speed-up capacitor.

Since Crc is effective by a factor of 2 due to the mirror effect, it can be said that increasing this CTC makes it stronger against information reversal due to alpha rays.

In Figure 5, the junction 11th CTC is N
- type epitaxial layer (3) and P-type base diffusion region (
There is a first PNN junction with 4), and its capacity value varies depending on the PN junction area and the impurity concentration at the junction. The latter of these is
In FIG. 5, the distance between the door-shaped base diffusion region (4) and the N-shaped buried layer (2) depends on the thickness of the N-type epitaxial layer (3). In the conventional technology, the N-type epitaxial layer (3) was formed simultaneously in the memory cell section and the peripheral circuit section, and was controlled to have the same thickness.◇ [Problems to be solved by the invention] Conventional Since the conventional semiconductor memory device was constructed as described above, for example, if the N-type epitaxial layer (3) is made thicker, the base-collector junction capacitance Crc of the transistors in the memory cell part and the peripheral circuit part becomes smaller. Although high-speed operation is possible, on the other hand, because the capacitance is small, information in the memory cell is more likely to be inverted due to alpha rays or the like. On the other hand, if the N-type epitaxial layer (3) is thinned, CTc
becomes larger, making it less likely that information will be inverted in the memory cell, but on the other hand, it has the drawback that high-speed operation cannot be expected.

Furthermore, if the clamping diode is a Schottky barrier diode alone, the forward voltage is small, so the hold voltage vH of the memory cell is small. The objective is to obtain a semiconductor memory device that is capable of high-speed operation and has high reliability.

[Means for solving problems]

In order to achieve such an object, the present invention provides that the thickness of the epitaxial layer of the second conductivity type in the memory cell portion of the substrate of the first conductivity type is thinner than that of the peripheral circuit portion, and that the thickness of the epitaxial layer of the second conductivity type is thinner than that of the peripheral circuit portion. Gartling is applied around the diode by forming a first conductivity type diffusion layer with a high impurity concentration simultaneously with the formation of the external base.

[Effect]

In the semiconductor memory device according to the present invention, since the thickness of the epitaxial layer of the second conductivity type constituting the collector of the transistor in the memory cell portion is made thinner than that in the peripheral circuit portion, the above-mentioned junction capacitance it CTC is reduced. In addition, since a guard ring is formed around the Schottky barrier diode, the forward voltage increases, and the hold voltage vH of the memory cell increases accordingly, allowing high-speed operation. It also becomes more resistant to reversals.

[Embodiments of the invention]

FIG. 1 shows a sectional view of an embodiment of a semiconductor memory device according to the present invention. As shown in FIG. 1, &1. S shown surrounded by lines indicates a transistor in the peripheral circuit section, and M indicates a memory cell section, which are formed on the same substrate. The circuitry of the memory cell section M is as shown in FIG. In FIG. 1, an N small buried layer (2) is formed on a P-type substrate ill, and an N'' type epitaxial layer (3) is formed on the N small buried layer (2). A P+ type base diffusion region (4) is formed on the N″″ type epitaxial layer (3), and N type emitters afJR (5a), ( 5b).

0 (6a) to (6h) where (5c) is formed is A! In the wiring, (6g) and (6f) are the collector and (6c)
), (6h) are the base, (6b) + (6d), (6
g) is connected to the emitter, and (6e) is connected to the positive word line. (71, +81 are oxide films, and the peripheral circuit section S and memory cell section M are separated by an oxide film (8). Also, (9) is a Schottky barrier diode, and tlol is a resistance that serves as a load for the memory cell. It is.

(181 is a guard ring formed by a P-type diffusion 11 formed around the contact portion of the Schottky barrier diode (9).

FIGS. 3 and 4 are cross-sectional views showing a method of manufacturing a portion in which the thickness of the N-type epitaxial layer in the memory cell portion is made thinner than that in the peripheral circuit portion in the device shown in FIG. @1. . S is a peripheral circuit section, and M is a memory cell section. First, in FIG. 3, a KN 0-type buried layer (2) is formed on a P- type substrate (1), and an N- type epitaxial layer #i31 is formed on the N+ type buried layer (2). After forming the N-type epitaxial layer (3), the peripheral circuit section S is masked with a resist decoration, only the memory cell section M is selectively oxidized, and then etched to form the memory cell section M, as shown in FIG. The thickness of the N″′ type epitaxial # (31) can be made thinner than the thickness in the peripheral circuit portion S.

After that, in the conventional process, a p-1-fJ external base region is formed, and at the same time, a high impurity-concentration P-type diffusion layer for a guard ring is formed around the contact of the Schottky barrier diode, and the final The apparatus shown in FIG. 1 is obtained.

As shown in FIG. Coupled with the floating of N-type impurities, the base-collector junction capacitance CTC of the memory cell portion M increases,
Furthermore, at the same time as forming the external base, the guard ring (country) of the P-type diffusion station with a high impurity concentration increases the PN junction area, and the parasitic capacitance (14s) in Fig.
b) becomes larger.

In addition, Schottky barrier diodes (9a), (9b
) The area of the Schottky barrier diodes (9a) and (9b) is reduced by providing a guard ring around the diodes (19a) and (19b). Inserted in parallel, Schottky barrier diode (9m),
The forward pressure in (9b) increases, and the hold voltage vH of the memory cell increases.

In addition, Schottky barrier diodes (9g), (9b
) guard ring α & due to the P-type diffusion layer is such that when phosphorus (P) is used as the N-type impurity, phosphorus pile-up occurs near the interface with the isolation oxide film, increasing the N-type impurity concentration. It also has the traditional effect of suppressing it.

In addition, Schottky barrier diode +9a), (9b
) The area of the intervening junction capacitance fcsBD is reduced, but this is compensated for by the PN junction capacitance formed by the guard ring (181) of the P-type diffusion layer.Therefore, the guard ring (18) is located in the external base region. Similarly, a high impurity concentration is required, and the obtained PN junction capacitance cannot be said to be sufficient if the impurity concentration is lower than that of the external base region, as in the conventional case where a guard ring is formed at the same time as the base region is formed.

As a result of the above effects, the memory cell becomes resistant to information inversion caused by α rays and the like, resulting in a highly reliable Xf.

On the other hand, the pace collector junction capacitance t cT of the peripheral circuit section S
Since c acts only as a parasitic capacitance, it is desirable to make it as small as possible, but as shown in FIG. The junction capacitance between ICTC and ICTC is small, so high-speed operation is possible.

Although the manufacturing method of this device is shown in FIGS. 3 and 4, any method can be used to make the thickness of the N-type epitaxial layer in the memory cell section M thinner than that in the peripheral circuit section S. It goes without saying that any other method is acceptable.

Note that although the upper side shows a case where the first conductivity type is P type and the second conductivity type is N type, the present invention is also applicable to the reverse case.

〔Effect of the invention〕

As explained above, in the present invention, by configuring the first conductor to reduce the film thickness of the second conductor layer only in the memory cell portion of the semiconductor substrate,
It is possible to increase the pace-collector junction capacitance in the memory cell section, and by providing a guard ring of the first conductivity type diffusion layer with a high impurity concentration around the Schottky barrier diode, the hold voltage vH of the memory cell can be increased. It is possible to operate at high speed, and the junction capacitance between the pace collectors can be further increased.
This has the effect of making it possible to obtain a highly reliable semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a diode clamp type memory cell constructed according to this embodiment.
4 is a cross-sectional view for explaining the manufacturing method of this embodiment device, FIG. 5 is a cross-sectional view showing a conventional semiconductor memory device, and FIG. 6 is a circuit showing a conventional diode clamp type memory cell. It is a diagram. In the figure, M is a memory cell section, S is a peripheral circuit section, (I
ll is a semiconductor substrate, (3) is epitaxial growth, 1-
1 (9) is a Schottky barrier diode, and (181 is a guard ring. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A Schottky junction is formed between a first bipolar transistor whose collector layer is an epitaxial growth layer of a second conductivity type formed in each first active region of a semiconductor substrate of a first conductivity type and the epitaxial growth layer. and a load means including the first Schottky barrier diode formed as a parallel element to constitute an inverter, and a plurality of memory cells constituted by flip-flops formed by connecting two of these inverters in combination with each other. and a peripheral circuit constituted by a second bipolar transistor whose collector layer is an epitaxial growth layer of a second conductivity type formed in a second active region other than the first active region of the semiconductor substrate. In the semiconductor memory device formed by the epitaxial growth layer of the first active region,
The thickness is thinner than the epitaxial growth layer of the active region of
A semiconductor memory device further comprising: a first conductivity type diffusion layer having a high impurity concentration and forming an external base region of the first bipolar transistor and forming a guard ring surrounding the Schottky junction.