JPS6216028B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor memory device, and in particular to a PNPN
The present invention relates to a semiconductor memory device having shaped memory cells.

(2) Background of the Technology Currently, in bipolar semiconductor memory devices commonly used, memory cells with a diode load or a Schottky Barrier Diode (SBD) load are widely used. However, it is known that this type of memory cell is not suitable for large-capacity storage devices that require a small holding current. That is, in order to reduce the holding current, it is necessary to increase the resistance value, which makes it difficult to reduce the cell area.

Therefore, in recent years PNP transistor loads or
PNPN type memory cells and ^I2L type memory cells with NPN transistor loads are attracting attention.
It is generally known that I ² L type memory cells cannot achieve as high-speed operation as PNPN type memory cells.

(3) Prior Art and Problems A conventional PNPN memory cell is shown in FIG. FIG. 2 shows an equivalent circuit of the PNPN type memory cell of FIG. 1. The memory cell in FIG.
It is formed on a type semiconductor substrate (P-SUB) 11, and a portion corresponding to a half cell in the circuit shown in FIG. 2 is formed in a region isolated by isolation (ISO) 18 and 19. A heavily doped N-type buried layer 12 is formed on a P-type substrate 11, and an N-type region 13 is formed on the buried layer 12. Within the N-type region 13 are two P-type regions 14,1.
5 is formed. Two N-type regions 16 and 17 are formed within the P-type region 15.

As shown in Figure 2, within the half cell,
Three junction pairs Q ₁ , Q ₂ , Q ₃ are formed which equivalently operate as transistors. The PNP type transistor _Q1 has a P type region 14 as an emitter region,
It is formed using N type region 13 as a base region and P type region 15 as a collector region. The NPN transistor _Q2 is formed using the N-type region 13 as a collector region, the P-type region 15 as a base region, and the N-type region 17 as an emitter region. Also, NPN transistor
Q ₃ is formed using the N-type region 13 as a collector region, the P-type region 15 as a base region, and the N-type region 16 as an emitter region. The P-type region is connected to the first word line W ⁺ through a contact window. N-type area 1
7 is connected to the second word line ^W- through a contact window. N-type region 16 is connected to E through the contact window.
_S and connected to bit line _BL1 . N-type region 13 is led out to point C through the contact window, and P-type region 15 is connected to point B through the contact window.

The PNPN type memory cell in Figure 2 has a diode
When compared with a resistive load type memory cell, it can be considered as a memory cell in which the PNP transistor Q ₁ is used as a load to keep the NPN transistor Q ₃ in the on or off state. However, PNPN
The type memory cell shares the base-collector connection of the PNP transistor _Q1 and the base-collector junction of the NPN transistor _Q3 , as shown schematically in FIG. It is impossible to consider the collector current and base current separately in the equivalent circuit expressed using . In fact, the first and second word lines W ⁺ ,
The voltage/current characteristics of the PNPN element constituting the half cell between W ^- are often expressed by a unique characteristic curve having negative characteristics, as shown in FIG. (Depending on the structure, negative resistance may not appear.) Therefore, the PNPN type memory cell shown in Fig. 2 has two stable current values for the same voltage value in the characteristic curve shown in Fig. 4. Taking advantage of this fact, a half cell in the on state and a half cell in the off state are created between the two word lines W ⁺ and W ^- to hold the memory contents.

By the way, in the conventional PNPN memory cell described above, it is not possible to use a pulse in the wiring layer as in the I ² L memory cell described above.
It is necessary to route the word lines W ⁺ and W ^- through the contact window, which is disadvantageous in reducing the cell area. Also, as shown in Figure 1, a transistor
Although Q ₂ and Q ₃ are formed vertically, the transistor Q ₁ is formed horizontally, which tends to cause variations in characteristics, particularly causing problems in switching speed during writing.

(4) Object of the Invention In view of the problems of the conventional type described above, the main object of the present invention is to provide a transistor that uses a buried layer as a wiring layer and forms a PNPN element in a semiconductor memory device having a PNPN memory cell. By forming all the cells vertically, the cell area can be reduced and the switching speed can be improved.

(5) Structure of the Invention In the present invention, a group of pairs of a first word line connected to a word line drive circuit and a second word line connected to a holding current source, a group of pairs of bit lines, and a memory cell provided at each intersection of the word line pair and the bit line pair, the memory cell comprising a pair of memory cells connected in parallel between the first and second word lines.
In the semiconductor memory device having a PNPN type element, the PNP (or NPN) transistor is a load transistor, and the NPN (or PNP) transistor is a driving and information holding transistor whose base and collector are cross-connected to each other, A PPNN type element of a memory cell is formed on a buried layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type in a region surrounded by an isolation region, and the PPNN type element is formed in a region surrounded by an isolation region. a first region of one conductivity type formed on the layer, a second region of the opposite conductivity type formed on the first region, a third region formed separately from each other on the second region, and one conductivity type. the third region is made of a semiconductor of one conductivity type or a metal having a shot barrier with the second region; the load transistor is composed of the buried layer, the first and second regions; The driving transistor is composed of the first, second and third regions, and the information holding transistor is composed of the first, second and third regions.
and a fourth region, the first, second, third, and fourth regions are each connected in a predetermined manner on the substrate, and the buried layer is connected to one of the first and second word lines. Provided is a semiconductor memory device characterized in that it is a wiring layer for.

(6) Embodiment of the Invention A semiconductor memory device as a first embodiment of the invention is shown in FIGS. 5 and 6. FIG. 5 shows a schematic circuit diagram of the semiconductor memory device.
FIG. 6 is a cross-sectional view showing the structure of the semiconductor memory device of FIG. 5 on a substrate.

The semiconductor memory device shown in FIG. 5 has a first word line W ⁺ _{1 .} . . W _o ⁺ connected to a word line drive transistor Q _D and a second word line W ₁ ^- connected to a holding current source I _H. ,…
. . . It has m×n memory cells MC-i,j connected between W _o ^- . Memory cell MC-i,
j is also the bit line pair BL ₁ and BL ₂ , ... BL _2n-1 and
Connected to one pair of BL _2n . memory cell
Each of MC-i,j is PNPN shown in FIG.
It is represented by the same equivalent circuit as a type memory cell.
Each bit line pair has a bit line clamp circuit BC ₁ to
BC _n and bit line drive circuits BD ₁ to _{BD n} are connected. A word line selection signal WLS ₁ ...WLS _o is applied to the base of each word line drive transistor Q _D , and a bit line selection signal BLS ₁ ... BLS _n is applied to the bit line drive circuits BD ₁ to BD _n . Ru. Further, a common bit clamp level signal BCL is supplied to all bit line clamp circuits BC ₁ to _{BC n} .

One of the memory cells shown in FIG.
The configuration of MC-1,1 on the board is shown in FIG. Figure 6 shows an N-type semiconductor substrate (N-SUB).
A word line driving NPN type transistor Q _D formed on the word line drive layer 21 , a P type buried layer 22 forming a wiring layer for the word line W ₁ ⁺ , and a memory cell MC-1, 1, formed on the buried layer 22 and a PNP transistor Q _S formed around the memory cell. Since the buried layer is used as a wiring, the conductivity is increased as a highly concentrated impurity layer. The memory cells MC-1, 1 in FIG. 6 are PNPN type cells consisting of a pair of half cells, as described above. Each half cell is formed within an area separated by an isolation area ISO. This isolation region does not separate the buried layers when separating cell rows MC-i,j (j=1 to m), but also separates the buried layers when separating n cell rows. , deepen the isolation.

In the divided area, the N-type area 23
is formed on the buried layer 22, and the P type region 24 is formed on the buried layer 22.
formed on the N-type region 23 and N-type regions 25 and 2.
6 are formed on the P-type region 24 and separated from each other. The PNP transistor Q ₁ in the equivalent circuit shown in FIG.
and P-type region 24, NPN transistor Q ₂ is formed by N-type region 23, P-type region 24 and N-type region 25, and NPN transistor Q ₃ is formed by N-type region 23, P-type region 24 and N-type region 24. It is formed by a shaped area 25.

The N-type region 23, P-type region 24, and N-type regions 25 and 26 are connected to metal wiring via contact windows on the surface opposite to the N-type substrate 21. N-type region 23 of one half cell is connected to P-type region 24 of the other half cell by metal wiring. N-type region 25 is connected to the bit line. The N-type region 26 is also connected to the word line W ₁ ^- . The buried layer 22 is formed in common to the memory cells MC- ⁱ ,j connected to the word line _W1- , connected to the metal wiring through the contact hole CH, and further connected to the emitter of the transistor _QD . Therefore, the buried layer 22 forms a wiring layer for the word line W ₁ ⁺ .

In the semiconductor memory device of FIG. 6, transistors Q ₁ , Q ₂ , Q ₃ forming a PNPN half cell
are all vertically shaped, which speeds up switching and reduces variation in characteristics. In addition, since the buried layer 22 is used as a wiring layer for the word line W ₁ ⁺ , the number of metal wirings is reduced and two contact windows per memory cell are no longer required, improving yield and reducing cell area. is easy.

Next, a semiconductor memory device as a second embodiment of the present invention is shown in FIGS. 7, 8, and 9. FIG. 7 shows an equivalent circuit A and a schematic configuration B of a memory cell in the semiconductor device. FIG. 8 shows a schematic circuit diagram of the aforementioned semiconductor memory device constructed using the memory cells shown in FIG. 7. FIG. 9 shows the structure of the semiconductor memory device on the substrate.

The PNPN type memory cell shown in FIG. 7A differs from the one in FIG. 2 by using an NPN transistor Q ₁ ' as a load transistor and
configured to hold Q ₃ ′ in an on or off state. Therefore, in a semiconductor memory device using ^the memory cell shown in FIG. 7, as shown in FIG. 8, a current source I _H is connected to the positive word line W _{1 +} ^. side word line W ₁ ^- ...W _o ^- for word line driving
Connected to NPN transistor _QD . In this way, in the semiconductor memory device of FIG.
The polarity of the signal line and the polarity of the transistor are reversed from those in the figure. Therefore, in the structure on the substrate shown in FIG. 9, the conductivity types are reversed, N-type and P-type, compared to the structure shown in FIG. 6. Therefore, in the semiconductor device of the second embodiment, the buried layer 22' is used as a wiring layer for the word line W ₁ ^- .

As a modification of the second embodiment, it is also possible to configure the half cell as shown in FIG. 10.

In FIG. 10, a metal forming a shot barrier is provided on the surface of the N-type region and used as an electrode to form a shot barrier diode SBD.

In other words, in this modification, the P-type region on the buried layer,
The N-type region thereon and the shot barrier electrode constitute a driving transistor.

(7) Effects of the Invention According to the present invention, it is possible to provide a semiconductor memory device having a PNPN memory cell in which the cell area can be easily reduced, the switching speed can be improved, and the characteristics have less variation.

[Brief explanation of the drawing]

Figure 1 shows a conventional semiconductor memory device.
2 is a circuit diagram showing the equivalent circuit of the PNPN type memory cell in FIG. 1, and FIG. 3 is a diagram schematically showing the equivalent circuit in FIG. 2. , Figure 4 shows the voltage and
5 is a schematic circuit diagram of a semiconductor memory device as a first embodiment of the present invention, and FIG. 6 is a sectional view showing the configuration of the semiconductor memory device of FIG. 5. FIG. 7 is a diagram showing an equivalent circuit and a schematic configuration of a PNPN type memory cell in a semiconductor memory device as a second embodiment of the present invention, and FIG. A schematic circuit diagram, FIG. 9 is a sectional view showing the configuration of the semiconductor memory device of FIG. 8, and FIG. 10 is a sectional view showing a modification of the PNPN type memory cell in the semiconductor memory device of FIG. 8. be. (Explanation of symbols), 11; P-type semiconductor substrate, 1
2; N ⁺ type buried layer, 13, 16, 17; N type region, 14, 15; P type region, 18, 19; isolation, 21; N type semiconductor substrate, 22; P ⁺
type buried layer, 23, 25, 26; N type region, 2
4; P-type region, 21'; P-type semiconductor substrate, 22';
N ⁺ type buried layer, 23', 25', 26'; P type region, 24'; N type region, ISO; isolation, SBD; Schottky barrier diode.

Claims (1)

[Claims] 1. A group of pairs of a first word line connected to a word line drive circuit and a second word line connected to a holding current source, a group of pairs of bit lines, and the word line. A memory cell is provided at each intersection of the word line pair and the bit line pair, the memory cell having a pair of PNPN type elements connected in parallel between the first and second word lines. In a semiconductor memory device in which a PNP (or NPN) transistor is a load transistor, and the NPN (or PNP) transistors are driving and information holding transistors whose bases and collectors are cross-connected to each other, the memory cell has a PNPN type. The element is formed on a buried layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type in a region surrounded by an isolation region, and the PNPN type element is formed on the buried layer. A first region of one conductivity type, a second region of an opposite conductivity type formed on the first region, a third region formed separately from each other on the second region, and a fourth region of one conductivity type. the third region is made of a semiconductor of one conductivity type or a metal having a shot barrier with the second region, the load transistor is composed of the buried layer, the first and second regions, and the driving transistor is made of a semiconductor of one conductivity type or a metal having a shot barrier with the second region; comprising a first, second and third region, and the information holding transistor is comprised of the first, second and third regions;
and a fourth region, the first, second, third, and fourth regions are each connected in a predetermined manner on the substrate, and the buried layer is connected to one of the first and second word lines. 1. A semiconductor memory device, characterized in that it is a wiring layer for. 2. The semiconductor memory device according to claim 1, wherein the buried layer is separated for each word line pair. 3 The one conductivity type is N type, and the opposite conductivity type is P type.
The semiconductor memory device according to claim 1, which is in the form of a semiconductor memory device. 4 The one conductivity type is P type, and the opposite conductivity type is N type.
The semiconductor memory device according to claim 1, which is in the form of a semiconductor memory device.