JPS63170956A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain the sufficiently high reliability even when the size of a memory cell is reduced by a method wherein a dielectric is installed between an N<+> buried layer at the memory cell and a substrate. CONSTITUTION:An N<+> type buried layer 2 is formed on a P-type substrate 1 ; a buried oxide film 10 is formed between the N<+> type buried layer 2 and the P-type substrate 1 only at a memory cell part M; an N<-> type epitaxial layer 3 is formed on the N<+> type buried layer 2; a P<+> type base diffused region 4 is formed on the N<-> type epitaxial layer 3. Because the N<+> buried collector region 2 at the memory cell part M is insulated electrically by the oxide film 18 which is formed between the P-type substrate 1 and the region, electric charges which are generated inside the oxide film 18 and the P-type substrate 1 out of the electric charges which are generated along the trace of an ionizing radiation are not collected in the N<+> buried collector region 2 when the memory cell part M is irradiated by the ionizing radiation such as alpha rays or the like. By this method, it is possible to secure sufficient allowance against a soft error due to the alpha rays or the line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a random access memory using bipolar transistors.

[Conventional technology]

Bipolar RAM (Random Access Memory) has been increasingly required to have higher integration and speed in recent years. BACKGROUND ART With advances in microfabrication technology for higher integration and speed, memory cells and the like have been miniaturized. However, as the size of transistors has become smaller, the amount of charge stored in memory cells has decreased, and soft errors caused by alpha rays have become a major problem.

This α-ray soft error is caused by α-rays emitted from trace amounts of uranium (U) and thorium (Th) contained in the package that houses the chip. α
The alpha rays emitted from uranium and thorium upon decay are 5
It has an energy of about M e V and a range in silicon of about 30 μm. When alpha rays enter a memory cell,
Electron-hole pairs are generated along the trajectory. In particular, when electron-hole pairs are induced near the collector-substrate junction,
Attracted by the electric field within the junction, the two holes reach the substrate and the electrons reach the collector region. This results in current flow from the collector to the substrate. For this reason, the potential of the collector of the off-side transistor of the pair of memory cell transistors forming the flip-flop decreases, causing information inversion of the memory cell.

A structural cross-sectional view of a bipolar transistor memory cell according to the prior art is shown in FIG. Further, FIG. 6 is an equivalent circuit diagram thereof.

In FIG. 5, an N-type buried layer 2 is formed on a P-type substrate 1, an N-type epitaxial layer 3 is formed on the N-type buried layer 2, and an N-type epitaxial layer 3 is formed on the N-type buried layer 2. epitaxial layer 3
A P medium-sized base diffusion region 4 is formed on the P medium-sized base diffusion region 4, and N medium-sized emitter regions 5a, 5 are formed in the P medium-sized base diffusion region 4.
b, 5c are formed. Also, 7.8 is an oxide film,
The elements are separated by an oxide film 8. Further, 6a to 6h are AI wirings, 6a is connected to the collector, 6b and 6d are connected to the emitter, 6c is connected to the base, and 6e is connected to the positive word line. 9 is a Schottky barrier diode, 10
is resistance.

Figure 6 shows a diode clamp type memory cell, which includes a multi-emitter transistor 11 for reading and writing stored information.
Load resistors 10a and 1 are connected to the collectors of a and 11b, respectively.
0b and Schottky barrier diodes 9a and 9b are connected in parallel to form a flip-flop. 6 is a positive side word line, and 12 is a negative side word line. These are connected to a constant current source (not shown) for memory retention, and draw a constant current from each memory cell. Further, 13a and 13b are bit lines, and multi-emitter transistors 11a and llb
is connected to one of the emitters.

Further, 14a and 14b are the junction capacitance 1icsBD of the Schottky barrier diode 9, 15a and 15b are the base-collector junction capacitance 11cTc of the multi-emitter transistors 11a and 11b, and 16a and 16b are the base-emink junction capacitance CTE of the multi-emitter transistors lla and llb.
, 17a, 17b are multi-emitter transistors 11a
, 11b is the collector-substrate junction capacitance CTS.

In FIG. 6, it is assumed that multi-emitter transistor 11a is off and transistor llb is on. That is, it is assumed that the collector node N of the multi-emitter transistor 11a is in the "H" state. In Figure 6,
The total capacity C attached to node N is: C= CTS+ C5BD + 4 CTC+ 2 C
Becomes TE. If the electron-hole pair charge induced near the collector-substrate junction in the memory cell by α rays is ΔQ, then the change in the collector potential of the off-side transistor lla is ΔQ/
It becomes C. Since the hold voltage VH of the memory cell is about 0.3V, information inversion of the memory cell will occur unless this potential change ΔV is suppressed to about 0.1V or less.

In order to reduce this potential change ΔV, conventional methods have been used, for example, Japanese Patent Application Laid-open No. 57-196563 and Japanese Patent Publication No. 59-53711. As described in Japanese Unexamined Patent Publication No. 56-4263, a method of increasing the capacitance C has been used.

[Problem that the invention seeks to solve]

Conventional semiconductor memory devices are configured as described above, so as the memory cell size decreases, the area of the junction of the memory cell, that is, the capacity, decreases, and the above method suffers from soft errors caused by alpha rays, etc. On the other hand, there was a problem in that it became difficult to secure a sufficient margin.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor memory device that has sufficiently high reliability even when the memory cell size is reduced. It is in.

[Means for solving problems]

In the semiconductor memory device according to the present invention, a dielectric material is provided between the N0 buried layer of the memory cell portion and the substrate.

[Effect]

In this invention, since the N0 buried collector region is insulated by the dielectric provided between the substrate and the substrate, P It is possible to prevent charges generated in the mold substrate from being collected in the N÷embedded collector region, and it is possible to ensure a sufficient margin against soft errors.

〔Example〕

A semiconductor memory device according to an embodiment of the present invention is shown in FIG. In FIG. 1, S indicated by a broken line is a transistor in the peripheral circuit section, and M is a memory cell section, which are formed on the same substrate. The equivalent circuit of the memory cell section M is the same as the conventional one, as shown in FIG.

In FIG. 1, an N medium-sized buried layer 2 is formed on a P-type substrate 1, and a buried oxide film 18 is formed only in a memory cell portion M between the N+ type buried layer 2 and the P-type substrate 1. formed, N
An N − type epitaxial layer 3 is formed on the medium-sized buried layer 2 , a P 10 type base diffusion region 4 is formed on the N − type epitaxial layer 3 , and a P 0 type base diffusion region 4 is formed on the N − type epitaxial layer 3 . N-type emitter regions 5a, 5b, and 5c are formed therein. 6a to 6h are AI wiring, 6a r6
f is the collector, 6c, 6g is the base, and 6b.

6d and 6h are connected to the emitter, and 6e is connected to the positive word line. Reference numeral 7.8 is an oxide film, particularly 8 is an oxide film for isolation between elements. In addition, 9 is a Shiritky barrier diode,
10 is a resistor serving as a load on the memory cell.

FIGS. 2, 3, and 4 are cross-sectional views for explaining a method of manufacturing the semiconductor memory device shown in FIG. 1, in which S represents a peripheral circuit portion and M represents a memory cell portion.

First, in FIGS. 2 and 3, an N medium-sized buried layer 2 is formed on a P-type substrate 1, and an oxide film 18 is formed between the N medium-sized buried layer 2 and the P-type substrate 1 by implanting oxygen ions. Formed by Since the portion on the buried oxide film 18 thus formed is polycrystalline, it is annealed. After this annealing, the fourth
As shown in the figure, an N- type epitaxial layer 3 is formed on the N medium-sized buried layer 2, and the subsequent formation is performed according to the conventional process, and finally the semiconductor memory device shown in FIG. 1 is obtained.

This example will be described in detail below.

As shown in FIG. 1, the N+ buried collector region 2 of the memory cell portion M has an oxide film 18 provided between it and the P type substrate l.
Therefore, when ionizing radiation such as alpha rays enters the memory cell part M, some of the charges generated along the trajectory of the ionizing radiation are generated in the oxide 311118 and the P-type substrate 1. Those that do are not collected in the N0 buried collector area 2.

For example, if an α ray with an energy of 5 M e V is incident on the memory cell part M, the range in St is about 30 μ.
m, and since the depth of the transistor in the memory cell portion M is about 2 μm, it is considered that most of the charge is generated in the P-type substrate l. Therefore, it is possible to reduce the rate of charge collection induced by ionizing radiation, thereby reducing changes in the potential of the collector of the off-side transistor of the memory cell, and providing sufficient margin against soft errors caused by alpha rays, etc. can be secured.

In the above embodiment, the P type substrate 1 and the N+buried N
2, the oxide film 18 is used as the dielectric between the oxide film 18 and the oxide film 18, but it may be made of any material as long as it is a dielectric. 1 and N
Needless to say, any method may be used to provide the space between the ten buried layers 2.

〔Effect of the invention〕

As described above, according to the present invention, since a dielectric is provided between the substrate and the N+ buried layer, it is possible to secure sufficient margin against soft errors caused by alpha rays, etc., and improve reliability. This has the effect of making it possible to obtain a semiconductor memory device with high performance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present invention, FIGS. 2, 3, and 4 are cross-sectional views for explaining its manufacturing method, and FIG. 5 is a conventional semiconductor memory device. A sectional view showing the device, and FIG. 6 is a circuit diagram showing a diode clamp type memory cell. 1 is a P-type substrate, 2 is an N-buried layer, 3 is an N-epitaxial layer, 4 is a P-type base diffusion region, and 5a. 5b and 5c are N0 emitter regions, 6a to 6h are AI
Wiring, 7.8 is an oxide film, 9 is a Schottky barrier diode, 10 is a resistor, and 18 is a buried oxide film. M is a memory cell section, and S is a peripheral circuit section. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A flip-flop type semiconductor memory device constituted by bipolar transistors, characterized in that a dielectric material is provided between the N^+ buried layer of the memory cell portion and the substrate. (2) The semiconductor memory device according to claim 1, wherein the dielectric is an oxide film. (3) The semiconductor memory device according to claim 2, wherein the oxide film is formed by implanting oxygen ions.