JPS63141364A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform a high speed operation and also firmly deal with the information inversion caused by alphs rays and the like by setting the film thickness of an N<-> type epitaxial layer so that the junction breakdown strength between collector and base can obtain specific values. CONSTITUTION:N<+> type buried layers 2 are formed on a P<-> type substrate 1 and an N<-> type epitaxial layer 3 is formed on the N<+> type buried layer 2. After forming the N<-> type epitaxial layer 3, a peripheral circuit part S is masked by a nitrided film 19 and only a memory cell part M is selectively oxidized and after that, it is etched. Such being the case, the film thickness of the N<-> type epitaxial layer is established so that the junction breakdown strength between collector and base can get 7-10 V. The junction breakdown strength BVCBO becomes smaller as the above layer makes the film thickness thinner. Further, a soft error rate becomes smaller as the junction breakdown strength BVCBO between collector and base of a memory cell transistor decreases and, especially its rate promptly becomes smaller when its BVCBO is less than 10 V. On the other hand, unless the BVCBO of the memory cell transistor is higher than 3 V, the operability and reliability of its transistor become a serious problem. Therefore, it is made clear that a numeric value of 7 V or higher of the BVCBO of memory cell transistor is necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a random access memory using bipolar transistors.

[Conventional technology]

In recent years, there has been an increasing demand for higher integration and higher speed for bipolar SRAMs. With advances in microfabrication technology for higher integration and higher speed, memory cells and the like have been miniaturized. However, as the size of transistors becomes smaller, the amount of charge stored in memory cells decreases, so soft errors caused by alpha rays have become a major problem. This α-ray soft error is caused by the trace amount of uranium (U) contained in the package that houses the chip.
It is caused by alpha rays emitted from thorium (Th). α rays emitted from uranium and thorium due to α decay have an energy of about 5 M e V and a range in silicon of about 30 μm. When α rays enter a memory cell, they generate electron-hole pairs along their range. In particular, when electron-hole pairs are induced in the vicinity of the collector-substrate junction, the holes reach the substrate and the electrons reach the collector region, attracted by the electric field within the junction. This results in current flow from the collector to the substrate. Therefore, the collector potential of the off-side transistor of the pair of memory cell transistors forming the flip-flop decreases,
Information reversal in memory cells is likely to occur.

FIG. 6 shows a structural cross-section of a bipolar transistor memory cell according to the prior art. FIG. 7 is its equivalent circuit diagram. In FIG. 6, an N-type buried layer 2 is formed on a P- type substrate 1, an N- type epitaxial layer 3 is formed on the N+ type buried layer 2, and an N- type buried layer 2 is formed on the N+ type buried layer 2. A P" type base diffusion region 4 is formed on the epitaxial layer 3, and an N9 type emitter region 5 is formed in the P+ type base diffusion region 4.
a.

5b is formed. Further, 7 and 8 are oxide films, and the elements are separated by the oxide film 8. Further, 6a to 6e are Al wirings, the Al wiring 6a is connected to the collector, and the Al wiring 6a is connected to the collector.
b, 6d are the emitters, Al wiring 6c is the base, Al
The wiring 6e is connected to the positive word line. 9 is a Schottky barrier diode, and 10 is a resistor.

The device shown in FIG. 7 is a diode clamp type memory cell, in which load resistors 10a, 10b and a Schottky barrier diode 9a are connected to the respective collectors of multi-emitter transistors 113 and 11b for reading and writing stored information.
9b are connected in parallel to form a flip-flop. 6 is a positive side word line, and 2 is a negative side word line. These are connected to a constant current source (not shown) for memory retention, and draw a constant current from each memory cell. Also 13a
, 13b is a bit line, and multi-emitter transistor l
It is connected to one of the emitters of la and llb. 14a and 14b are the junction capacitances of the Schottky barrier diode 9 (capacitance value = Csmn), 15a and 15b are the base-collector junction capacitances of the multi-emitter transistors lla and llb (capacitance value "" Cyc), and 16a and 16b are the multi-emitter transistors. Pace-emitter junction capacitance of transistors lla and llb (capacitance value = Cti), i'ya, 17
b is the junction capacitance (hereinafter referred to as "collector-substrate junction capacitance") between the collector and substrate of the multi-emitter transistors lla and llb (capacitance value=Cts).

Next, the operation of the conventional memory cell will be explained. In FIG. 7, multi-emitter transistor lla is off,
Assume that multi-emitter transistor llb is on. That is, it is assumed that the collector node N of the multi-emitter transistor lla is in the "H" state. When the α rays enter the memory cell, as described above, the collector potential of the node N in the "H" state decreases, making it easier for information inversion to occur. Here, the total capacitance value C attached to the above node N is C=Cys+Cs! 10+A Ctc+2 Crt
becomes. If the electron-hole pair charge generated near the collector-substrate junction in the memory cell by α rays is ΔQ, then the change Δ■ in the collector potential of the off-side transistor ILa is ΔQ/
It becomes C. Since the hold voltage (1) of the memory cell is approximately 0.3V, unless this potential change ΔV is suppressed to 0.1V or less, information in the memory cell will be inverted.

In order to reduce the potential change ΔV, the capacitance value C may be increased. Junction capacitance 1 with capacitance value C310
Junction capacitance 15a, 15b between 4a, 14b and capacitance value CA
is connected in parallel to the load resistances 10a and 10b of the memory cells, so it plays the role of a speed-up capacitor. Since the capacitance value CtC of the junction capacitances 15a and 15b is determined by a factor of 4 due to the Miller effect, it can be said that increasing this CTC increases the resistance to information inversion caused by α rays.

In FIG. 6, the junction capacitances 15a and 15b are the PN junction capacitances of the N-type epitaxial layer 3 and the P-type base diffusion region 4, and therefore
The capacitance CTCO value changes depending on the film thickness. Therefore, the collector-base junction breakdown voltage B■. . It also changes depending on the film thickness. In the prior art, the N-type epitaxial layer 3 is
The memory cell portion and the peripheral circuit portion are formed at the same time and controlled to have the same film thickness, and therefore the collector-base junction breakdown voltage BVcgo of the memory cell portion and the peripheral circuit portion is also controlled to the same value.

[Problem that the invention seeks to solve]

Since the conventional semiconductor memory device is configured as described above, for example, if the N'' type epitaxial layer 3 is made thicker,
The base-collector junction capacitance value CTC of the transistors in the memory cell section and the peripheral circuit section is reduced, thus enabling high-speed operation, and increasing the collector-base junction breakdown voltage B.
VCIIG also increases, but on the other hand, the capacitance value is small, so α
Information in the memory cell is more likely to be inverted due to lines or the like.

On the other hand, if the thickness of the N-type epitaxial layer 3 is reduced,
As the capacitance value CtC increases, information inversion in the memory cell becomes less likely to occur, but on the other hand, high-speed operation cannot be expected, and the collector-base junction breakdown voltage BVc++.

It also had the disadvantage of being smaller.

The present invention has been made in view of these points, and an object thereof is to obtain a semiconductor memory device that enables high-speed operation and is highly reliable.

[Means for solving problems]

In order to achieve such an object, the present invention provides a method for connecting the collector of the N- type epitaxial layer, the base of the P+ type diffusion region, and the N- type epitaxial layer.
In a flip-flop type semiconductor memory device configured with a bipolar transistor having a +-type emitter, the junction breakdown voltage between the collector and base is 7 to 7.
The thickness of the N-type epitaxial layer is set so that it becomes lOv.

[Effect]

In the present invention, the semiconductor memory device is capable of high-speed operation and is resistant to information inversion caused by alpha rays and the like.

〔Example〕

An embodiment of a semiconductor memory device according to the present invention is shown in FIG. In FIG. 1, the dotted line S indicates a transistor in the peripheral circuit section, and the dotted line M indicates a memory cell section, which are formed on the same substrate. The circuitry of the memory cell section M is the same as the conventional one, as shown in FIG.

In FIG. 1, an N-type buried layer 2 is formed on a P-type substrate 1, an N-type epitaxial layer 3 is formed on the N-type buried layer 2, and an N-type epitaxial layer 3 is formed on the N-type epitaxial layer 3. A P" type base diffusion region 4 is formed, and a P° type base diffusion region 4 is formed.
N emitter regions 5a, 5b, and 5c are formed therein. 6a to 6h are An wiring, Af wiring 6a, 6f
is the collector, A/wiring 6c, 6g is the base, Al wiring &16b.

6d and 6h are connected to the emitters, and the Al wiring 6e is connected to the positive word line. 7.8 is an oxide film, and the peripheral circuit section S and the memory cell section M are separated by the oxide film 8. Also,
9 is a Schottky barrier diode, and 10 is a resistor serving as a load for the memory cell.

FIGS. 2 and 3 are cross-sectional views for explaining a method of manufacturing the device shown in FIG. 1, in which S represents a peripheral circuit portion and M represents a memory cell portion. First, in Fig. 2, N
A buried layer 2 is formed, and an N-type epitaxial layer 3 is formed on the buried layer 2. After forming the N-type epitaxial layer 3, the peripheral circuit section S is masked with a nitride film 19, and only the memory cell section M is selectively oxidized, and then etched to form the memory cell section M, as shown in FIG.
The thickness of the N-type epitaxial layer 3 can be made thinner than that of the peripheral circuit section S. Thereafter, the process is performed according to the prior art, and the device shown in FIG. 1 is finally obtained.

FIG. 4 shows the relationship between the collector-base junction breakdown voltage BVc++o and the soft error rate of the memory cell transistor obtained from this device. The BvcIloO value is a value obtained by changing the film thickness of N-type epitaxial N3,
The value of BVC10 decreases as the film thickness decreases.

From FIG. 4, the collector-base junction breakdown voltage BVc1. .

The soft error rate decreases as the voltage decreases, and in particular, the soft error rate decreases rapidly below B VC [10=10 V. By thinning the N-type epitaxial layer 3 of the memory cell portion M, the collector-base junction breakdown voltage BVc of the memory cell transistor can be increased. This is because the value CTC of the base-collector junction capacitance 15a, 15b of the memory cell transistor becomes large.

FIG. 5 shows the relationship between the collector-base junction breakdown voltage BVcao and the collector-emitter junction breakdown voltage BVCE'0 of the memory cell transistor obtained from this device. Here, if the BVcEo of the memory cell transistor is not 3 or more, problems will arise in terms of operation and reliability. Therefore,
From FIG. 5, it can be seen that the BVCI 10 of the memory cell transistor needs to be 7V or more. Therefore, in order to obtain a semiconductor memory device that is resistant to information inversion caused by alpha rays and has high reliability, it is necessary to
cw.

It is necessary to set the voltage to about 7 to 10V.

On the other hand, the peripheral circuit S is not concerned with information inversion caused by α rays or the like, and therefore it is desirable that the collector-base junction breakdown voltage BV-0 of the transistor in the peripheral circuit section S be large. As shown in FIG. 3, the N-type epitaxial layer 3 of the peripheral circuit section S
is thicker than the N-type epitaxial layer 3 of the memory cell section M, and therefore the collector-base junction breakdown voltage BVcmo of the transistor in the peripheral circuit section S is large, and the base-collector junction capacitance value C? . can be expected to be smaller and faster.

Furthermore, by adopting the structure of the semiconductor memory device shown in FIG. 1, the hem of the memory cell transistor becomes large.
Therefore, the potential drop on the rHJ side of the memory cell becomes smaller,
Another advantage is that a decrease in the margin of memory cell amplitude can be prevented.

An example of the manufacturing method of this device is shown in FIGS. 2 and 3, but when comparing the collector-base junction breakdown voltage BVCI10 of the transistor in the memory cell section M with the BVI:IQ of the transistor in the peripheral circuit section S, BVc of the transistor in the memory cell section M is made smaller. Needless to say, any method may be used as long as it reduces the value to 7 to 10 ■.

〔Effect of the invention〕

As explained above, in the present invention, by setting the collector-base junction breakdown voltage of the memory cell part to 7 to 10V, only the base-collector junction capacitance value of the memory cell part can be increased. , it is possible to obtain a semiconductor memory device that operates at high speed and has high reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor memory device according to the present invention, FIGS. 2 and 3 are cross-sectional views for explaining a method of manufacturing the device shown in FIG. 1, and FIG. A graph showing the relationship between the collector-base junction breakdown voltage and the soft error rate of the transistor in the memory cell section of the device shown in the figure. - A graph showing the relationship with the inter-emitter junction withstand voltage; FIG. 6 is a cross-sectional view of a conventional semiconductor memory device; and FIG. 7 is an equivalent circuit diagram thereof. M...Memory cell section, S...Peripheral circuit section, ■...
P-...N-type part transmitter region 6a to 6h...Al
Wiring, 7.8... Oxide film, 9... Schottky barrier diode, 10... Resistor.

Claims (1)

[Claims] In a flip-flop type semiconductor memory device constituted by a bipolar transistor having a collector of an N^- type epitaxial layer, a base of a P^+ type diffusion region, and an emitter of an N^+ type region, between the collector and the base. The above N^-
A semiconductor memory device characterized in that the film thickness of a type epitaxial layer is set.