JPS61135159A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a capacitor having large capacitance while obtaining a semiconductor circuit the area of which is reduced, by shaping the capacitor and an NPN or PNP transistor into one isolation wall. CONSTITUTION:When the forward bias of a junction between a collector and a base in an NPN transistor 15 is prevented in a semiconductor integrated circuit, N<+> diffusion layers 24 and an N type epitaxial layer 20 have the same potential, and two capacitors of a capacitor 14a by both diffusion layers 24 and a capacitor 14b by a P type diffusion layer 23 and the N type epitaxial layer 20 are formed. The two capacitors 14a, 14b are connected in parallel, and capacitance per a unit area synthesizing these capacitors is increased to twice or more. The N<+> diffusion layers 24 are connected electrically to the N type epitaxial layer 20, and the P type diffusion layer 23 functions as a base in the NPN transistor. Accordingly, the NPN transistor 15 and the capacitors 14a, 14b are shaped in one confined isolation walls 21, 22, thus extremely reducing the occupying areas of several element consisting of a semiconductor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of practical application] The present invention relates to a semiconductor integrated circuit in which a transistor and a capacitor are provided within one separation wall.

[Conventional technology]

FIG. 4 is a cross-sectional view of a conventional semiconductor integrated circuit.

FIG. 5 shows its equivalent circuit. In Diagram 4-1 Series 5, numeral 1 is a P-type silicon single crystal substrate (hereinafter referred to as a P-type substrate), and numeral 21 is a Nm layer formed on this P-type substrate 1.
4.5 is an Nff1 pittaxial layer, 6 and 7.8 are P-type separation walls, and 9.10 is a P layer formed in the Nff1 pittaxial layers 4 and 5.
M1 diffusion layer, 11.13 is Walill! PIIi diffusion layer! 1, 1 is a Nmm impurity-concentrated N0 diffusion layer formed in stt stt, 12 is a N11 impurity-concentrated N0 diffusion layer formed in the N type epitaxial layer 5, and 4 is a capacitor, which is a 1tlle pH diffusion layer. M9 is used as one 11L pole, and N0 diffusion layer 11Y is used as the other electrode, which is formed at the junction between PM1 diffusion layer 9 and N0 diffusion layer 11. 15 is NPN) Kunjista, ltI N ten diffusion layer 12 Y collector, P light diffusion N 10 Y Heath, N ten diffusion layer 1
3't' emitter. 16 is a terminal to which the collector terminal of the NPN transistor 15 and one terminal of the capacitor 14 are connected; 1T is ni the NPN transistor 1;
50 is a terminal to which the other terminal of the capacitor 14 is connected, and 18 is the emitter terminal of the NPN Kunister 15.

Since the conventional semiconductor integrated circuit is configured as shown in 5 above, if the junction between the NPN/F/V vector and base of the raster 15 is not biased in the forward direction,
A depletion layer is formed at the PN junction formed by the P-type diffusion layer 9 and the N0 diffusion layer 11, and the width of this depletion layer and the silicon i1
! A capacitor 14 whose capacitance value is determined by the voltage ratio is formed between the terminals 16 and 17.

[Problem that the invention seeks to solve]

Since the capacitance per unit area of the conventional PN junction capacitor 14 as described above is small, there is a problem in that a large surface area is required in the semiconductor integrated circuit in order to secure a meaningful capacitance value in the circuit configuration. there were.

This invention was made to solve this problem. It is an object of the present invention to obtain a semiconductor integrated opening 18' whose area is reduced.

[Means for solving problems]

The semiconductor integrated circuit according to the present invention includes a first P-type diffusion layer provided on an N epitaxial layer formed on a P-type substrate,
1cN+diffusion Nw is provided so as to span this first P-base diffusion layer and the N-type epitaxial layer.

A capacitor formed at the junction between the N-type epitaxial layer and the first P-type diffusion layer, and at the junction between the N-type epitaxial layer and the first Pf-type diffusion layer.

An N-type diffusion layer is provided in the first P-type diffusion layer, or a second P-diffusion layer is provided in the N-type epitaxial layer to form an NPN or PNP transistor, and the capacitor is and n' are provided within one separation wall consisting of an NPN or PNP transistor and a P-type substrate.

[Effect]

In this invention, an NPN or PNP transistor and a capacitor are provided within one closed separation wall, and this capacitor is a capacitor formed by joining a first P-type diffusion layer and an N+ diffusion layer. A capacitor is also formed by the junction of the first P-type diffusion layer and the N-type epitaxial layer.

As a result, the two capacitors are connected in parallel and act as a large capacitor.

〔Example〕

FIG. 1 is a sectional view showing the structure of a semiconductor integrated circuit according to an embodiment of the present invention, and reference numerals 16 to 18 are shown in FIG.
It shows the same or equivalent parts as FIG. 5. In FIG. 1, reference numeral 19 indicates an N-doped buried layer with a high N-type impurity concentration formed on the PW substrate 1, 20 indicates an N-type epitaxial layer,
21 and 22 are P-type separation walls, 23 is a first P-type diffusion layer formed in the N-layer epitaxial layer 20, and 24 is the N-type epitaxial layer 20 and the first P-diffusion layer 2.
This is an N1 diffusion layer formed over three layers.

In the semiconductor integrated circuit configured as described above, N
If the collector paste junction of the PN transistor 15 is not forward biased, the N+ diffusion layer 24 and the N-type epitaxial layer 20 have the same potential t, so the first P diffusion layer 23 and PN due to N10 diffusion layer 24
A depletion layer is formed at the junction and at the PN junction between the first Pf diffusion layer 23 and the N type epitaxial layer 2G. , two capacitors 14a and 14b are formed, the first P diffusion layer 23 and the capacitor 14b formed by the N epitaxial layer 20, but these two capacitors 14a and 14b are connected in parallel, and the first P diffusion diffusion layer When compared with only the capacitor 14a consisting of the layer 23 and the N+ diffusion layer 24, these two capacitors 14a, 14
bY match.

The capacity per unit area thus achieved is more than doubled. Also,
The N+ diffusion layer 24 is electrically connected to the N-type epitaxial layer 20 which is the collector of the NPN transistor 15, and the first P diffusion layer 23 acts as the base of the NPN transistor (therefore, the NPN transistor 15 and the capacitor 14a , 14b can be formed within one closed separation wall 21, 22, and the area occupied by each semiconductor element can be made extremely small.

FIG. 2 is a sectional view showing another embodiment of a PNP transistor, in which numerals 20 to 24 indicate the same or equivalent parts as in FIG.
A second P-type diffusion layer 26 formed in 0 is based on the N-type epitaxial layer 20Y, and is formed in the first P-type diffusion layer 2
3'lk: IV Kuta.

This is a PNP transistor with the emitter of the second P type diffusion layer 21'. FIG. 3 is an equivalent circuit diagram of FIG. 3112. In the embodiment of the second cause, if the contactor-space junction of the PNP transistor 26 is not forward biased, the N1 diffusion layer 24 and the Nff1 epitaxial layer 20 have the same potential t. P diffusion layer 2
A depletion layer is formed in the fusion region formed by the P-3 and N+ diffusion layers 24 and the PN junction formed by the first P-diffusion layer 23 and the N-temperature epitaxial layer 20, respectively. There are two capacitors 14a: a capacitor 14& formed by the first diffusion layer 24, and a capacitor 14b formed by the first PM diffusion layer 23 and the Nll epitaxial layer 2◎.

14b is formed. Further, 27 is a terminal to which the pace of this PNP l-transistor 26 and the terminal of the capacitor 14m are connected, 2B is a terminal to which the connoft of the PNP transistor 26 and the terminal of the capacitor 14b are connected;
9 is the emitter terminal of the PNP transistor 26.

〔Effect of the invention〕

As explained above, in this invention, a first P-type diffusion layer is provided on an N-type epitaxial layer, and an N+ diffusion layer is provided so as to straddle this first P-type diffusion layer and the N-type epitaxial layer. A capacitor is formed at the junction between the N-base diffusion layer and the first Pf-type diffusion layer, and at the junction between the M-base N-base epitaxial layer and the first Pf-type diffusion layer, and the first P-base diffusion layer. An N diffusion layer is provided within the diffusion layer, or the N
Since the structure is such that an NPN or PNP transistor is formed by providing a Pf type diffusion layer of kg2 in the type epitaxial layer, and provided within one separation wall consisting of the capacitor, the transistor, and the P temperature semiconductor substrate, This has the effect that semiconductor integrated circuits can be made extremely small and inexpensive.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor integrated circuit according to one embodiment of the present invention IPIIVC, FIG. 2 is a sectional view showing the structure of another embodiment of the invention, and FIG. 3 is an equivalent circuit diagram of FIG. 2. ,
FIG. 4 is a sectional view showing the structure of a conventional semiconductor integrated circuit, and FIG. 5 is an equivalent circuit diagram of FIG. 4. In the figure, 1 is a P-type substrate, and 13 is an N+ diffusion layer. 14a and 14b are 27 capacitors, 15 is NPN): 7 transistors, 1S is an N0 buried layer, 20 is an NM epitaxial layer, 21 and 22 are separation walls, 23 is a P type diffusion layer, 24 is an N0 diffusion layer, 25 is a P-world diffusion layer, and 26 is a PNPI-transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] An N^+ buried layer and an N-type epitaxial layer are formed on a P-type semiconductor substrate, and a first P layer is formed on this N-type epitaxial layer.
A type diffusion layer is provided, an N^+ diffusion layer is provided so as to straddle the first P-type diffusion layer and the N-type epitaxial layer, and a junction between the N^+ diffusion layer and the first P-type diffusion layer is provided. and a capacitor formed at the junction of the N-type epitaxial layer and the first P-type diffusion layer, and an N^+ diffusion layer provided within the first P-type diffusion layer or a capacitor formed within the N-type epitaxial layer. A second P-type diffusion layer is provided to form an NPN or PNP transistor, and the capacitor and the NPN or PNP transistor are provided within one separation wall made of the P-type semiconductor substrate. Semiconductor integrated circuit.