JPS6262066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device equipped with a flip-flop type memory cell such as an ECL (emitter coupled logic) type memory cell.

In this type of device that has been proposed in the past, alpha rays emitted from an alpha ray source such as uranium (U) or thorium (Th) contained in a package enter a memory cell and generate electron-hole pairs. This has the disadvantage of inverting the states of the flip-flops constituting the memory cells and destroying the memory contents.

An object of the present invention is to provide a novel semiconductor memory device that can reduce such inconveniences.

In the device according to the present invention, in each multi-emitter transistor constituting a flip-flop, the capacitance between the second emitter and the base connected to the word line is smaller than the capacitance between the first emitter and the base connected to the digital line. It is characterized by its large size, and the embodiments shown in the accompanying drawings will be described in detail below.

FIG. 1 is an equivalent circuit diagram of an ECL type memory cell according to an embodiment of the present invention, where Q ₁ and Q ₂ are multi-emitter transistors, R ₁ and R ₂ are load resistors,
D ₁ and D ₂ are clamp diodes, UW is the upper word line, LW is the lower word line, DG ₁ and DG ₂ are the digit lines, C ₁ is the first emitter-base capacitance of each transistor, and C ₂ is the first emitter-base capacitance of each transistor. This is the capacitance between the second emitter and the base.

According to the present invention, the capacitor C ₂ is formed larger than the capacitor C ₁ in FIG. 1. That is, the capacity
Capacitor C ₁ normally determines the operating speed of the cell, so it is made as small as possible to increase the speed, but capacitor C ₂ has a small effect on operating speed, so it is made larger than C ₁ . As a result, the response of each transistor to noise caused by α-ray irradiation becomes slow, and flip-flop state reversal becomes less likely to occur. Therefore, destruction of memory contents due to alpha rays and other physical factors can be minimized.

FIG. 2 shows a specific integrated structure of the circuit portion A in FIG. 10 is a semiconductor substrate made of P-type silicon, in which an N ⁺ type buried layer 11 is formed. An N type epitaxial layer 12 is formed on the N ⁺ type buried layer 11, and a portion of this N type epitaxial layer 12 is converted into a field SiO ₂ film 13. N ⁺ type buried layer 1
The N ⁺ type region 14 connected to 1 is a collector contact region.

A transistor is formed on the surface of the N-type epitaxial layer 12 surrounded by the field SiO ₂ film 13.
Q ₂ , a resistor R ₁ and a diode D ₂ are formed, and 15 is a P-type base region of the transistor Q ₂ ,
16 is a P-type anode region of the diode _D2 , 17 is a P-type region constituting the resistor _R1 , and 18 and 19 are N ⁺ -type emitter regions of the transistor _Q2 .

The emitter region 18 is formed to have a wider area than the emitter region 19 in order to satisfy the above-mentioned condition of C ₁ <C ₂ .For example, the region 18 has a width of 10 μm square, and the region 19 has a width of 3 μm square. (Note that conventionally, regions 18 and 19 were formed to have the same size). To this end, it is sufficient to simply define the mask openings for emitter diffusion (or ion implantation) so that one opening is larger than the other.

A configuration similar to that described above is also adopted for the remaining half of the flip-flop components (ie, transistor Q ₁ , diode D ₁ , and resistor R ₂ ).

Therefore, according to the above configuration, the capacitance C ₂ can be made larger than the capacitance C ₁ by the emitter-base junction capacitance corresponding to the increase in area of the emitter region 18 than the emitter region 19.

In the above example, due to the increase in junction capacitance, C ₁ <
Although the condition of C ₂ is satisfied, the capacitance C ₁ ,
Since C ₂ is not a function of only the junction capacitance but a function of the sum of the junction capacitance and the diffusion capacitance, it is also possible to employ a diffusion capacitance increasing means separately from or together with the above-described junction capacitance increasing means. Specifically, as shown by the broken line 15A in FIG. 2, the base width may be made larger below the emitter region 18 than below the emitter region 19. A relatively deep base portion may be formed below region 18 by diffusion or ion implantation prior to formation.

As described above, according to the present invention, since the junction capacitance and/or the diffusion capacitance are formed so as to satisfy the condition of C ₁ <C ₂ , information reversal in the memory cell is less likely to occur, and malfunctions caused by α-ray irradiation etc. A memory cell with high resistance to (so-called soft errors) can be realized. Furthermore, there is little decrease in operating speed due to an increase in C ₂ , and access times can be expected to be almost the same as in the past.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of an ECL type memory cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a substrate showing an integrated structure of circuit portion A in FIG. Q ₁ , Q ₂ ... transistor for flip-flop configuration, C ₁ ... first emitter-base capacitance, C ₂ ... second emitter-base capacitance.

Claims (1)

[Claims] 1. In each multi-emitter transistor constituting a flip-flop type memory cell, the capacitance between the second emitter connected to the word line and the base is formed to be larger than the capacitance between the first emitter connected to the digital line and the base. A semiconductor memory device characterized by: