JPS63296265A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress the flowing of electrons into a substrate so as to prevent memory information from being broken, by forming a charge capturing region in the vicinity of a dicing line which is formed of an impurity diffusion region where an internal substrate bias potential is applied. CONSTITUTION:An electron capturing region 30 is divided into an insulating layer 50 and an N<+> layer 20 which forms a dicing line 2. An N<+> layer 32 and P<+> layers 33, 34 are formed inside an N<-> well 31 on a P<-> substrate, and a poly-Si gate 35 is formed on an insulating thin film 35, so that an RET is composed. A positive voltage V is applied to the N<+> layer 32 and the P<+> layer 33. A memory cell 40 is formed inside the region 30. A substrate bias potential is applied through a parasitic diode 8 formed between the N<+> layer 20 and the P type substrate. When a memory circuit is operated to change the substrate bias voltage and electrons generated are implanted into the substrate through the parasitic element 8, all the electrons are captured by the N<-> layer 31 biased positively through the N<+> layer 32 to which the positive voltage V is applied and so they cannot reach the memory cell 40, and hence have no effects on data held in the cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a semiconductor memory device, and particularly to a semiconductor memory device in which electrons are injected into a semiconductor substrate due to fluctuations in a substrate bias potential applied to a semiconductor substrate, and the generated electrons are generated by the injected electrons. The present invention relates to a configuration of an electron absorption region for preventing malfunction of internal circuits.

[Prior Art] FIG. 3 is a schematic plan view showing the structure of a semiconductor wafer on which a semiconductor memory device is formed. In FIG. 3, a plurality of semiconductor memory devices 3 are arranged on the surface of a semiconductor wafer 1, the area of which is defined by dicing lines 2. As shown in FIG. The semiconductor memory devices 3 formed on the semiconductor wafer 1 all have the same configuration, and after forming internal circuits such as memory elements, each semiconductor memory device 3 is cut along the dicing line 2 and separated into individual pieces. It is divided into semiconductor memory devices 3.

FIG. 4 is a schematic plan view showing the configuration of the dicing line. As shown in FIG. 4, when the semiconductor wafer 1 has a P-type conductivity type, the dicing line 2 is formed by an N-type impurity diffusion region formed on the surface of the semiconductor wafer 2. Each region surrounded by the dicing line 2 defines a so-called semiconductor chip region, and internal circuits such as semiconductor memory elements are formed in this chip region to constitute one semiconductor memory device. At this time, the N-type impurity diffusion region forming the dicing line 2 is cut so as to remain around the semiconductor chips constituting each semiconductor memory device.

Normally, semiconductor memory devices include: ■ Preventing electrons from being injected into the P-type semiconductor substrate; ■ Substrate effect constant of threshold voltage of MOS (metal-oxide-semiconductor) transistors used in semiconductor memory devices; ■ Between each node of the internal circuit of a semiconductor memory device (N
The P-type semiconductor substrate is brought to a negative potential with the aim of increasing circuit speed and reducing power consumption by reducing the PN junction capacitance formed between the P-type impurity diffusion layer and the P-type semiconductor substrate. A substrate bias generation circuit is provided to maintain the voltage.

FIG. 5 is a diagram showing an example of the configuration of a conventionally used substrate bias generation circuit. In FIG. 5, the substrate bias generation circuit includes a charge pump circuit 4 configured of, for example, a free-running oscillation circuit that receives a voltage from an operating power supply voltage VCC and further boosts the voltage, and a capacitor that transmits the output of the charge pump circuit 4 through capacitive coupling. 5, a diode-connected MOS) provided between the capacitance 5 output and the ground potential, a diode-connected MOS) connected to the connection point A between the capacitance 5 and the MOS) transistor, and a MOS ) A diode 8 is connected between a common connection point B between the gate of the Ranjistaf and the other conductive terminal and the ground potential.

The gate and one conductive terminal of the transistor (MOS) are connected to the electrode of the capacitor 5, and the other conductive terminal is connected to the ground potential. The MOS transistor 7 has one conductive terminal connected to the electrode of the capacitance 5,
Its gate and the other conductive terminal are commonly connected. The diode 8 has its cathode connected to a common connection point B between the gate of the MOS transistor and the other conductive terminal, and its anode connected to the ground potential.

FIG. 6 is a schematic cross-sectional view showing the structure of a portion of the substrate bias generation circuit shown in FIG. 5 surrounded by a broken line. In FIG. 6, the MOS transistor 7 is connected to the P-type semiconductor substrate 1.
N+ type impurity diffusion region 7 formed in a predetermined region of the 0 surface
1.72 and an extremely thin oxide film 73 formed on the charge transfer region between the impurity diffusion regions 71.72, and a gate electrode 74 made of polysilicon, for example, formed on the thin oxide film 73. Ru. The diode 8 is parasitically formed between the N type impurity diffusion region 20 forming the dicing line 2 and the P − type semiconductor substrate 10 . M
(OS) The connection between the Langstaff and the diode 8 is made by a conductor wiring 75 made of aluminum, for example. A thick oxide film 76 is provided between the impurity diffusion region 72 of the Rangistaf (MOS) and the N-type impurity diffusion region 20 serving as the dicing line constituting the diode 8 in order to prevent electrical conduction between the impurity diffusion regions. MOS transistor 7 is also provided with an insulating film 77 for preventing electrical conduction between the respective electrodes. The conductor wiring 75 is a MOS) gate electrode 74 of Langistuf, the N+ type impurity diffusion region 72, and the N+ type impurity diffusion region 2 of the diode 8.
0 is connected, and the internal substrate bias voltage is output to the outside via the output terminal 9. The internal substrate bias voltage taken out via this output terminal 9 is applied to the back surface of the semiconductor substrate 10 in order to prevent fluctuations in the substrate bias potential. Next, the operation will be explained.

MOS) Let the threshold voltage of the transistor be vth, and let the peak voltage of the signal output by the charge pump circuit 4 be Vp.
shall be. At this time, node A (MOS transistor 6
The voltages at the ground terminal and the conductive terminal opposite to
-Vp.

When the voltage at node A becomes negative, electrons flow into node B (impurity diffusion region 72) via the MOS transistor, and a negative substrate bias potential VllB is generated. At this time, if the forward voltage drop of the parasitic diode 8 is Vf, then the voltage drop across the P-semiconductor substrate 10 via the parasitic diode 8 is
A negative potential of v[1a+Vf will be applied to.

[Problems to be Solved by the Invention] The conventional substrate bias generation circuit is configured as described above, and the internal substrate bias potential VIIB is equal to the threshold voltage vth of the charge pump circuit 4 output and the MOS transistor 6.7. It is a constant value defined by .

In a normal semiconductor memory device, the signal lines of the internal circuit are
It is constructed using a conductive wiring layer formed on a semiconductor substrate via an insulating film and an N medium impurity diffusion layer formed on the surface of the semiconductor substrate. Therefore, a large coupling capacitance exists between the signal line and the semiconductor substrate.

At this time, when the internal circuit operates and the signal line charges and discharges, the substrate potential changes via this coupling capacitance.

Furthermore, when a semiconductor memory device is operated at a high voltage, a hole current flows to the semiconductor substrate due to the impact ionization phenomenon of the MOS transistors that constitute the internal circuit of the semiconductor memory device, thereby reducing the substrate bias potential applied to the semiconductor substrate. The absolute value becomes smaller. In such a case, with respect to the parasitic diode 8 formed between the semiconductor substrate 10 and the dicing line 2 consisting of the internal substrate bias generation circuit and the N1 impurity diffusion region 20 maintained at the internal substrate bias potential Vaa, the semiconductor substrate 10 The internal substrate bias potential VflB generated by the substrate bias generation circuit due to potential fluctuations in
A voltage higher than the forward drop voltage Vf of the diode 8 is momentarily applied between the diode 8 and the diode 8, and a forward current flows through the diode 8. As a result, electrons are injected into the semiconductor substrate 10 via the diode 8. Ru. The absolute value of the internal substrate bias potential Vaa increases as the semiconductor memory device is operated at a higher voltage. The potential difference between becomes large. As a result, the forward current flowing through the diode 8 increases, and the amount of electrons injected into the semiconductor substrate 10 increases accordingly. Usually, memory cells including N-channel MOS transistors are arranged near the dicing line 2 (N medium-sized impurity diffusion region 20). In such a case, electrons injected into the semiconductor substrate 10 through the N+ type impurity diffusion layer 20 constituting the dicing line 2 are injected into the capacitor portion of the memory cell in the vicinity, and the data held by the memory cell is There were problems such as the memory being destroyed and the memory not functioning properly.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of conventional semiconductor memory devices, and to provide a structure between a dicing line consisting of an N+ type impurity diffusion region maintained at the internal substrate bias potential Vaa level and a P- type semiconductor substrate. An object of the present invention is to provide a semiconductor memory device including an electron trapping region for preventing injection of electrons into a semiconductor substrate caused by forward current flowing through a parasitic diode formed.

[Means for Solving the Problems] A semiconductor memory device according to the present invention is provided with a charge trapping region near a dicing line consisting of an impurity diffusion region to which an internal substrate bias potential is applied.

Preferably, the charge trapping region includes an N-type impurity diffusion region formed on the surface of the P-type semiconductor substrate electrically separated from the dicing line and biased to a positive potential near the dicing line consisting of the N+-type impurity diffusion region. configured using

[Function] In the semiconductor memory device of the present invention, a charge trapping region is provided near the dicing line to trap charges injected from the dicing line to the semiconductor substrate, so that the bias potential applied to the semiconductor substrate fluctuates. death,
Even if a forward current flows through a parasitic diode formed between the impurity diffusion region and the semiconductor substrate that make up the dicing line and charges are injected into the semiconductor substrate, they are all absorbed by the charge trapping region. Stable memory operation can be ensured without causing the injected charges to reach memory cells formed nearby and destroying memory cell information.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, in the following description, parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a plan view showing a schematic configuration of a semiconductor memory device according to the present invention. In FIG. 1, a semiconductor memory device 3 according to the present invention includes a dicing line 2 made of an N+ type impurity diffusion region, an electron capture region 30 provided along the dicing line 2 near the dicing line 2, and a memory for storing information. A cell 40 is provided. Peripheral circuits of the semiconductor memory device, such as a decoder circuit and a buffer circuit for decoding address signals, are formed using the electron capture region 30 as a part of the region.

FIG. 2 is a diagram showing a schematic cross-sectional structure taken along the line A--A shown in FIG. In Figure 2, electron capture region 3
0 is electrically isolated from the N+ type impurity diffusion region 20 forming the dicing line 2 via a thick insulating film 50,
In order to apply an externally applied positive voltage V to the N-type impurity diffusion region 31 formed on the surface of the P-type semiconductor substrate 10 and the N-type impurity diffusion region 31, The N+ type impurity diffusion region 32 formed, the P+ type impurity diffusion region 33, 34 formed on the surface of the N− type impurity diffusion region 31, and the P+ type impurity diffusion region 33.
．． A gate electrode 36 made of polysilicon, for example, is formed on a charge transfer region between 34 with an extremely thin insulating film 35 interposed therebetween. P+ type impurity diffusion region 33
An external voltage V is applied to. The P channel field effect transistor formed in this N- type impurity diffusion region 31 is used for peripheral circuits such as decoders and buffers constituting a semiconductor memory device.

The memory cell 40 includes an N÷ type impurity diffusion region 41 forming a bit line and an N type impurity diffusion region forming a storage node of the memory cell.
Ten type impurity diffusion region 42 and N+ type impurity diffusion region 41
．． A gate electrode 44 is formed on the charge transfer region between 42 with an extremely thin insulating film (gate insulating film) 43 interposed therebetween;
Cell plate 4 serving as the other electrode of the memory cell capacitor
5. Here, the memory cell 40 is illustratively shown as having a one-transistor/one-capacitor type structure, and this specific structure may be of any kind.

Next, the operation will be explained. First, as in the conventional case, an internal substrate bias potential Vaa from the substrate bias generation circuit shown in FIG. 5 is applied to the N+ type impurity diffusion region 20. Further, a substrate bias is applied to the semiconductor substrate 10 via a parasitic diode 8 formed between the N0 type impurity diffusion region 20 forming the dicing line 2 and the P- type semiconductor substrate 10. Now, due to the operation of the internal circuit in the semiconductor memory device, the substrate bias potential applied to the semiconductor substrate 10 changes, and a forward current flows through the parasitic diode 8. As a result, negatively charged electrons are transferred to the parasitic diode. Suppose that it is implanted into the P- type semiconductor substrate 10 through the P-type semiconductor substrate 10. Electrons injected into the P'' type semiconductor substrate 10 through the parasitic diode 8 are transferred to the N- type impurity biased to a positive potential via the N-type impurity diffusion layer 32 to which a positive voltage V is applied. All are captured in the diffusion region 31.

Therefore, the electrons injected into the semiconductor substrate 10 via the parasitic diode 8 do not reach the memory cell 40 (
Therefore, the data held in the memory cells is not adversely affected, and malfunctions of the semiconductor memory device can be prevented. Furthermore, the injected electrons do not reach the peripheral circuits, and malfunctions of the peripheral circuits due to the injected electrons can be prevented.

Here, the N- type impurity diffusion region 31 is preferably formed deeper than the N+ impurity diffusion region 20 forming the dicing line 2. By doing so, it becomes possible to capture electrons injected into the P- type semiconductor substrate 10 more reliably.

Here, since the P-channel MOS transistor formed in the N-type impurity diffusion region 31 constitutes the peripheral circuit of the semiconductor memory device, no new and complicated manufacturing process is added to the conventional manufacturing process of the conductor memory device. An electron trapping region can be easily formed without adding.

[Effects of the Invention] As described above, according to the present invention, since the charge trapping region is provided near the dicing line consisting of the impurity diffusion region,
Even if the substrate bias potential applied to the semiconductor substrate fluctuates and charges are injected from the impurity diffusion region that forms dicing lines on the semiconductor substrate, all of them are captured in the charge trapping region, so the information held in the memory cells is destroyed. Furthermore, it is possible to prevent malfunctions caused by charges injected into other peripheral circuits, thereby realizing a stable semiconductor memory device without malfunctions.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a main part of an embodiment of the semiconductor memory device according to the present invention, and is a view showing the cross-sectional structure taken along the line A--A shown in FIG. FIG. 3 is a plan view showing the positional relationship between a semiconductor memory device formed on a semiconductor wafer and a dicing line. FIG. 4 is an enlarged view of the dicing line portion of the semiconductor wafer. FIG. 5 is a diagram showing an example of the configuration of a conventionally used substrate bias generation circuit. FIG. 6 is a sectional view showing the structure of the output section of the substrate bias generation circuit shown in FIG. In the figure, 1 is a semiconductor wafer, 2 is a dicing line, 3 is a semiconductor memory device, 4 is a charge pump circuit, 5 is a capacitance, 6 and 7 are MOS transistors, 8 is a parasitic diode, 10 is a semiconductor substrate, and 20 is a dicing line. 30 is a charge trapping region;
31 is an N- type impurity diffusion region, 32 is an N+ type impurity diffusion region, 33.34 is a P+ type impurity diffusion region, 40 is a memory cell, and 41.42 is an N+ type impurity diffusion region constituting the memory cell. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] (1) The impurity diffusion layer is cut along the dicing line from a semiconductor wafer in which a plurality of semiconductor memory devices are arranged, the area of which is defined by the dicing line made of the impurity diffusion layer, and the dicing line is formed around the dicing line. a semiconductor substrate having: a memory element formed on the semiconductor substrate; and a substrate bias potential generation for applying a bias potential to an impurity diffusion layer formed on the semiconductor substrate and forming the dicing line in the peripheral area of the semiconductor substrate. a semiconductor memory device having a circuit, the semiconductor memory device comprising: a charge trapping region formed near the impurity diffusion layer serving as the dicing line and capturing charges flowing into the semiconductor substrate from the impurity diffusion layer serving as the dicing line; Storage device. (2) The impurity diffusion layer that will become the dicing line is an N-type impurity diffusion layer, and the semiconductor substrate is a P-type semiconductor substrate, and the charge trapping region is an N-type impurity diffusion layer that will become the dicing line on the surface of the semiconductor substrate. The semiconductor memory device according to claim 1, comprising an N-type impurity diffusion layer formed near the impurity diffusion layer and biased to a positive potential. (3) The semiconductor memory according to claim 2, wherein a P-channel field effect transistor forming a peripheral circuit of the semiconductor memory device is formed in the N-type impurity diffusion layer biased to a positive potential. Device.