JPH04317372A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent an n-type diffusion layer and a p-well from getting in forward bias condition by biasing the p-well of the n-type diffusion layer which falls below the earth potential to the inner potential which has occurred inside a semiconductor device. CONSTITUTION:In a semiconductor storage device which has a memory cell inside the p-well 4 provided in a semiconductor substrate 1, an n-type MOSFET 5, which constitutes the peripheral circuit excepting the memory cell, is made inside the p-well 2 biased to the internal potential.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to complementary MOS semiconductor memory devices.

0002

2. Description of the Related Art Conventional complementary MOS semiconductor memory devices, particularly those in which dynamic memory cells are formed in P-wells, stabilize the characteristics of MOSFETs forming transfer gates of memory cells, as shown in FIG. In order to reduce the capacitance of the diffusion layer connected to the bit line, the potential of the P well is biased to an internal potential below the ground potential generated within the semiconductor device. The circuit needs to be formed in a well that is not biased to an internal potential due to problems with transistor characteristics as described below.

In other words, in a MOSFET fabricated with a submicron channel length, if the impurity concentration distribution is set on the assumption that the substrate potential is biased, the threshold voltage vs. substrate potential characteristic will change as shown by curve A in FIG. When the substrate potential is 0V, the threshold voltage is approximately 0V or below 0V, and when the power is turned on, the substrate potential has not reached the desired potential and an excessive leakage current occurs due to latch-up, etc., which is specific to CMOS semiconductor devices. This is because there is a risk of damaging the device. In order to avoid such a risk and obtain a sufficient threshold voltage even when the substrate potential is 0V, MOSFETs with threshold voltage vs. substrate potential characteristics as shown in curve B in Figure 4 are adopted as peripheral circuit elements. There is a need to.

For the reasons stated above, the conventional complementary type M
In an OS semiconductor memory device, a P-well in which a memory cell is formed is biased to an internally generated potential, and a P-well in which a MOSFET for a peripheral circuit other than the memory cell is formed is biased to a ground potential.

[0005]

However, in the conventional complementary MOS semiconductor memory device described above, in the peripheral circuit elements, for example, in the output buffer circuit, the contact potential of the output terminal is as shown in FIG. If ringing occurs due to an inductance component included in wiring such as a bonding line on a semiconductor device chip or in a package, and the contact potential becomes more negative than the ground potential, or if the signal input to the input terminal When the potential becomes more negative than the ground potential, the N-type diffusion layer region connected to the output terminal or the input terminal becomes forward biased with respect to the P-well, and electrons are injected into the P-well. The disadvantage is that the potential of the well fluctuates.

[0006]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes an N-type transistor of an output buffer and an N-type diffusion layer of an input protection circuit device in a P-well biased with an internal potential generated inside the semiconductor device. have.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention.

[0009] N-type semiconductor substrate 1 is biased to a power supply potential. The memory cell matrix region is formed inside a P well 4 biased to an internal voltage. A P-type MOSFET 8 as a peripheral circuit is formed on the semiconductor substrate 1. The N-type MOSFET 7 of the peripheral circuit is formed in a P well biased to the ground potential. A P-type MOSFET 6 for an output buffer is formed on the semiconductor substrate 1. An N-type MOSFET 5 for an output buffer is formed in a P well 2 biased to ground potential. Here, even if the output terminal fluctuates from high level to low level and drops below the ground potential due to ringing due to the inductance component, the junction between the N-type diffusion layer and the P well does not change in the forward direction, and the P well potential is kept stable. .

FIG. 2 is a schematic cross-sectional view showing a second embodiment of the present invention.

[0011] N-type semiconductor substrate 1 is biased to a power supply potential. The memory cell matrix region is formed inside a P well 4 biased to an internal voltage. P-type MOSFET 8 of the peripheral circuit is formed on a semiconductor substrate. The N-type MOSFET 7 of the peripheral circuit is formed in a P well biased to the ground potential. The N type impurity diffusion layer 3 of the input protection device is formed in the P well 2 biased to an internal potential. Here, even if a potential lower than the ground potential is applied to the input terminal, the junction with the P-well does not become forward-oriented, and the P-well potential is kept stable.

0012

Effects of the Invention As explained above, the present invention has the advantage of biasing the P-well of the N-type diffusion layer, which is below the ground potential, to the internal potential generated within the semiconductor device.
This has the advantage of preventing the well from becoming forward biased.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing an example of a conventional semiconductor memory device.

FIG. 4 is a diagram showing threshold voltage versus substrate voltage characteristics of a MOSFET.

FIG. 5 is a diagram showing operating waveforms of the output buffer circuit.

[Explanation of symbols]

1 N-type semiconductor substrate 2,4 P well 3 N-type diffusion layer for input protection 5,7 N-type MOSFET 6,8 P-type MOSFET

Claims (1)

[Claims] 1. A semiconductor memory device in which a memory cell is formed on a semiconductor substrate of one conductivity type and in a first well of an opposite conductivity type, wherein the memory cell is formed in a region other than the first well and in which the semiconductor memory cell is formed in a region other than the first well; 1. A semiconductor memory device comprising at least one transistor constituting a circuit other than a memory cell formed in a second well of an opposite conductivity type biased by the internal potential generated above.