JPH1168058A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device, which is capable of being restrained from increasing in chip size without deteriorating the high- potential generation function of a charge pump circuit. SOLUTION: A first shield layer 1, formed of first aluminum layer, is provided to a gate electrode layer 5 comprised in the MOS capacitor of a charge pump circuit. The first shield layer 1 is connected to a second GND wiring layer 2 formed of second aluminum layer. The potential of the GND wiring 2 is fixed at a grounding potential GND. By this setup, signal lines L1 , L2 ,..., Lk formed of second aluminum layer can be arranged on the charge pump circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a high voltage generating circuit.

[0002]

2. Description of the Related Art Conventionally, an electrically rewritable nonvolatile semiconductor memory device has a charge pump circuit for generating a predetermined internal potential in order to appropriately operate an internal circuit.

FIG. 6 is a circuit diagram showing a basic configuration of a charge pump circuit 550 used in a conventional semiconductor memory device. The charge pump circuit 550 shown in FIG. 6 is a circuit for generating the internal boosted potential VPP, and includes a plurality of P-channel MOS transistors C (C1, C2, C3,.
Cn-1, Cn), and a plurality of N-channel MOSs
The transistors T (T0, T1, T2, T3,..., Tn−
1, Tn).

Each P-channel type MOS transistor C
Functions as a capacitor. In the following description, for simplicity, a capacitor formed from a P-channel MOS transistor is called a MOS capacitor, and an N-channel MOS transistor is called a MOS transistor.

[0005] One conduction terminal of the MOS transistor T0 is connected to the external power supply potential VCC. From one conduction terminal of MOS transistor Tn, internal boosted potential VP
P is output.

A charge pump circuit 550 operates in response to clock signals φ and / φ received from the outside, and a MOS capacitor C
(C1, C2, C3,..., Cn-1, Cn) generates a high voltage by charge pumping.

Clock signals φ and / φ have an amplitude of an external power supply voltage (usually 3 volts) supplied into the semiconductor memory device. The charge boosted by the first-stage MOS capacitor C1 is charged to the next-stage MOS capacitor C2 via the MOS transistor T1. MOS capacitor C2 performs boosting again using the charged electric charge. The boosted charge is charged to the next stage MOS capacitor C3 via the MOS transistor T2.

In this manner, an external power supply voltage of about 3 volts to a high voltage of about 10 volts (internal boosted potential VP)
P). Internal boosted potential VPP is applied to a circuit required in the semiconductor memory device, for example, a memory transistor.

Next, a layout of a conventional semiconductor memory device 500 having a charge pump circuit 550 will be described.

FIG. 7 is a plan view showing an arrangement relationship between components of the charge pump circuit 550 in the conventional semiconductor memory device 500 and various signal wirings. In FIG. 7, as specific examples of the components of charge pump circuit 550, MOS capacitor C receiving clock signal φ, M
The connection relationship between the OS capacitor C and the MOS transistor T to which the gate electrode layer is connected is shown.

FIG. 8 is a sectional view obtained when the MOS capacitor C of the charge pump circuit 550 is cut along the line AA in FIG.

In FIGS. 7 and 8, symbols L1, L2,
.., Lk represent various signal wirings in the semiconductor memory device 500.

Referring to FIGS. 7 and 8, MOS capacitor C included in charge pump circuit 550 includes a P-type silicon substrate 50, an N well 51, a first impurity region 52, a second impurity region 53, and a gate. It has an electrode layer 55 and field insulating films 57.1 and 57.2.

Field insulating films 57.1 and 57.2 are formed on the main surface of P-type silicon substrate 50. An N well 51 is formed in a region electrically separated by the field insulating films 57.1 and 57.2. First impurity region 52 and second impurity region 53 are formed on the main surface of N well 51 at predetermined intervals. The gate electrode layer 55 made of polysilicon is formed over a region from the first impurity region 52 to the second impurity region 53 with a gate insulating film interposed.

The contact holes 5 are formed in the insulating layers on the first impurity region 52 and the second impurity region 53, respectively.
6.1, 56.2 are formed. The first impurity region 52 and the second impurity region 53 are electrically connected by a first-layer aluminum wiring 60 via contact holes 56.1 and 56.2, respectively. First layer aluminum wiring 6
0 is located directly above the gate electrode layer 55. The first layer aluminum wiring 60 is further connected to the second layer aluminum wiring 61.
1 is connected. The above-described clock signal φ is supplied to the MOS capacitor C via the aluminum wiring 61.1 of the second layer. The clock signal / φ is supplied to the MOS capacitor C (not shown) of the preceding stage or the next stage via the aluminum wiring 61.2 of the second layer.

The MOS transistor T has a first impurity region 62, a second impurity region 63, and a gate electrode layer 65. From the first impurity region 62 to the second
The gate electrode layer 65 is formed on the region reaching the impurity region 63 of FIG. Gate electrode layer 65 is connected to gate electrode layer 55 of MOS capacitor C via aluminum interconnection 70. Further, second impurity region 63 is connected to a next-stage MOS capacitor C and MOS transistor T (not shown) via aluminum interconnection 71.2. Also,
Gate electrode layer 65 and first impurity region 62 are connected to a preceding MOS transistor T (not shown) via aluminum interconnection 71.1.

[0017]

By the way, in the conventional semiconductor memory device 500, a high internal boosted potential VP
In order to generate P at high speed, the charge pump circuit 55
A MOS capacitor C having a large area is used as a component of 0.

However, when the MOS capacitor C having a large area is provided, noise is easily generated inside the semiconductor memory device 500 due to capacitive coupling with other signal lines.

Therefore, in order to suppress this effect, as shown in FIG. 7, the other signal lines L1, L2,.
Must be arranged in a region away from the region where the charge pump circuit 550 is formed, and there is a problem that the larger the capacitance of the MOS capacitor C, the larger the region of the peripheral circuit.

The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor memory device capable of suppressing a chip size without reducing a high potential generating function of a charge pump circuit. Is to provide.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a charge pump circuit including a plurality of capacitors, wherein each capacitor has a well and a predetermined surface provided on the surface of the well. An MO formed by a pair of impurity regions formed at intervals and a gate electrode layer formed on a region between the pair of impurity regions
An S-capacitor, further comprising a shield layer fixed at a predetermined potential and arranged at a position covering at least each gate electrode layer.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, further comprising a plurality of signal wirings arranged on the shield layer.

A semiconductor memory device according to a third aspect is the semiconductor memory device according to the second aspect, wherein the predetermined potential is an external power supply potential.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the second aspect, wherein the predetermined potential is a ground potential.

According to a fifth aspect of the present invention, there is provided a semiconductor memory device including a charge pump circuit formed of a plurality of MOS transistors, wherein each of the MOS transistors is connected by a first layer of aluminum wiring. A second-layer aluminum wiring for shielding, which is arranged on the first-layer aluminum wiring via an insulating film and is fixed at a predetermined potential.

A semiconductor memory device according to a sixth aspect is the semiconductor memory device according to the fifth aspect, wherein the predetermined potential is an external power supply potential.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to the fifth aspect, wherein the predetermined potential is a ground potential.

[0028]

Embodiments of the present invention will be described below. Note that the same components are denoted by the same reference numerals and symbols, and description thereof will not be repeated.

[Embodiment 1] Embodiment 1 of the present invention
Is M of the charge pump circuit in the semiconductor memory device.
By providing a shield layer fixed at a predetermined potential on the OS capacitor portion, it is possible to suppress noise caused by the MOS capacitor portion.
Further, by providing the shield layer, it is possible to arrange the signal wiring on the charge pump circuit.

Semiconductor memory device 1 according to the first embodiment of the present invention
The 00 layout will be described.

FIG. 1 is a plan view showing an arrangement relationship between components of the charge pump circuit 150 and various signal wirings in the semiconductor memory device 100 according to the first embodiment of the present invention.

Semiconductor memory device 1 according to the first embodiment of the present invention
00 includes a charge pump circuit 150. The components of the charge pump circuit 150 are a plurality of MOS capacitors C and a plurality of MOS transistors T, as in the conventional charge pump circuit 550 described above.

In FIG. 1, the charge pump circuit 15
As a specific example of the component 0, a connection relationship between a MOS capacitor C receiving a clock signal φ and a MOS transistor T to which the MOS capacitor C and the gate electrode layer are connected is shown.

FIG. 2 is a sectional view obtained when the MOS capacitor C of the charge pump circuit 150 is cut along the line BB in FIG. 1, and FIG. 3 is a sectional view taken along the line CC in FIG.
The cross-sectional views obtained when the MOS capacitor C portion of the charge pump circuit 150 is cut along the line are shown.

Referring to FIGS. 1 to 3, MOS capacitor C of charge pump circuit 150 is a P-type silicon substrate 5.
0, an N well 51, a first impurity region 52, a second impurity region 53, a gate electrode layer 55, and field insulating films 57.1 and 57.2. These configurations are:
This is the same as the configuration of the MOS capacitor C described in FIG.

The contact 56.1 formed on the insulating layer on the first impurity region 52 is connected to the first-layer aluminum wiring 10. The contact 56.2 formed in the insulating layer on the second impurity region 53 is a first layer aluminum wiring 1
1 is connected. First layer aluminum wiring 10, 11
Are connected through an aluminum wiring 12 to an aluminum wiring 61.1 for supplying a clock signal φ.

In the first embodiment of the present invention, the shield layer 1 is formed of a first layer of aluminum on the gate electrode layer 55 formed of polysilicon. The shield layer 1
Further, it is connected to the second-layer aluminum GND wiring 2. G
The potential of the ND wiring 2 is fixed to the ground potential GND.

That is, in the semiconductor memory device 100 according to the first embodiment of the present invention, the charge pump circuit 150
Are laid out in the first layer of aluminum, and the MOS capacitor C portion is shielded by the first layer of aluminum fixed at a predetermined potential.

With this configuration, noise generated by the MOS capacitor C is suppressed, and as shown in FIG. 1, a plurality of signal lines L1 formed of aluminum in the second layer are provided on the charge pump circuit 150. , L2, ..., L
k can be arranged.

Therefore, even if the capacity of the MOS capacitor C is increased to improve the performance of the charge pump circuit 150, an increase in the area of the peripheral circuit in the entire chip can be suppressed.

In place of the GND wiring 2 shown in FIGS. 1 to 3, shielding may be performed by a VCC wiring receiving the external power supply voltage VCC.

[Second Embodiment] FIG. 4 is a plan view showing an arrangement relationship between components of a charge pump circuit 250 and various signal lines in a semiconductor memory device 200 according to a second embodiment of the present invention.

Semiconductor memory device 2 according to the second embodiment of the present invention
00 includes a charge pump circuit 250. The components of the charge pump circuit 250 are a plurality of MOS capacitors C and a plurality of MOS transistors T, as in the conventional charge pump circuit 550 described above.

In FIG. 4, the charge pump circuit 25
As a specific example of the component 0, a connection relationship between a MOS capacitor C receiving a clock signal φ and a MOS transistor T to which the MOS capacitor C and the gate electrode layer are connected is shown.

FIG. 5 is a sectional view taken along the line DD of FIG.
FIG. 4 shows a cross-sectional view obtained when the MOS capacitor C included in the charge pump circuit 250 is cut.

Referring to FIGS. 4 and 5, MOS capacitor C of charge pump circuit 250 is a P-type silicon substrate 5.
0, an N well 51, a first impurity region 52, a second impurity region 53, a gate electrode layer 55, and field insulating films 57.1 and 57.2. These configurations are:
This is the same as the configuration of the MOS capacitor C described in FIG. Further, the MOS transistor T has a first impurity region 62, a second impurity region 63, and a gate electrode layer 65.

In the second embodiment of the present invention, the field insulating film 57.1 is formed above the first layer of the aluminum wiring 10.
On the region from to the part of the gate electrode layer 55
The wiring 5 is formed from the aluminum layer. Furthermore, a second layer of aluminum wiring 6 is formed in a region that does not overlap with the wiring 5, and over a region from the field insulating film 57.2 to a part of the gate electrode layer 55 above the first aluminum wiring 11. To form

The wirings 5 and 6 in the second layer are GND wirings, and the potential is fixed to the ground potential GND. Further, the GND lines 5 and 6 are connected to the signal lines 71.1, 70, and 7 respectively.
1.2 is located in the upper layer. The GND wirings 5 and 6 are composed of MOS transistors T and MO
Shield all of the S capacitor C.

That is, in the semiconductor memory device 200 according to the second embodiment of the present invention, the layout of the charge pump circuit 250 is performed using only the first layer of aluminum, and further shielded by the second layer of aluminum fixed at a predetermined potential. I do.

Since the GND wiring itself obtains a strong potential from a chip pad (not shown), the potential does not fluctuate due to noise received from the charge pump circuit 250.

With this configuration, the charge pump circuit 250 can be shielded from other signal lines. Therefore, it is not necessary to secure a layout area for only the charge pump circuit as in the related art, and the area of the entire chip can be reduced.

The GND wirings 5 and 6 shown in FIGS.
Alternatively, shielding may be performed with a VCC wiring fixed to the external power supply potential VCC.

[0053]

As described above, according to the semiconductor memory device of the first aspect, the MOS capacitor portion of the charge pump circuit can be shielded by the wiring fixed at the predetermined potential level, and as a whole, The chip area can be reduced.

Further, according to the semiconductor memory device of the second aspect, the MOS capacitor portion of the charge pump circuit can be shielded by the wiring fixed at a predetermined potential level, so that the signal wiring is formed on the charge pump circuit. , The area of the chip can be reduced.

Furthermore, according to the semiconductor memory device of the third or fourth aspect, the MOS of the charge pump circuit
The capacitor portion can be shielded by an external power supply potential or a ground potential.

According to the semiconductor memory device of the fifth aspect, a wiring fixed at a predetermined potential level is arranged above the charge pump circuit to shield the charge pump circuit, so that the chip area as a whole is reduced. Can be achieved.

Further, according to the semiconductor memory device of the sixth or seventh aspect, the charge pump circuit can be shielded by the external power supply potential or the ground potential.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device 10 according to a first embodiment of the present invention.
FIG. 3 is a plan view showing an arrangement relationship between a charge pump circuit 150 and various signal lines at 0.

FIG. 2 is a cross-sectional view obtained when the MOS capacitor C portion of the charge pump circuit 150 is cut along the line BB in FIG.

FIG. 3 is a cross-sectional view obtained when the charge pump circuit 150 is cut at the MOS capacitor C portion along the line CC in FIG. 1;

FIG. 4 shows a semiconductor memory device 20 according to a second embodiment of the present invention;
FIG. 9 is a plan view showing an arrangement relationship between a charge pump circuit 250 and various signal lines at 0.

5 is a cross-sectional view obtained when the MOS capacitor C included in the charge pump circuit 250 is cut along the line DD in FIG.

FIG. 6 is a circuit diagram showing a basic configuration of a charge pump circuit 550 used in a conventional semiconductor memory device.

FIG. 7 is a plan view showing an arrangement relationship between a charge pump circuit 550 and various signal lines in a conventional semiconductor memory device 500.

8 is a cross-sectional view obtained when the MOS capacitor C included in the charge pump circuit 550 is cut along the line AA in FIG.

[Explanation of symbols]

50 P-type silicon substrate, 51 N well, 52, 5
3, 62, 63 impurity region, 55, 65 gate electrode layer, 56 contact hole, 57 field insulating film, 1
Shield layer, 2, 5, 6 GND wiring, 10-12,
60, 61, 71 aluminum wiring, L signal wiring, CMO
S capacitor, TMOS transistor, 150-25
0 charge pump circuit, 100 to 200 semiconductor memory device.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (7)

[Claims] 1. A semiconductor memory device including a charge pump circuit including a plurality of capacitors, wherein each of the capacitors includes a well, and a pair of impurity regions formed at a predetermined distance from each other on a surface of the well. A MOS capacitor formed by a gate electrode layer formed on a region between the pair of impurity regions, further fixed at a predetermined potential arranged at a position covering at least each of the gate electrode layers. Having a shield layer,
Semiconductor storage device. 2. The semiconductor memory device according to claim 1, further comprising a plurality of signal wirings arranged on said shield layer. 3. The semiconductor memory device according to claim 2, wherein said predetermined potential is an external power supply potential. 4. The method according to claim 1, wherein the predetermined potential is a ground potential.
The semiconductor memory device according to claim 2. 5. A semiconductor memory device comprising a charge pump circuit formed of a plurality of MOS transistors, wherein each of the MOS transistors is connected by a first layer of aluminum wiring, and A second shield, which is arranged on the aluminum wiring via an insulating film and fixed at a predetermined potential,
A semiconductor memory device including a layer of aluminum wiring. 6. The semiconductor memory device according to claim 5, wherein said predetermined potential is an external power supply potential. 7. The predetermined potential is a ground potential.
The semiconductor memory device according to claim 5.