JPH0212027B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which noise is reduced by applying a ground voltage or a power supply voltage.

A conventional semiconductor integrated circuit will be explained with reference to FIG. 1, taking as an example a circuit in which two-input OR gates are integrated. In FIG. 1, 1 is a semiconductor integrated circuit chip (hereinafter simply referred to as a chip) that integrates a two-input OR gate, and 2 to 5 are input/output terminals that connect the chip 1 to an external circuit (not shown). 2 is a power terminal, 3 is a ground terminal, 4a, 4b are input terminals, 5
is the output terminal. 6 is an input protection circuit, 7 is an internal circuit, 8 is an output circuit, 9 is an input protection resistor, 10
is an input protection transistor, and 11a and 11b are output transistors.

Next, the operation will be explained.

When a normal voltage within the range of ground voltage and power supply voltage is applied to the input terminals 4a and 4b, the input protection transistor 10 remains off, so the input voltage is transmitted as is to the internal circuit 7, and the logic according to the level is applied. An output is applied from the internal circuit 7 to the output circuit 8, and one of the output transistors 11a and 11b is turned on to charge or discharge the external circuit through the output terminal 5. Furthermore, if an abnormal voltage outside the range of the ground voltage and power supply voltage is accidentally applied to the input terminals 4a and 4b, the input protection transistor 10 is turned on, so that the input voltage is
The internal circuit 7 is protected from the application of overvoltage because it is resistance-divided by the input protection resistor 9 and the input protection resistor 9.

However, in this case, overcurrent flows through the input protection resistor 9 and the input protection transistor to the ground terminal 3.
Because of this, noise is generated in the ground terminal 3 and the ground wiring inside the chip 1. Furthermore, an overvoltage may be applied to the output terminal 5 due to a reflected wave of the output signal, etc., and in this case too, an overcurrent flows through the output transistors 11a and 11b to the power supply terminal 2 and the ground terminal 3. Therefore, power terminal 2,
Noise occurs in the ground terminal 3, power supply wiring, and ground wiring. Since these wirings are also connected to the internal circuit 7, noise from each of the terminals mentioned above is transmitted not only to the input protection circuit 6 and the output circuit 8 but also to the internal circuit 7, causing malfunctions and latch-up.

As described above, in the conventional semiconductor integrated circuit, the internal circuit 7 is connected to the power supply wiring and ground wiring of the same system as the input protection circuit 6 and the output circuit 8.
There is a drawback that noise due to overvoltage applied to the input/output terminals is transmitted to the internal circuit 7 and the like through the power supply wiring and the ground wiring.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and provides input protection for the power supply wiring and the ground wiring connected to the internal circuit by providing a plurality of at least one of a power supply terminal and a plurality of ground terminals. By providing a separate system from those connected to the circuit and output circuit, the purpose is to isolate the internal circuit from noise caused by overvoltage applied to the input/output terminals. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a configuration diagram showing an embodiment of this invention.
2a and 2b are power terminals, 3a and 3b are ground terminals, and the power terminal 2a and the ground terminal 3a are dedicated to the input protection circuit 6 and the output circuit 8;
b and the ground terminal 3b are provided exclusively for the internal circuit 7.

FIG. 3 is a plan view showing the chip 1 attached to a capacitor 12 such as a ceramic package.
13 to 16 are external terminals provided in the capacitor 12, 13 is a power supply terminal, 14 is a ground terminal, and 15
a and 15b are input terminals, and 16 is an output terminal.
Each of the terminals 2 to 5 inside the chip 1 and each of the external terminals 13 to 16 are connected through a metal wire 17. In particular, the power terminals 2a, 2 in the chip 1
b and the ground terminals 3a, 3b are connected to one external terminal 13 or 14. Therefore, the number of required external terminals is the same as in the conventional case. Note that when the semiconductor integrated circuit board is at the same potential as the power supply or ground, the power supply terminals 2a, 2b or the ground terminals 3a, 3b are connected through the board, but the impedance of the board is lower than that of metal wiring. big.

When overvoltage is applied to the input terminals 4a, 4b and the output terminal 5, the power supply terminals 2a, 2a, which are connected to the input protection circuit 6 and the output circuit 8, as in the conventional case.
Noise is generated at the ground terminal 3a. This noise is transmitted to the chip 1 via the external power supply terminal 13 and the external ground terminal 14.
The signal is transmitted to the internal power supply terminal 2b, the ground terminal 3b, and further to the internal circuit 7. However, metal wire 17
Noise is attenuated and transmitted due to the impedance of the Moreover, the external power supply terminal 13 and the external ground terminal 14 are connected to the power supply at low impedance, and since a decoupled capacitor is generally connected in parallel between the external power supply terminal 13 and the external ground terminal 14, the power supply in the internal circuit 7 is Voltage noise and ground voltage noise are minimal.

In the above embodiment, the input protection circuit 6 and the output circuit 8 are divided into two groups, and the internal circuit 7 is divided into two groups. If the division method is such that the input protection circuit 6 and the output circuit 8 are not included in the input protection circuit 6 and the output circuit 8, even if some internal circuits 7 that are insensitive to noise are included in the input protection circuit 6 and the output circuit 8, or three or more groups Even if it is divided into two parts, the same effect as in the above embodiment can be obtained.

In addition, power terminals 2a, 2b and ground terminals 3a, 3
Although a configuration in which two terminals of both terminals b are provided is shown, a plurality of terminals of only one terminal may be provided, and the other terminal may be made common to one terminal.

Further, in the above embodiment, a two-input OR gate is shown as the internal circuit 7, but it goes without saying that it can be applied to any type of internal circuit 7, such as random logic or memory.

As explained above, according to the present invention, the power supply terminal and the ground terminal of the internal circuit of the semiconductor integrated circuit are provided separately from those of the input protection circuit and the output circuit, so that operation is stable against input/output noise. There is an effect that can be obtained.

[Brief explanation of drawings]

Figure 1 shows a conventional semiconductor integrated circuit; Figure 2 shows a conventional semiconductor integrated circuit;
The figure shows a semiconductor integrated circuit according to an embodiment of the invention, and FIG. 3 is a plan view showing the semiconductor integrated circuit according to an embodiment of the invention attached to a capacitor. In the figure, 1 is a semiconductor integrated circuit chip, 2a, 2b
is the power terminal, 3a, 3b is the ground terminal, 4a, 4b
is an input terminal, 5 is an output terminal, 6 is an input protection circuit,
7 is an internal circuit, 8 is an output circuit, 9 is an input protection resistor, 10 is an input protection transistor, 11a, 11
b is an output transistor, 12 is a capacitor, 13 is an external power supply terminal, 14 is an external ground terminal, 15a, 15b
16 is an external input terminal, 16 is an external output terminal, and 17 is a metal wire.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a power supply terminal, a ground terminal, an input/output terminal, an internal circuit, an input protection circuit, and an output circuit are formed on the same substrate, including a plurality of at least one of the power supply terminal and the ground terminal, The plurality of power supply terminals or ground terminals are separately provided for the internal circuit and the input protection circuit, or for the internal circuit and the output circuit, respectively, using metal wiring for the internal circuit and the input protection circuit, respectively. Alternatively, a semiconductor integrated circuit characterized in that the internal circuit and the output circuit are connected.