JPH1065115A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the degree of integration of a semiconductor integrated circuit device. SOLUTION: An information accumulating capacity element C, in which a ferroelectric substance film 10, whose polarization direction changes describing a hysteresis curved line, is pinched by the first electrode 9 and the second electrode 11, and a memory cell M, consisting of a semiconductor region 6 is electrically connected to a bit line B and a direct current of the memory cell selecting MISFETQ on which a gate electrode 5 is electrically connected to a word line WL, are provided in this device. At the time the information of a memory cell M is read out, the potential of one half of the operation potential Vcc to be applied to the bit line BL of the second electrode 11 of the information accumulating capacity element C, is fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to information storage in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode. And a semiconductor region electrically connected to a bit line, the other semiconductor region electrically connected to a first electrode of the information storage capacitor, and a gate electrode electrically connected to a word line. The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a memory cell composed of a direct circuit with a connected MISFET for selecting a memory cell.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit device, an FRAM is used.
(Ferro-electricRandomAccessMemory)
Is being done. This FRAM memory cell stores information.
MISFET for selecting a storage capacitor and a memory cell (Metal
InsulatorSemiconductorFieldEffectTransist
or) and stores 1 [bit] information
doing.

[0003] The information storage capacitance element is a memory cell selection MI to reduce the planar size of the memory cell.
It is configured above the SFET. This information storage capacitor has a structure in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode.

The memory cell selecting MISFET is formed of, for example, an n-channel conductivity type. Each of a pair of n-type semiconductor regions, which are a source region and a drain region of the n-channel conductive type memory cell selecting MISFET,
The main surface of the active region of the p-type semiconductor substrate or the main surface of the p-type well region formed on the main surface of the active region of the semiconductor substrate.

One semiconductor region of the memory cell selection MISFET is electrically connected to a bit line, the other semiconductor region is electrically connected to a first electrode of an information storage capacitor, and a gate electrode thereof is provided. It is electrically connected to the word line.

The plurality of memory cells are arranged in a matrix to form a memory cell array. In the memory cell array, a plurality of bit lines and plate wires extending in the X direction are arranged, and a plurality of word lines extending in the Y direction are arranged. One semiconductor region of each memory cell selection MISFET of a plurality of memory cells arranged along the extending direction is electrically connected to one bit line. Further, the second electrodes of the information storage capacitance elements of a plurality of memory cells arranged along the extending direction are electrically connected to one plate wiring. The gate electrode of the memory cell selecting MISFET of each of the plurality of memory cells arranged along the extending direction is electrically connected to one word line.

In the memory cell, information (data) of "1" or "0" is distinguished depending on which electrode the polarization direction of the ferroelectric film faces. For example, FIG.
As shown in the (hysteresis curve diagram of the ferroelectric film), the charge of the memory cell is at the position of point C or the position of point A in the initial state. When the information of the bit line is “1”, the charge of the memory cell moves from the point C to the point B by raising the word line and raising the plate wiring. The signal amount at this time is point C′−point C. Conversely, when the bit line information is "0", the charge of the memory cell moves from point A to point B by raising the word line and raising the plate wiring. The signal amount at this time is point C′−point A.

[0008] The FRAM is, for example,
Nikkei Micro Device published by Nikkei BP [June 1992
Monthly, pages 78 to 83].

[0009]

The FRAM controls the information reading operation of the memory cell by changing the potential of the plate wiring. Hereinafter, the information reading operation of the memory cell will be described with reference to FIGS. 7 and 6 (waveform diagrams).

[Reading of Information "0"] First, a selection potential Vch (for example, 5 [V]) is applied to the word line to raise the potential of the word line, and then the operating potential Vcc is applied to the plate wiring.
(For example, 3.3 [V]) is applied to raise the potential of the plate wiring. At this time, the charge of the memory cell moves from point A in the initial state to point B, and is read as information (data) “0”. Next, a reference potential Vss (for example, 0 [V]) is applied to the plate wiring to temporarily lower the potential of the plate wiring, and then the operating potential Vcc is applied to the plate wiring to raise the potential of the plate wiring. At this time, the charge of the memory cell moves from point B to point D via point C. Next, the reference potential Vss is applied to the plate wiring to lower the potential of the plate wiring. At this time, the charge of the memory cell moves from point D to point A in the initial state. Next, the reference potential Vss is applied to the word line, and the word line falls. Information “0” is read by this series of operations.

[Reading of Information "1"] First, the selection potential Vch is applied to the word line to raise the potential of the word line, and then the operating potential Vcc is applied to the plate wiring to raise the potential of the plate wiring. . At this time, the charge of the memory cell moves from the point C in the initial state to the point B, and is read as information (data) “1”. Next, the reference potential Vss is applied to the plate wiring.
Is applied to lower the potential of the plate wiring. At this time,
The charge of the memory cell moves from point B to point C in the initial state. Next, the reference potential Vss is applied to the word line, and the word line falls. Information “1” is read by this series of operations.

As described above, the information reading operation of the memory cell is controlled by changing the potential of the plate wiring. To perform the information reading operation of the memory cell, the plate wiring is divided for each bit line. Must be kept. For this reason, the area of the memory cell array increases by an amount corresponding to the separation dimension between the plate wirings, and FR
The degree of integration of AM decreases.

In the memory cell, the electric charge stored in the information storage capacitance element is changed to the memory cell selection MISF.
From the other n-type semiconductor region of ET to p-type semiconductor substrate or p-type
It gradually decreases due to the leak current (junction leak current) flowing in the mold well region. That is, the charge of the information storage capacitor moves from the point A to the point B shown in FIG. For this reason, refresh (rewrite) to replenish the reduced charge at regular intervals
It is necessary to perform the operation, and the power consumption of the FRAM increases by an amount corresponding to the number of times of the refresh operation.

An object of the present invention is to provide an information storage capacitor in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode, and that one of the semiconductor regions has A memory cell selection MISFET electrically connected to a bit line, the other semiconductor region electrically connected to a first electrode of the information storage capacitor, and a gate electrode electrically connected to a word line; It is an object of the present invention to provide a technique capable of increasing the degree of integration of a semiconductor integrated circuit device provided with a memory cell composed of a direct circuit.

Another object of the present invention is to provide a technique capable of reducing the power consumption of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) An information storage capacitor in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode, and one semiconductor region is connected to a bit line. The other semiconductor region is electrically connected to the first electrode of the information storage capacitor, and the gate electrode is directly connected to the memory cell selecting MISFET electrically connected to the word line. A semiconductor integrated circuit device comprising a memory cell comprising: a second electrode of the information storage capacitor element having an operating potential of 2 applied to the bit line;
The potential is fixed to one-half the potential.

(2) The MISFET for selecting a memory cell
Each of the pair of semiconductor regions is of the first conductivity type, and each of the pair of first conductivity type semiconductor regions is formed on the main surface of the second conductivity type semiconductor region formed on the insulating film; At least the bottom surface of the other second conductivity type semiconductor region electrically connected to the second electrode of the information storage capacitor element is brought into contact with the insulating film.

According to the above means (1), the information reading operation of the memory cell can be controlled without changing the potential of the plate wiring, so that the plate wiring can be configured as a common plate wiring. As a result, the distance between the plate wirings can be eliminated, and the area of the memory cell array can be reduced correspondingly, so that the degree of integration of the semiconductor integrated circuit device can be increased.

According to the means (2) described above, the other first conductive type semiconductor region and the second conductive type semiconductor region corresponding to the area of the bottom surface of the other semiconductor region of the memory cell selecting MISFET are formed. The area of the pn junction to be formed can be reduced, and the leakage current (junction leakage current) flowing from the other first conductivity type semiconductor region to the second semiconductor region can be reduced. A decrease in charge can be suppressed. As a result, the retention time of the charge stored in the information storage capacitor element can be increased, and the number of refresh operations (rewrite operations) of the memory cell can be reduced. Electricity can be achieved.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows an FRA according to an embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of a main part of a memory cell array of M (semiconductor integrated circuit device).

As shown in FIG. 1, the FRAM has a memory cell array MC in which a plurality of memory cells M are arranged in a matrix.
A is on the tower. The memory cell M is configured by a series circuit of an information storage capacitor C and a memory cell selection MISFETQ, and stores 1 [bit] information.

One semiconductor region (6) of the memory cell selection MISFET Q is electrically connected to the bit line BL, and the other semiconductor region (6) is an information storage capacitor C
Is electrically connected to one electrode (9) of the
(5) is electrically connected to the word line WL. The other electrode (11) of the information storage capacitor C is a plate wiring PL.
Is electrically connected to

The memory cell array MCA has a plurality of bit lines BL extending in the X direction and a plurality of word lines WL extending in the Y direction. One semiconductor region (6) of each of the memory cell selecting MISFETs Q of a plurality of memory cells M arranged along the extending direction is electrically connected to one bit line BL. In one word line WL, one semiconductor region (6) of each of the memory cell selecting MISFETs Q of the plurality of memory cells M arranged along the extending direction thereof
Are electrically connected.

Next, the specific structure of the memory cell M mounted on the FRAM will be described with reference to FIGS. 2 (plan view of a main part) and FIG. 3 (cross-sectional view taken along line AA shown in FIG. 2). ). In FIGS. 2 and 3, layers above the bit lines BL are omitted for easy viewing.

As shown in FIG. 3, the FRAM mainly comprises a semiconductor substrate 1 having an insulating film 1B formed on a supporting substrate 1A and a semiconductor layer 1C formed on the insulating film 1B. The support substrate 1A is formed of, for example, a p-type semiconductor substrate made of single-crystal silicon, the insulating film 1B is formed of, for example, a thermal silicon oxide film, and the semiconductor layer 1C is formed of, for example, a p-type semiconductor substrate made of single-crystal silicon. . That is, FR
AM is a semiconductor substrate 1 made of SOI (S ilicon O n I nsulator ) structure mainly.

The periphery of the semiconductor layer 1C of the semiconductor substrate 1 is defined by the field insulating film 2 and the insulating film 1B, and is electrically separated from the other semiconductor layers 1C. The field insulating film 2 is formed of, for example, a thermal silicon oxide film.

The memory cell selection MI of the memory cell M
The SFET Q is configured on the main surface of the semiconductor layer 1C of the semiconductor substrate 1. A p-type well region 3 is formed in the semiconductor layer 1C. That is, the MISFET for memory cell selection
Q mainly includes a p-type well region 3, which is a channel forming region, a gate insulating film 4, a gate electrode 5, and a pair of n-type semiconductor regions 6, which are a source region and a drain region.

The gate insulating film 4 is formed of, for example, a thermal silicon oxide film, and the gate electrode 5 is formed of, for example, a polycrystalline silicon film into which an impurity (for example, phosphorus (P)) for reducing a resistance value is introduced. The gate electrode 5 has a word line W extending in the Y direction.
L.

The information storage capacitor C of the memory cell M
Has a structure in which a ferroelectric film 10 whose polarization direction changes along a hysteresis curve is sandwiched between electrodes 9 and 11, respectively. Each of the electrodes 9 and 11 is formed of, for example, a platinum (Pt) film, and the ferroelectric film is formed of, for example, lead zirconate titanate (PZT). The information storage capacitance element C is formed above the memory cell selection MISFETQ as shown in FIGS. 3 and 2 in order to reduce the plane size of the memory cell M.

A bit line BL is electrically connected to one n-type semiconductor region 6 of the memory cell selecting MISFET Q through connection holes 16 formed in the interlayer insulating film 7, interlayer insulating film 12, and interlayer insulating film 15, respectively. It is connected to the. Also,
The other n-type semiconductor region 6 of the memory cell selection MISFET Q is electrically connected to an electrode 9 of an information storage capacitor C through a connection hole 8 formed in an interlayer insulating film 7. The bit line BL is formed of, for example, a polycrystalline silicon film into which impurities are introduced and a silicide film formed on the polycrystalline silicon film. The silicide film is, for example, WSix
It is formed of a film, a TaSix film, a TiSix film, a MoSix film, or the like.

A plate wiring PL is electrically connected to the electrode 11 of the information storage capacitor C through a connection hole 13 formed in the interlayer insulating film 12. The plate wiring PL is fixed to a half of the operating potential Vcc (for example, 3.3 [V]) applied to the bit line BL during the read operation of the memory cell M. The plate wiring PL is formed of, for example, a polycrystalline silicon film into which impurities are introduced and a silicide film formed on the polycrystalline silicon film.

As shown in FIGS. 3 and 2, the plate wiring PL is arranged in the entire area of the memory cell array MCA, and is electrically connected to the electrodes 11 of the information storage capacitance elements C of the plurality of memory cells M. It is connected to the. That is, the plate wiring PL is configured as a common plate wiring. As described above, by configuring the plate wiring PL as a common plate wiring, it is possible to eliminate the separation dimension between the plate wirings as compared with the case where the plate wiring is divided for each bit line. Cell array M
Since the area of the CA can be reduced, the degree of integration of the FRAM can be increased. Note that an opening 14 for electrically connecting one n-type semiconductor region 6 of the memory cell selection MISFETQ and the bit line BL is formed in the plate wiring PL.

In the memory cell selecting MISFET Q, the bottom surface of one n-type semiconductor region 6 electrically connected to the bit line BL has an insulating film 1B formed under the p-type well region 3 (semiconductor layer 1C). Is in contact with Further, the bottom surface of the other n-type semiconductor region 6 electrically connected to the electrode 9 of the information storage capacitor C is in contact with the insulating film 1B formed below the p-type well region 3 (semiconductor layer 1C). ing. That is, the memory cell selecting MISFET Q includes a pair of n-type semiconductor regions 6 serving as a source region and a drain region.
Are formed in a structure in which the respective bottom surfaces are in contact with the insulating film 1B.

In the FRAM thus configured, the memory cell M is changed by changing the potential of the bit line BL.
Is controlled. Hereinafter, the information reading operation of the memory cell M will be described with reference to FIGS.
(Hysteresis curve diagram of ferroelectric film) will be described.

In the initial state, the electric charge of the memory cell M is at the position of the point C or the position of the point A shown in FIG. 7, and each of the bit line BL and the plate wiring PL has a potential of one half of the operating potential. Fixed.

[Reading of Information "0"] First, a selection potential Vch (for example, 5 [V]) is applied to the word line WL, and the potential of the word line WL is raised (MIS for memory cell selection).
After turning on the FET Q), the reference potential Vss (for example, 0 [V]) is applied to the bit line BL to lower the potential of the bit line BL. At this time, the charge of the memory cell M moves from the point A in the initial state to the point B, and is read as information (data) “0”. Next, an operating potential Vcc (for example, 3.3 [V]) is applied to the bit line BL to increase the potential of the bit line BL. At this time, the electric charge of the memory cell M moves from the point B to the point D via the point C. Next, half the operating potential is applied to the bit line BL to lower the potential of the bit line BL. At this time, the charge of the memory cell M moves from the point D to the point A in the initial state. Next, a reference potential is applied to the word line WL to lower the word line WL (MI for memory cell selection).
SFETQ is turned off). Information “0” is read by this series of operations.

[Reading of Information "1"] First, the selection potential Vch is applied to the word line, the potential of the word line is raised (after the MISFET Q for memory cell selection is turned on), and then the bit line BL is applied to the bit line BL. Apply a reference potential to the bit line BL
Lower the potential of. At this time, the charge of the memory cell M moves from the point C in the initial state to the point B, and is read as information (data) “1”. Next, the operating potential Vcc is applied to the bit line BL to lower the potential of the bit line BL. At this time, the potential of the memory cell M moves from the point B to the point C in the initial state. Next, the reference potential Vss is applied to the word line WL, and the word line W
L falls (the memory cell selection MISFET Q is set to O
FF state). Information “1” is obtained by this series of operations.
Is read.

As described above, by fixing the potential of the plate line PL to one half of the operating potential Vcc applied to the bit line BL, the memory cell can be maintained without changing the potential of the plate line PL. The information reading operation of M can be controlled.

The FRAM thus configured is shown in FIG.
As shown in (block diagram), it is mounted on a portable computer system. The portable computer system has a central processor unit 20, which includes a cache memory unit 22, a sub processor unit 23, a memory control unit 24, and a bus unit 25 via an internal bus 21. It is connected.

The bus unit 25 has an I / O bus 2
6, a storage unit 27, a display adapter 28, a keyboard data converter 29, a parallel port interface 30, a serial port interface 31, a floppy disk unit 32, and a hard disk buffer unit 33 are connected to each other.
A hard disk unit 34 is connected to the hard disk buffer unit 33.

The memory control unit 24 is connected to a storage unit 36, an extended storage unit 38, and an extended storage unit 39 via a local bus 35. An auxiliary storage unit 37 is connected to the storage unit 36.

The storage unit 27 has a ROM (Read
OnlyMemory). The storage unit
36, an auxiliary storage unit 37, an extended storage unit 38,
Each of the extended storage units 39 has F to which the present invention is applied.
RAM is mounted.

As described above, according to the present embodiment, the following effects can be obtained.

(1) The information storage capacitance element C in which the ferroelectric film 10 whose polarization direction changes along a hysteresis curve sandwiched between the electrodes 9 and 11 and one n-type semiconductor region 6 are formed. A memory electrically connected to the bit line BL, the other n-type semiconductor region 6 electrically connected to the electrode 9 of the information storage capacitor C, and the gate electrode 5 electrically connected to the word line WL. An FRAM (semiconductor integrated circuit device) provided with a memory cell M formed of a direct circuit with a cell selection MISFET Q, wherein an electrode 1 of the information storage capacitor C is read during an information reading operation of the memory cell M.
1 is fixed to a half of the operating potential Vcc applied to the bit line BL. With this configuration, the information reading operation of the memory cell M can be controlled without changing the potential of the plate wiring PL, so that the plate wiring PL can be configured as a common plate wiring. As a result, the distance between the plate wirings can be eliminated, and the area of the memory cell array MCA can be reduced correspondingly, so that the integration degree of the FRAM (semiconductor integrated circuit device) can be increased.

(2) The MISFET for selecting a memory cell
Each of the pair of Q-type n-type semiconductor regions 6 is formed on a main surface of a p-type well region 3 formed on an insulating film, and at least the information storage capacitor C of the pair of n-type semiconductor regions 6 is formed. The bottom surface of the other n-type semiconductor region 6 electrically connected to the electrode 9 is brought into contact with the insulating film 1B. With this configuration, the area of the pn junction formed by the other n-type semiconductor region 6 and the p-type well region 3 is reduced by an amount corresponding to the area of the bottom surface of the other n-type semiconductor region 6 of the memory cell selecting MISFETQ. As a result, a leak current (junction leak current) flowing from the other n-type semiconductor region 6 to the p-type well region 3 can be reduced, so that a decrease in charges stored in the information storage capacitor C can be suppressed. it can. As a result, the holding time of the charge stored in the information storage capacitor C can be increased, and the number of refresh operations (rewrite operations) of the memory cell M can be reduced. Device) can be reduced in power consumption.

Also, since the power consumption of the FRAM can be reduced, the portable computer system can
Each of the storage unit 36, the auxiliary storage unit 37, the extended storage unit 38, and the extended storage unit 39
When a RAM is mounted, the storage capacity of each of the storage unit 36, the auxiliary storage unit 37, the extended storage unit 38, and the extended storage unit 39 can be significantly increased.

(3) The MISFET for selecting a memory cell
Each of the pair of Q-type n-type semiconductor regions 6 is formed on the main surface of the p-type well region 3 formed on the insulating film, and the bottom surface of each of the pair of n-type semiconductor regions 6 is in contact with the insulating film 1B. Let it. With this configuration, the area of the pn junction formed by the n-type semiconductor region 6 and the p-type well region 3 can be reduced by an amount corresponding to the area of the bottom surface of the n-type semiconductor region 6, and is added to the pn junction. Since the parasitic capacitance can be reduced, the driving power of the memory cell selecting MISFETQ can be increased, and the operating speed of the FRAM (semiconductor integrated circuit device) can be increased.

Further, since the operation speed of the FRAM can be increased, in the portable computer system, each of the storage unit 36, the auxiliary storage unit 37, the extended storage unit 38, and the extended storage unit 39 is provided with the FRAM of the present invention. In the case where is mounted, the processing speed of the portable computer can be increased.

Although the plate wiring PL is configured as a common plate wiring, the electrode 11 of the information storage capacitor C may be configured as a common plate wiring.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, the present invention can be applied to a one-chip microcomputer having an FRAM.

[0056]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

An information storage capacitor in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode, and one semiconductor region is electrically connected to a bit line. The other semiconductor region is electrically connected to the first electrode of the information storage capacitor, and the gate electrode is electrically connected to the word line.
The degree of integration of a semiconductor integrated circuit device provided with a memory cell formed of a direct circuit with an SFET can be increased.

Further, the power consumption of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a main part equivalent circuit diagram of a memory cell array of an FRAM (semiconductor integrated circuit device) according to an embodiment of the present invention.

FIG. 2 is a plan view of a main part of the FRAM.

FIG. 3 is a sectional view taken along a line AA shown in FIG. 2;

FIG. 4 is a waveform diagram for explaining an information reading operation of a memory cell mounted on the FRAM.

FIG. 5 is a block diagram of a portable computer system on which the FRAM is mounted.

FIG. 6 is a waveform diagram for explaining an information reading operation of a memory cell mounted on a conventional FRAM.

FIG. 7 is a hysteresis curve diagram of a ferroelectric film.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 1A ... Support substrate, 1B ... Insulating film, 1C
... semiconductor layer, 2 ... field insulating film, 3 ... p-type well region, 4 ... gate insulating film, 5 ... gate electrode, 6 ... n-type semiconductor region, 7 ... interlayer insulating film, 8 ... connection hole, 9 ... electrode, 10
... ferroelectric film, 11 ... electrode, 12 ... interlayer insulating film, 13 ...
Connection hole, 14: Opening, 15: Interlayer insulating film, C: Capacitance element for storing information, Q: MISFET for selecting memory cell, M ...
Memory cell, MCA: Memory cell array.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Kaneki Oishi 2326, Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Yoshio Sakai Incorporated Hitachi Semiconductor Co., Ltd.

Claims (3)

[Claims] An information storage capacitor in which a ferroelectric film whose polarization direction changes along a hysteresis curve is sandwiched between a first electrode and a second electrode, and one semiconductor region is electrically connected to a bit line. The other semiconductor region is electrically connected to the first electrode of the information storage capacitor, and the gate electrode is electrically connected to the word line.
A semiconductor integrated circuit device having a memory cell comprising a direct circuit with an ISFET, wherein a potential of a second electrode of the capacitor is fixed to a half of an operating potential applied to the bit line. A semiconductor integrated circuit device characterized by the above-mentioned. 2. A semiconductor device according to claim 1, wherein each of the pair of semiconductor regions of the memory cell selecting MISFET is formed of a first conductivity type, and each of the pair of first conductivity type semiconductor regions is formed of a second conductive region formed on an insulating film. A bottom surface of a second conductive type semiconductor region that is formed on a main surface of the type semiconductor region and is electrically connected to at least a second electrode of the information storage capacitor element of the pair of first conductive type semiconductor regions. 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is in contact with said insulating film. 3. A semiconductor device according to claim 1, wherein each of the pair of semiconductor regions of the memory cell selecting MISFET is formed of a first conductivity type, and the pair of first conductivity type semiconductor regions is formed on an insulating film.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed on a main surface of a conductive type semiconductor region, and respective bottom surfaces of the pair of first conductive type semiconductor regions are brought into contact with the insulating film.