JPH0638485B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a one-transistor type dynamic random access memory which realizes a large capacity without increasing a planar area and is suitable for a large scale.

[Background of the Invention]

Since the introduction of a 1 Kb dynamic random access memory (hereinafter abbreviated as dRAM) at the beginning of 1970, the MOS dynamic memory has been quadrupled in size in three years. However, a 16-pin DIP (dual-in-run package) has mainly been used as a package for inserting this memory chip, and the size of the cavity for inserting the chip is also limited. At most, it has increased only 1.4 times. (In addition, since the dRAM is used in a large amount, it is necessary to reduce the cost in terms of cost.) Accordingly, the memory cell area for one bit, which is one storage capacity unit, is also greatly reduced, and is four times as large. As it becomes smaller, it is reduced to about 1/3. Capacitor capacity C is C
= ΕA / Ti (here, ε: dielectric constant of insulating film, A: capacitor area, Ti: insulating film thickness), so area A
Is 1/3, C is also 1 / so long as ε and T are the same.
It will be 3. The signal amount S as a storage capacity is proportional to the stored charge amount Q _S , and since Q _S is the product of C and the storage voltage V _S , the smaller A is, the smaller Q _S is. And the signal S becomes smaller accordingly.

If the noise voltage is N, the signal-to-noise ratio (S / N ratio) becomes smaller as S decreases, which is a serious problem in circuit operation. Therefore, the decrease in A is usually compensated for by the decrease in Ti, and with the increase in the size of 4Kb, 16Kb, 64Kb and dRAM, the typical thickness Ti of the SiO ₂ film as an insulating film is increased. Has become as small as 100 nm, 75 nm and 50 nm.

More recently, heavy metals (U, T
(2) and the like are generated in the Si substrate by α particles emitted from
It has been confirmed that a charge of 00fC is generated, and that this becomes noise, and the charge as a signal amount is approximately 200f in terms of highly reliable operation.
It became difficult to make it C or less.

Therefore, further acceleration of the insulating film to reduce the thickness has been carried out, and in this case, dielectric breakdown of the insulating film has become a problem. Dielectric breakdown voltage field of the SiO ₂ film is at most 10 ⁷ V / cm, SiO ₂ film of the slave connexion 10nm Whether causes little permanent damage Te cowpea to 10V is applied, or degraded. Further, it is a serious problem in terms of long-term reliability that it is used near the maximum electric field even if it does not cause permanent destruction.

[Object of the Invention]

The object of the present invention is to reduce the size of α associated with miniaturization of these memory cells.
A method capable of maintaining or increasing the capacitor area A without reducing the insulating film thickness even if the memory cell is miniaturized, by coping with the disturbance due to particles, the deterioration of the S / N ratio, and the aggravation of the withstand voltage problem. Is to provide.

[Outline of Invention]

The essence of the present invention is that a capacitor electrode formed on an insulating film such as SiO ₂ has a recessed shape (for example, a comb shape,
By forming holes and grooves), it is possible to increase the electrode area without increasing the plane area. As a result, the desired capacitance can be obtained without making the insulating film thinner and increasing the risk of the insulating film being broken or deteriorated.

Example of Invention

FIG. 1 is a block diagram of a one-transistor type dRAM memory cell, which is composed of a capacitor 1 for storing charges and a switch transistor 2, the drain of the switch transistor is connected to a bit line 3, and the gate is a word line. 4 is connected.

This memory cell operates by reading out the signal charge stored in the capacitor 1 by means of the switch transistor 2. In order to actually construct an N-bit memory, a memory array is formed, but there are roughly two methods described below.

FIG. 2 shows a so-called "open bit line" configuration in which bit lines 3-1 and 3-2 are arranged on both sides of a sense amplifier 5 for differentially amplifying a signal. This is one word line 4
Only one bit line 3-1 is electrically crossed with respect to -1, and the difference between the signals on the bit lines 3-1 and 3-2 is detected by the sense amplifier 5.

FIG. 3 shows the other "folded bit line" configuration, in which two bit lines 3-1 and 3-2 connected to the sense amplifier 5 are arranged in parallel and one word is formed. Line 4-1 intersects with two bit lines 3-1 and 3-2.

Although the embodiments of the present invention described later mainly show the case of the folded bit line structure, they can be similarly applied to the open bit line structure.

As shown in FIGS. 2 and 3, if the value of the parasitic capacitance 6 of the bit line 3-2 is C _D and the value of the capacitor 1-2 of the memory cell is C _S , the main performance of this memory array is shown. One of the indexes is C _S / C _D. The S / N ratio of this memory array has a one-to-one correspondence with C _S / C _D, and it is also possible to increase the capacitance of the memory cell and at the same time decrease the parasitic capacitance C _D of the bit line 3. The S / N ratio will be improved.

FIG. 4 shows an example of a plane of a folded bit line type memory cell. A part of the active region 7, which is usually surrounded by a thick field oxide film of 100 nm or more, forms a capacitor, and is therefore covered with a plate 8. The plate 8 is selectively removed from the portion forming the switch transistor and the portion of the contact hole 9 on the Si substrate for connecting the drain heavy line electrode, and word lines 4-1 and 4- are formed in this portion.
2 is deposited to form the switch transistor 2. To facilitate understanding, FIG. 5 shows a sectional view taken along the line AA 'of FIG.

For convenience of description, an example using an n-channel type transistor is shown below. In order to obtain the p-channel type, generally, the conductivity types of the Si substrate and the diffusion layer may be reversed from those of the n-channel type.

The conventional memory cell shown in FIG. 5 is a p-type, 10 Ω-cm.
A field-effect SiO ₂ film 11 having a thickness of about 100 to 1000 nm is selectively deposited on the Si substrate 10 of about 10 nm by the so-called LOCOS method using Si ₃ N ₄ as a thermal oxidation mask. Thereafter phosphorus and A _S added polycrystalline Si (hereinafter poly S
a plate 8 represented by abbreviated i) is selectively attached,
The poly Si plate 8 is oxidized to form a first interlayer oxide film 13. Thereafter, deposited word line 4 typified by poly Si or M _O silicide or refractory metal, (M _O, W, etc.), the phosphorus or A _S to the ion implantation, deposition of the plate 8 and the word lines 4 An n ⁺ diffusion layer 15 is formed in the active region which is not formed to serve as the source and drain of the switch transistor 2. After this, PSG (Phosoho Silicate) containing phosphorus by so-called CVD method
Glass) to a thickness of 200 to 1000 nm to form a second interlayer insulating film 14, and a contact hole 9 is formed at a portion for connecting the bit line 3 typified by an Al electrode to the diffusion layer 15. 3 is selectively applied.

In this memory cell, the region 16 of the capacitor 1 which becomes the storage capacity is the shaded portion in FIG. 4, and the region 16 becomes smaller as the memory cell itself becomes smaller, unless the gate oxide film 12 is made thinner. As described above, the capacitance C _{S of the} capacitor becomes small, which is a great obstacle to the memory operation.

In the above description, the insulating film under the plate 8 and the word line 4 (that is, the gate of the switch transistor 2) is the same SiO ₂ film 12 for the sake of convenience, but the main purpose is to increase the value C _S of the capacitor of the memory cell. The insulating film below the plate 8 may be an insulating film having a one-layer to _three- layer structure using one or both of SiO ₂ and Si ₃ N ₄ .

It is an object of the present invention to compensate for the drawbacks of the above-described conventional structure and increase C _S without increasing the plane area.

The present invention will be described in detail below with reference to examples. First 6th
The figure shows a plan view of one embodiment of the invention. The difference from the conventional memory cell shown in FIG. 4 is that the capacitor region is not formed on the surface of the Si substrate 10 and is constituted by the capacitor electrode 19 and the plate 8 deposited on the insulating film. There is a point. A sectional view taken along the line AA shown in FIG. 6 is shown in FIG. This feature is that the capacitor electrode 19-1 is connected to the diffusion layer 15 corresponding to the word line 4-1 through the capacitor electrode connection hole 20.

Further, the capacitor electrode 19 does not have a simple rectangular shape as shown in FIG. 6, but has at least one recessed portion in a plane. For example, FIG. 8 shows the shape of the capacitor electrode 19 having two recesses and having a shape. Due to this recess, the surface area of the capacitor electrode 19 is increased, and the value C _S of the memory cell capacitor can be increased without enlarging the plane dimension of the memory cell, and the S / N ratio can be improved.
Further, not only the comb-shaped capacitor electrode 19 but also the capacitor electrode 19 having a recess at the center as shown in FIG. 9 can similarly increase the C _S corresponding to the increase in the surface area.

That is, the capacitor electrode 19 has a shape having a recess in plan view on the main surface of the Si semiconductor substrate 10, and the capacitor electrode 19 has a certain thickness as shown in FIGS. 8 and 9. The recess is formed so as to have a predetermined depth in the thickness direction of the capacitor electrode 19, and as a result, the sidewall of the recess is substantially perpendicular to the main surface of the semiconductor substrate,
The capacitance between the capacitor electrode 19 and the plate 8 can be increased without increasing the planar size of the memory cell.

That is, by forming the concave portion of the capacitor electrode 19 in the above-described shape, the capacitor is divided by the product of the increase in the peripheral distance of the electrode due to the concave portion formed on the capacitor electrode 19 in a plane and the depth of the vertical side wall of the concave portion. The opposing area between the electrode 19 and the plate 8 is increased, and the capacitance value C _S of the memory capacitor of the memory cell can be increased without increasing the plane size.

In the embodiment of the present invention shown in FIGS. 6 and 7, the channel of the switch transistor 2 is formed on the surface of the Si substrate 10. However, a Si crystal in which the switch transistor is formed on an insulating film, a so-called SOI ( Silicon On Ins
ulaton). 10 and 11 show another embodiment of the present invention.

In this embodiment, the switch transistor and the capacitor region 1
6 are both formed in a Si crystal formed on the substrate insulating film 17 formed on the Si substrate 10, preferably a single crystal.
As a result, the carrier is not affected by noise as noise generated by, for example, α-rays or defects in the Si substrate.

The manufacturing process of the semiconductor memory according to the present invention will be described in detail below. First, as shown in FIG. 12, n or p type Si
The substrate 10 has a SiO ₂ film or Si ₃ film with a thickness of 10 to 1000 nm.
A single layer of N ₄ film or a multilayer film 17 is deposited on the entire surface. After this,
Amorphous or polycrystalline Si as a whole or S that is partly single crystallized
i of 100 to 1000 nm is well known SiH ₄ and SiH ₂ Cl
₂ Adhere using gas. After that, the entire Si substrate 10 is kept at a predetermined temperature from room temperature to 1000 ° C., and CW-
15 ~ with energy of 5 ~ 10W using Ar laser
When the spot of 30 .mu.m.phi. Is irradiated on the entire surface of the above-mentioned polycrystalline Si film at a scanning speed of 10 to 50 cm / sec, an epitaxial layer (SOI layer) 27 on the insulating film is obtained.

Here, an example in which laser annealing using a so-called CW laser is used is shown, but in the end, the channel portion 24 of the switch transistor 2 only needs to be a single crystal,
Besides the laser annealing method, any method such as annealing using a carbon heater or annealing using an electron beam can be used.

Although not shown in FIG. 12, if a part of the Si film having the SOI structure is brought into contact with the Si substrate 10, single crystallization can be easily performed, which is a great advantage.

In the present invention, the method of growing single crystal Si on the insulating film is not limited.

After that, as shown in FIG. 13, etching is performed by well-known photolithography so that at least a portion forming a switch transistor is left, and unnecessary S is removed.
Remove the OI layer.

For this etching, any method of etching Si can be used. Solution etching of HF-HNO ₃ system, plasma etching having CF ₄ or SF ₆ gas as a main component, or anisotropic etching using KOH or hydrazine having a slow (111) plane etching speed can be performed. it can. Especially, this anisotropic etching is
When the upper surface of the I layer 17 is the (100) plane, it is formed into a trapezoid with a wide lower end at an angle of about 55 degrees (the angle formed by the (100) plane and the (111) plane). Part of the
It has an advantage that various films deposited thereon can be easily formed.

Further, the SOI layer has a resistivity of 1 to 20 Ω by the ion implantation method and the annealing method so that it is suitable for forming an n-channel transistor.
Be sure to have −cm.

Previously forming a Kiyapashita electrode 19 A _S and phosphorus ion implantation and thermal diffusion in subsequent portions to be Kiyapashita electrode.

After that, a single layer of SiO ₂ or Si ₃ N ₄ , a composite film thereof, or a capacitor insulating film 18 typified by Ta ₂ O ₅ is deposited.

Further, a plate 8 of polycrystalline Si added with _AS or phosphorus is selectively deposited and oxidized by a dry or wet oxidation method at 800 to 1100 ° C. to form a first interlayer insulating film 13 of 100 to 200 nm.
To form.

Then, as already shown in FIG. 11, Sui Tutsi in part to form the transistor 2 to form a gate oxide film 12 of 10~50nm thickness more poly Si or M _O silicide thereon or M _O, such as W, The gate (word line 4) is deposited. Implanted A _S like in the subsequent ion implantation, n
^{A +} diffusion layer 15 is formed.

Further, a second interlayer insulating film 14 typified by CVDPSG is deposited to form a contact hole 9 to the n ⁺ diffusion layer 15, and a bit line 3 typified by Al is deposited.

By doing so, the capacitor 1 is formed by the capacitor insulating film 18, two electrodes sandwiching the capacitor insulating film 18, that is, the capacitor electrode 19 and the plate 8.

Further, the planar shape of the plate electrode 19 is already shown in FIGS.
It is similar to that shown in the figure.

In this embodiment, the desired portion of the SOI portion on the entire surface is monocrystallized and the unnecessary portion is removed. However, polycrystalline Si is deposited on the entire surface, and the unnecessary portion is removed first, and then the above-mentioned laser annealing or the like is performed. It is also possible to crystallize a desired portion into a single crystal.

Further, although the method of removing the unnecessary SOI portion is used in the present embodiment, there is a method of changing a part of the unnecessary portion to an oxide film as in another embodiment of the present invention shown in FIG. That is, an underlying SiO ₂ film having a thickness of 1 to 50 nm is formed in a necessary portion, and a LOCOS mask Si ₃ N ₄ film having a pressure of 50 to 200 nm is selectively deposited.

Wet oxidation at 800-1100 ° C as shown below
A desired SOI field oxide film 21 is obtained. At this time S
The OI field oxide film 21 covers the entire SOI layer 23 with Si.
When the O ₂ film is not used, Boron is ion-implanted into a channel stopper by using the Si ₃ N ₄ film as a mask, as in the well-known LOCOS method. afterwards
By removing the Si ₃ N ₄ film and the SiO ₂ film, a structure as shown in FIG. 14 is obtained. In this embodiment, since the unnecessary SOI layer is replaced with an oxide film, the step is smaller than the case where the unnecessary SOI layer is removed, which is advantageous not only for forming various films deposited thereon, but also for the field SiO ₂ film. Since there is 32, there is an advantage that the parasitic capacitance between the underlying plate 8 and the Si substrate 10 becomes small.

Further, the capacitor electrode 19 of the present invention constitutes a capacitor at the portion facing the plate 8. However, if the insulating film 17 on the substrate is thinned, the capacitor with the Si substrate 10 can be added to further increase C _S. . In this case, the p-type resistivity of the Si substrate 10 is made extremely low so that an inversion layer and a depletion layer are not formed on the surface of the Si substrate and the effect of increasing the capacitance is reduced when the capacitor electrode 19 has a positive voltage. Alternatively, it may be of n-type.

In addition, the present invention, as described at the beginning, has an n-channel type M.
Although the description has been made using the OS transistor, the p-channel type can be achieved by using impurities that reverse the conductivity types of all the impurities. Phosphorus or A _S may be replaced with B or Al, and B may be replaced with phosphorus, A _S , Sb, or the like.

〔The invention's effect〕

According to the present invention, the capacitance C of the capacitor can be reduced with a small memory cell.
_S can be increased.

malfunction of Dyna honey click memory by α-rays, C _S is 10
Even if it increases by%, it is often improved by one digit or more, so C _S
More than double, not only increases the reliability of the memory of that scale, but also enables realization of a larger scale memory.

Further, in the present invention, a large amount of electron-hole pairs generated in the Si substrate due to α rays rarely directly flow into the capacitor electrode, and particularly in the case of using SOI, it does not flow at all. It has strong characteristics against α rays.

[Brief description of drawings]

1 to 5 are views for explaining a conventional memory cell, and FIG.
FIG. 14 to FIG. 14 are views showing an embodiment of the present invention. 1 ... Capacitor, 2 ... Switch transistor, 3 ...
... bit line, 4 ... word line, 5 ... sense amplifier, 6
... parasitic capacitance, 7 ... active area, 8 ... plate, 9 ...
Contact hole, 10 Si substrate, 11 field oxide film, 12 gate oxide film, 13 first interlayer insulating film, 14 second interlayer insulating film, 15 diffusion layer, 16
...... Capacitor area, 17 ...... Insulating film on the substrate, 18 ......
Capacitor insulating film, 19 ... Capacitor electrode, 20 ...
Capacitor electrode connection hole, 21 ... SOI field oxide film, 23 ... SOI part, 24 ... Transistor channel part.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kikuo Kusukawa 1-280 Higashi Koikeku, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Masanobu Miyao 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Co., Ltd. Central Research Laboratory (72) Inventor Mitsunori Warabi, 1-280, Higashi Koikekubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP 55-19820 (JP, A) JP 54-54588 ( JP, A)

Claims (10)

[Claims] 1. A semiconductor substrate and a first shape having a desired shape formed on a surface of the semiconductor substrate.
An insulating film, a switching element formed on the substrate and formed of a field effect transistor having a gate electrode, a bit line electrically connected to the drain of the transistor, and a gate electrode of the transistor electrically connected to the bit line. The connected word line, the capacitor electrode formed on the first insulating film and electrically connected to the source of the transistor, the second insulating film formed on the surface of the capacitor electrode, and the second insulating film. In a semiconductor memory having a plate formed on the surface of an insulating film, the capacitor electrode has a predetermined thickness on the main surface of the semiconductor substrate and has a recess formed in at least the central portion thereof. A sidewall of the recess is substantially vertical to the main surface of the semiconductor substrate, and a capacitor is formed on the sidewall that is substantially vertical. And semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the second insulating film is a single layer film. 3. The semiconductor memory according to claim 1, wherein the second insulating film is a multilayer film. 4. The semiconductor memory according to claim 3, wherein the multilayer film is a three-layer film containing SiO ₂ . 5. The semiconductor memory according to any one of claims 1 to 4, wherein the capacitor electrode is made of polycrystalline Si. 6. The semiconductor according to claim 1, wherein the word line is made of polycrystalline Si, Mo silicide or refractory metal, and the bit line is made of Al. memory. 7. The semiconductor memory according to any one of claims 1 to 6, wherein the number of recesses provided in the capacitor electrode is two. 8. The transistor according to any one of claims 1 to 7, wherein the transistor is formed on a surface of a single crystal semiconductor formed on the first insulating film. Semiconductor memory. 9. The semiconductor memory according to claim 1, wherein the semiconductor memory is formed in a folded bit line system. 10. The semiconductor memory according to claim 1, wherein the semiconductor memory is formed in an open bit line system.
9. The semiconductor memory according to any one of items 8 to 8.