JPH03259549A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To minimize the alteration in layout when a logic circuit is additionally required after finishing the layout by a method wherein the logic circuit built-in a passage cell is substituted for the logic circuit additionally required after finishing the layout. CONSTITUTION:Within a plan illustration displaying a feed-through cell in a semiconductor integrated circuit designed in cell base mode, the cell lines not adjacent to one another can be connected by wiring Al wirings 5a, 5b for connecting the second layer wirings to the upper layer of the feed-through cell 20 without electrically connecting power supply lines 2 and GND lines 3 of the first layer wiring. Through these procedures, a spare inverter is formed in the feed-through cell 20. On the other hand, when a logic circuit is additionally required after finishing a layout by an automatic arrangement wiring, the spare inverter formed in the feed-through cell 20 is to be used. Accordingly, any inverter in high application frequency can be additionally required without the alteration in the layout.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit formed by arranging and wiring a plurality of standard cells having logical functions.

[Conventional technology]

FIG. 3 shows a feed-through cell 10 provided for connecting non-adjacent cell rows in a conventional semiconductor integrated circuit designed using a cell-based method in which a plurality of standards having logical functions are placed and routed. FIG. As shown in the figure, within the cell frame 1, power supply lines 2 and GND lines 3 of the first layer wiring extend in the column direction, and there is nothing in the transistor formation region 4 between the power supply lines 2 and 2 and the GND lines 3. Not formed.

In the upper layer of the feed-through cell 10 having such a configuration, an AI wiring 5 for connecting the second layer wiring is connected in the column direction without being electrically connected to the power supply line 2 and the GND line 3 of the first layer wiring. Can be wired vertically. Therefore, the fourth
As shown in the figure, connection between non-adjacent cell rows 6 and 7 can be made by A2 wiring 5 through feed-through cells 10 formed in cell row 8.

[Problem to be solved by the invention]

However, in semiconductor integrated circuits designed using the conventional cell-based method, if it becomes necessary to add logic circuits after the layout has been completed using automatic placement and routing, the logic circuits can be added by changing the layout, and There was a problem in that the wiring had to be changed as well, which required a major layout change.

This invention was made to solve the above-mentioned problems, and it provides a cell-based semiconductor integrated system that can minimize layout changes when it becomes necessary to add logic circuits after layout is completed. The purpose is to obtain a circuit.

[Means to solve the problem]

The semiconductor integration device according to the present invention is formed by arranging and wiring a plurality of standard cells each having a logic function, and a spare logic circuit is built into a passing cell used for connecting non-adjacent cell rows. There is.

[Effect]

In this invention, since a spare logic circuit is built into the pass-through cell used for connecting non-adjacent cell columns,
If the logic circuit that needs to be added after the layout is completed is a logic circuit built into the pass-through cell, it can be used.

〔Example〕

FIG. 1 is a plan view showing a feed-through cell 20 in a semiconductor integrated circuit designed using a cell-based method, which is an embodiment of the present invention. As shown in the figure, cell frame 1
The power supply line 2 and the GND line 3 of the first layer wiring extend in the column direction, and the transistor formation region 4 between the power supply line 2 and the GND line 3 includes a P' diffusion region 11, a N' diffusion region 12, and a polygon. The silicon gate electrode layer 13 and the first
A power line 14 and an output line 15 consisting of layer wiring are formed, and these areas 11, 12, 13, input line 14 and output line 1 are connected to each other.
5 through the contact hole 16, a frequently used inverter is constructed. However, in this formation state, the human power line 14 is connected to the power supply line 2 to fix the human power level, and the output line 15 is floating, so the inverter does not perform its original function and the transistor forming area 4 is This is equivalent to the conventional feed-through cell 10 in which nothing is formed.

Therefore, in the upper layer of the feed-through cell 20 in this formed state, AfI wirings 5a and 5b for connection of the second layer wiring are placed without being electrically connected to the power supply line 2 and the GND line 3 of the first layer wiring. By wiring, it is possible to connect non-adjacent cell columns as in the conventional case. In this way, a spare inverter is formed in the field through cell 20.

On the other hand, after the layout is completed by automatic placement and routing,
When it becomes necessary to add a logic circuit, if the logic circuit has an inverter, the spare inverter formed in the field-through cell 20 is used. That is, as shown in FIG. A1 wiring 5a
By electrically connecting the output [15 and the Af1 arrangement device [5b], an original inverter can be configured in the feed-through cell 2o, with the A1 wiring 5a as the inverter input line and the A1 wiring 5b as the inverter output line. .

In other words, when additional inverters are formed after the layout is completed, the feed-through cells 20 can be formed without changing the layout.
It is only necessary to perform a simple wiring change process such as a wiring cutting process and a contact hole forming process. Therefore, even if there is a request to add a frequently used inverter after the layout is completed, the inverter can be added without suddenly changing the layout.

In this embodiment, an inverter is built in the feedthrough cell 20, but the inverter is not limited to this, and it can also be used for a NAND circuit, an O
Other logic circuits such as an R circuit may also be incorporated.

〔Effect of the invention〕

As explained above, according to the present invention, spare logic circuits are built into the pass-through cells used to connect non-adjacent cell rows, so logic circuits that need to be added after the layout is completed can be added to the pass-through cells. If there is a logic circuit built into the cell, it can be used. Therefore, by incorporating frequently used logic circuits in the pass-through cells, it is possible to minimize layout changes when it becomes necessary to add logic circuits after the layout is completed.

[Brief explanation of drawings]

1 and 2 are plan views showing a feed-through cell of a semiconductor integrated circuit which is an embodiment of Hoko's invention, FIG. 3 is a plan view showing a feed-through cell of a conventional semiconductor integrated circuit, and FIG. 4 is a plan view showing a feed-through cell of a conventional semiconductor integrated circuit. FIG. 2 is an explanatory diagram showing the function of a feed-through cell. In the figure, reference numeral 4 indicates a transistor formation region, and 5a. 5b is A (wiring, 11 is a P+ diffusion region, 12 is an N" diffusion region, 13 is a polysilicon gate electrode layer, 14 is a human power line, 15 is an output line, and 16 and 17 are contact holes. The same reference numerals in the middle indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A semiconductor integrated circuit formed by arranging and wiring a plurality of standard cells having a logic function, characterized in that a spare logic circuit is built into a passing cell used for connecting non-adjacent cell rows. Semiconductor integrated circuit.