JPH1041393A - Semiconductor standard cell and method for layout and wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor standard cell which has an excellent noise-proof property and also provide a method for arranging and wiring the cells by which all the power lines can be connected to each other inside the cells just by locating the cells. SOLUTION: This semiconductor standard cell 2 has a logic gate section 8, power lines 4 which are connected to each other between the cells which are adjacent in the wiring direction and which supply supply voltage to the logic gate section 8, and power supply bridge lines 18 which are constituted of interconnect layers of different level from the power lines and which are connected to the power lines at right angles with them inside the cell. In this layout and wiring method, a plurality of the semiconductor standard cells 2 are located adjacently to each other in the direction at right angles with the wiring direction of the power lines 4. In a logic IC wherein such cells 2 are located suitably, no peripheral space is necessary for connecting the power lines to each other which has been necessary in conventional methods and the device does not malfunction even if where is a fluctuation in voltage level due to noise which is caused by applying the supply voltage evenly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor standard cell and a method of arranging and wiring the same, and more particularly, to a standard cell structure in which all power supply lines can be interconnected in a cell arranging region, and a layout method thereof.

[0002]

2. Description of the Related Art The standard cell system, which is one of the LSI design systems, has the advantage that the wiring and gates can be effectively used, the cell size can be reduced, and high performance can be easily obtained as compared with the gate array system. . This cell method has been used for a logic circuit in which cells of different types are irregularly arranged according to the circuit configuration, such as a control circuit. The standard cell method has come to be frequently used for logic circuits in the arrangement.

FIG. 8 is a block layout diagram showing a power line connection relationship in a conventional standard cell type logic circuit in which cells are regularly arranged. In the conventional logic circuit shown in FIG. 8, cell rows having the same configuration are repeatedly arranged. That is, in this example, cells are arranged in the horizontal direction in the order of A, B, C, D, E, A, E, F, B, and A to form a cell row.
Here, three stages are provided.

Here, symbols A to F in a cell are, for example, A
The types of logic gates, such as ND gates, inverters, latches, flip-flops, etc., are shown. Each cell is, for example, a CMO
S. FIG. 9 shows a cell pattern diagram of an AND gate as a configuration example of a conventional standard cell. Above and below the cell 40, a power supply voltage supply line 42, GND
The lines 44 (hereinafter collectively referred to as “power supply lines”) are each wired with the first layer metal. This power line 42,
The wiring direction of 44 is the same for other types of logic gates (inverters, latches, flip-flops, etc.).

A plurality of transistors are arranged in a region between the power supply voltage supply line 42 and the GND line 44, and are connected to each other by a first layer metal or a second layer metal.
A desired logic gate (here, an AND gate) is configured. Normally, a p-channel transistor is arranged on the side near the power supply line 42 and n
A channel transistor is provided. An input terminal 46 and an output terminal 48 for connecting a signal line between cells are arranged near the center of the cell using, for example, a second-layer metal.

As shown in FIGS. 8 and 9, in a conventional standard cell 40, power supply lines 42 and 44 are wired only in one direction, and power supply lines 42 and 4 are provided between cells arranged in that direction.
4 are connected in series. When there are three cell columns as in the illustrated example, the power supply lines 4 connected in series
2 and 44 are connected to each other in the vertical direction by using, for example, a second metal layer 50 outside the cell arrangement region.

[0007]

However, when block layout is performed using the conventional standard cell 40, a region for interconnecting the power supply lines 42 and 44 is required outside the cell arrangement region. However, this region exists as a useless region in terms of high integration. Also,
As the scale of the block layout becomes larger and the cell column becomes longer, the power supply voltage and the GND at the both ends of the cell where the power supply lines 42 and 44 are connected to each other and the cell at the center are accordingly increased.
The manner in which the potential is applied becomes non-uniform, and this may degrade the noise resistance of the entire logic circuit. Therefore, when the conventional standard cell 40 is used, it is necessary to secure the operation margin of each standard cell by increasing the transistor size or the like, which also hinders high integration.

The present invention has been made in view of such circumstances, and all power supply lines can be interconnected only by arranging standard cells, and a peripheral area for interconnection of power supply lines is unnecessary, and noise resistance is improved. It is an object of the present invention to provide a semiconductor standard cell having an excellent structure and a method of arranging and wiring the same.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and to achieve the above object, the semiconductor standard cell and the method of arranging and wiring the same according to the present invention provide not only the wiring direction of the power supply line, but also the following. The interconnection of the power supply lines in a direction orthogonal to this is performed inside the cell arrangement region using a wiring layer of a different hierarchy from the power supply lines.

That is, the semiconductor standard cell of the present invention comprises a logic gate portion, a power supply line interconnected between cells adjacent in the wiring direction and supplying a power supply voltage to the logic gate portion, and a power supply line having a different level from the power supply line. It is configured using a wiring layer,
A power supply bridging line connected to the power supply line in the cell and connected to the power supply line at right angles to each other so as to be mutually connected between cells adjacent in the direction orthogonal to the power supply line. It is characterized by.

Further, in the method for arranging and wiring semiconductor standard cells of the present invention, a plurality of semiconductor standard cells having the above-described configuration are arranged adjacent to each other in a direction orthogonal to the wiring direction of the power supply lines and connected in the wiring direction. The power supply lines are connected to each other within the cell arrangement region.

When a cell row having the same configuration is repeated in a plurality of stages, as a preferable cell configuration, a power supply bridging line connected to a power supply line is preferably wired in a direction orthogonal to the power supply line in the logic gate portion. In this case, since the same cells are arranged in the direction orthogonal to the cell row, the power supply bridges are connected in series through the semiconductor standard cells having the power supply bridges. The columns of the connected power supply lines are also connected to each other in a direction orthogonal to the cell columns.

Further, even when the cells are arranged irregularly, the power supply bridging line is provided by using a semiconductor standard cell which is wired from the connection point with the power supply line to the outside of the cell. Power supply lines can be connected to each other between two cells that are orthogonal to the direction. Then, by connecting the power supply lines between the two cells at different levels, or by combining the power supply bridging lines with the cells penetrating the logic gate portion, all the power supply lines are connected as the entire cell arrangement region. It is possible to do so.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor standard cell and a method of arranging and wiring the same according to the present invention will be described in detail with reference to the drawings. The present invention is applied to a semiconductor device in which a logic circuit is designed by a standard cell method. Here, the “standard cell method” refers to a plurality of types of logical circuit function blocks in which the types of block sizes, the positions of power supply lines and signal lines from which terminals are drawn out based on physical layout information, and the like, are used as a library. A method of designing a semiconductor circuit that prepares in advance, arranges these circuit function blocks based on a netlist (connection information), and connects them to form a desired logic circuit. Also,
The “standard cell” refers to each circuit function block used for the standard cell circuit design.

In general, in the standard cell system, the circuit function blocks are arranged on the same plane, and the power lines of all the circuit function blocks can be formed using the same level of wiring layers. As a result, there is a building block system in which power supply lines can be configured using wiring layers of different levels even with the same type of circuit function block. The semiconductor standard cell and the method of arranging and wiring the same according to the present invention can be applied to both the polycell system and the building block system.

Hereinafter, a specific embodiment of the present invention will be described by taking a polycell system as an example. First Embodiment FIG. 1 is a cell pattern diagram of an AND gate showing one configuration example of a semiconductor standard cell of the present invention. In the semiconductor standard cell 2, a power supply voltage supply line 4 and a GND line 6 (hereinafter, also collectively referred to as “power supply line”) are wired in the first layer above and below the cell. . The wiring directions of the power supply lines 4 and 6 are different from those of other circuit functions (inverters, latches, flip-flops, etc.).
As in the case of the semiconductor standard cell having the above, it is determined in one direction based on physical layout information, and its wiring width and terminal lead-out position are ruled.

In the present invention, a region between the power supply voltage supply line 4 and the GND line 6 is referred to as a logic gate portion. In the logic gate portion 8, a plurality of transistors are arranged. And a second-layer metal to form a desired logic gate (here, an AND gate).

That is, a p-type transistor region 10 into which an n-type impurity is introduced is arranged on the side closer to the power supply line 4 in the logic gate portion 8, and conversely, a p-type transistor region on the side closer to the GND line 6 is N-type transistor region 12 into which impurities are introduced
Is arranged. Then, the p-type transistor region 10
Above the first-layer metal, a source or drain electrode is formed, and a gate metal is arranged within the interval, whereby a plurality of p-channel transistors are arranged. Similarly, a plurality of n-channel transistors are arranged in the n-type transistor region 12. In the vicinity of the center between the power supply lines 4 and 6, two input terminals 14 and output terminals 16 of the AND gate are arranged side by side in the horizontal direction. In this figure, these input / output terminals 14 and 16 are configured using a second-layer metal.

Up to this point, the structure is the same as that of the conventional standard cell shown in FIG. 9, but the standard cell 2 of the present invention has a contact 18a connected to one of the power supply lines (the GND line 6 in FIG. 1). And a power supply bridge line 18 connected in a direction orthogonal to the wiring direction of the power supply lines 4 and 6,
It is newly provided. The power supply bridge line 18 is formed of a wiring layer (for example, a second-layer metal) of a different hierarchy from the power supply lines 4 and 6, and in the present embodiment, is wired so as to penetrate the logic gate unit 8 in the vertical direction. I have. FIG. 2 shows the connection relationship between the power supply bridge line 18 and the power supply lines 4 and 6 extracted from FIG.

In the present invention, various modifications are conceivable for the wiring configuration of the power bridge 18. That is, the power supply bridge line 18 may be connected to the power supply voltage supply line 4 via the contact 18b as shown in FIG. 3, or may be connected to the power supply voltage supply line 4 and the GND line 6 as shown in FIG. Two power supply bridge lines 18 to be connected may be provided. Further, as shown in FIG. 5, the power supply bridge line 18 may be formed wide so as not to hinder the arrangement of the input / output terminals 12 and 14. Further, although not particularly shown, the power supply bridge line 18 may be formed using a wiring layer (for example, a third-layer metal) on an upper layer side. In this case, the power supply bridge line 18 is superimposed on the input / output terminals 14 and 16. It may be wired.

Next, an arrangement and wiring method according to the present invention performed using the semiconductor standard cell having such a configuration will be described. FIG. 6 is a block layout diagram showing the connection relationship of the power supply lines in the standard cell type logic circuit according to the present embodiment. In this arrangement and wiring method, cells having different types of circuit functions are arranged in one direction (horizontal direction in the drawing) in a predetermined pattern to form a cell row, and the cell rows are arranged in a plurality of stages (three stages in this drawing). Thus, the entire logic circuit is configured. In the figure, the symbols A to F mean that the circuit functions of the cells are different. As a specific example of such a regular cell arrangement, for example, a data path block constituting an arithmetic unit in a CPU can be cited. In this case, each bit is assigned to each cell column.
The direction of the cell rows coincides with the wiring directions of the power supply lines 4 and 6 in FIG. 1, and when the respective cell rows are formed, the power supply lines 4 and 6 are connected in series in the cell row.

In the placement and routing method of the present invention, the above-described semiconductor standard cells of the present invention are appropriately placed in each cell column, so that the interconnection of the power supply lines 4 and 6 between each cell column is made within the cell placement region. Has been achieved. That is, in this illustrated example, the standard cell 2 having the same configuration as that of FIG. 2 described above, the standard cell 20 having the same configuration as that of FIG. 3, and the standard cell 22 having the same configuration as that of FIG. Have been. For this reason, three power supply voltage supply lines 4
Are connected to each other via standard cells 20 and 22, and the three GND lines 6 are connected to each other via standard cells 2 and 22.

As is apparent from the above, when designing a logic circuit having a regular cell arrangement, the power supply bridge 18
The semiconductor standard cell 2, 20,
The libraries 22 and 24 are prepared in advance as a library, and the positions of the cells 2, 20, 22 and 24 for power supply interconnection to be arranged in the cell row are determined. Thereafter, the cells are arranged as usual. Alone, the power supply lines 4 and 6
Can be realized.

According to the semiconductor standard cell and the method of arranging and wiring the same according to the present invention, a space for interconnecting the power supply lines 4 and 6 is provided in the cell arranging area as in the case of using the conventional standard cell shown in FIG. There is no need to secure specially the surroundings, and high integration can be achieved by that much.

Further, since the power supply lines 4 and 6 can be interconnected in the middle of the cell row, a power supply point of the power supply voltage and a connection point of the GND can be appropriately provided in the middle of the cell row. Noise design becomes easy. That is,
For example, the present embodiment shown in FIG.
8 is the same as that in FIG. 8 in that two vertical lines each sharing D are provided, but in the present embodiment in FIG. 6, this is provided in the cell arrangement region. As compared with FIG. 8, the manner in which the power supply voltage (including the GND potential) is applied to each cell is uniform, and even if the power supply voltage level fluctuates due to noise, this level fluctuation The influence on the operation of the logic circuit is reduced. Depending on the arrangement pattern of each cell column, as many power supply bridge lines 18 as possible between the cell columns can be arranged, so that even better noise immunity can be achieved, and the degree of freedom in noise immunity design is large. .

The above means that there is no problem even if the noise margin is reduced when designing each cell.
Since there is no need to take measures to increase the transistor size in consideration of the noise margin, this point can also contribute to high integration.

Second Embodiment In the above-described first embodiment, the present invention is applied to a logic circuit design having a regular cell arrangement. As a result, in the entire logic circuit shown in FIG. It was formed in a single line. On the other hand, the second embodiment shows that the present invention can be applied even when the cell arrangement is irregular.

FIG. 7 is a block layout diagram according to the second embodiment. Also in this layout example, as for the logic gates C and E, as in the first embodiment, the layout space of the power supply bridge line 18 is easily secured and the like.
This is realized by semiconductor standard cells 2, 20 and 22 having a power supply bridge 18 penetrating the logic gate section 8.

Particularly, in the layout example according to the second embodiment, unlike the first embodiment, the power supply bridge line 18 further includes semiconductor standard cells 30 and 32 in which the power supply bridge lines 18 are wired only outside the contacts. The interconnection of the power supply lines 4 and 6 is achieved in combination with the standard cells 2 and 20. That is, in the semiconductor standard cell 30, the power supply bridge line 18 connected to the GND line 6 via a contact is wired only outside the cell (the lower side in the figure). In addition, in the semiconductor standard cell 32, the power supply bridge line 18 is also connected via a contact to the power supply line 4 side, and this is wired outside the cell (upper side in the figure). The power supply bridge 18 wired only outside these cells is connected to the adjacent semiconductor standard cell 2.
Or 20 power supply bridge lines 18. And
Since the power supply bridges 18 extending between the two cells are provided at different levels, the three power supply lines 4 and 6 are connected to each other.

As described above, even in the case where the cell arrangement is irregular, the interconnection of the power supply lines 4 and 6 within the cell arrangement region is achieved by the present invention, and the same effects as those of the first embodiment can be obtained. . In order to interconnect the power supply lines 4 and 6, it is sufficient that the cell size is the same at the portion where the interconnection is performed, and the other portions need to have the same cell size at each stage as shown in FIG. Not necessarily.

[0031]

As described above, according to the semiconductor standard cell and the method of arranging and wiring the same according to the present invention, since this cell is provided with the power supply bridge line wired in the direction orthogonal to the power supply line, The power supply lines can be interconnected in the cell arrangement region only by appropriately arranging the power supply lines when designing the logic circuit, and the arrangement and wiring of the logic circuit is easy. Moreover,
It is not necessary to provide a space for interconnecting power supply lines between cell columns as in the related art around the cell arrangement region, and the layout density can be increased.

Further, interconnection of power supply lines between cell columns in the cell arrangement region can be performed as many as possible in accordance with the cell arrangement pattern, and the greater the number of connection points, the more effective the current is shunted. Power supply voltage to each cell (GN
(Including the D potential) can be applied in a uniform manner, and a logic circuit with excellent noise resistance can be designed. In addition, the degree of freedom of design in consideration of the high noise resistance is high.

As described above, according to the present invention, a semiconductor standard cell having a structure excellent in high density and high noise immunity and a method of arranging and wiring the same in the field of semiconductor logic IC in which high integration and low voltage are remarkably advanced are provided. can do.

[Brief description of the drawings]

FIG. 1 is a cell pattern diagram of an AND gate showing one configuration example of a semiconductor standard cell of the present invention.

FIG. 2 is a pattern diagram showing a power supply line and a power supply bridge line extracted from FIG. 1;

FIG. 3 is a first modification example of FIG.

FIG. 4 is a second modification example of FIG. 2;

FIG. 5 is a third modification example of FIG. 2;

FIG. 6 is a block layout diagram according to the first embodiment of the present invention.

FIG. 7 is a block layout diagram according to a second embodiment of the present invention.

FIG. 8 is a block layout diagram for explaining a conventional problem.

FIG. 9 is a cell pattern diagram of an AND gate showing one configuration example of a conventional semiconductor standard cell.

[Explanation of symbols]

2, 20, 22, 24 ... a semiconductor standard cell in which a power supply bridge line is routed inside the logic gate portion, 4 ... a power supply voltage supply line (power supply line), 6 ... GND line (power supply line), 8 ... a logic gate portion, 10 ... p-type transistor region, 12 ... n-type transistor region, 14 ... input terminal, 16 ... output terminal, 1
Reference numeral 8: power supply bridge, 18a, 18b: contacts (connection points), 30, 32: semiconductor standard cell in which the power supply bridge is wired from the connection with the power supply line to the outside of the cell,
A to I: types of logic gates.

Claims (6)

[Claims] A logic gate portion, a power supply line interconnected between cells adjacent to each other in a wiring direction and supplying a power supply voltage to the logic gate portion, and a wiring layer of a different hierarchy from the power supply line; A power supply bridging line connected to the power supply line in the cell and being connected to the power supply line at right angles to each other so as to be mutually connected between cells adjacent in the direction orthogonal to the power supply line. Standard cell. 2. The power supply line comprises a first power supply line and a second power supply line wired in parallel with each other with the logic gate portion interposed therebetween, wherein the power supply bridge line is a first power supply line. 2. The semiconductor standard cell according to claim 1, wherein the semiconductor standard cell is connected to one of the line and the second power supply line, and is wired in a direction orthogonal to the power supply line in the logic gate unit. 3. The power supply line includes a first power supply line and a second power supply line wired in parallel with each other with the logic gate portion interposed therebetween, and the power supply bridge line is a first power supply line. 2. The semiconductor standard cell according to claim 1, wherein the semiconductor standard cell is connected to one of the line and the second power supply line, and is wired from a connection point with the power supply line to the outside of the cell. 4. A method of arranging and wiring semiconductor standard cells in which a plurality of standard cells are arranged vertically and horizontally to interconnect each other, wherein the logic cells are interconnected between adjacent cells in the wiring direction. A power supply line for supplying a power supply voltage to the logic gate unit,
It is configured using a wiring layer of a different hierarchy from the power supply line, is connected to the power supply line in the cell, and is wired orthogonally to the power supply line, so that cells between cells adjacent in the direction orthogonal to the power supply line A plurality of standard cells having mutually connected power supply bridging lines are arranged adjacent to each other in a direction orthogonal to the wiring direction of the power supply lines, and a column of the power supply lines connected in the wiring direction is arranged in a cell arrangement area. A method of arranging and wiring semiconductor standard cells that are connected to each other within a cell. 5. The power supply line includes a first power supply line and a second power supply line wired in parallel with each other with the logic gate portion interposed therebetween, and the power supply bridge line is a first power supply line. 5. The method according to claim 4, wherein the method is connected to any one of the first power supply line and the second power supply line, and wired in a direction perpendicular to the power supply line in the logic gate portion. 6. The power supply line includes a first power supply line and a second power supply line wired in parallel with each other with the logic gate portion interposed therebetween, and the power supply bridge line is a first power supply line. 5. The method according to claim 4, wherein the semiconductor standard cell is connected to one of the first power supply line and the second power supply line, and is wired outward from a connection point with the power supply line.