JPH06112450A - Layout of block of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to conduct a design for facilitation of a test and a design of a layout suitable for the improvement of reliability by a method wherein field through wirings having no relation to a logic are put at all the positions at each specified pitch of all the cells of logic circuit cells designed in such a way that their heights are formed in a constant height and their widths are formed at a pitch set at a value integer multiples of the smallest pitch. CONSTITUTION:Functional blocks (a P-type diffused layer 4 and an N-type diffused layer 5) arranged with logic circuit cells designed in such a way that their heights are formed in the same height and their widths are formed at a pitch set at a value integer multiples the smallest constant pitch and wiring blocks (a power conductor 6 and a GND conductor 6a) arranged in parallel to these functional blocks are alternately arranged and field through wirings 1, which intersect orthogonally the functional and wiring blocks and are not connected to anything, are penetratingly wired at all the positions at a pitch set at a value specified integer multiples of the smallest pitch of all the cells of the logic circuit cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laying out functional blocks of a semiconductor integrated circuit, and more particularly to a layout designing method in which logic circuit cells have the same height and width is an integral multiple of a minimum pitch.

[0002]

2. Description of the Related Art Conventionally, the layout of a semiconductor logic circuit cell of this type has been as shown in FIG. 7 for a CMOS 3-input AND gate, for example. This IC2
0 means that the transistors 21 and the wiring regions 22 are regularly arranged. In the transistor region 21, the P-type diffusion layer 4 and the N-type diffusion layer 5 are provided between the element isolation gates 3,
Power line 6 and ground (GND) parallel to these diffusion layers 4 and 5
A line 6a is provided, and an input line 2 and an output line 7 of the gate are provided orthogonal to these. In this case, the AND gate is laid out so that the height is set to a certain value and the width in the horizontal direction is set to an integral multiple of a certain width (minimum pitch) so that each logical function has a minimum size.

Assuming that two-layer aluminum wiring is used as the signal wiring, the first aluminum wiring layer is assigned to the power supply line 6 and the in-cell wiring, and the second aluminum wiring layer is assigned to the output wiring 7 from the cell. I am assuming a cell. The layout of the logic circuit using these cells is such that the cells are arranged in the horizontal direction as shown in FIG.
2 was used.

On the other hand, in the case of a gate array of a system in which a region other than the wiring region is formed in advance and a different logic circuit is realized only by rewiring, for example, in the case of CMOS, FIG.
As described above, two transistor pairs are used as one basic cell, which are laid out in the lateral direction, and the wiring region 22 is provided to arrange them in several stages.

[0005]

In the above-described conventional cell design for a logic circuit, a gate array has a 3-input NAN.
In the case of realizing the D gate, since two basic cells are used as shown in FIG. 8, a transistor region such as an unused gate 13 is formed, so that there is a drawback that the utilization efficiency of the layout is lowered.

On the other hand, in order to reduce the layout area,
When the layout using the cells shown in FIG. 7 is performed,
Even if it is necessary to vertically pass some wirings (polysilicon or second aluminum wiring) from the upper side to the lower side, it is difficult to pass the wirings.

An object of the present invention is to eliminate these drawbacks, improve layout efficiency, and provide a highly reliable block layout method for a semiconductor integrated circuit.

[0008]

The structure of a block layout method for a semiconductor integrated circuit according to the present invention has the same height.
In a block layout method of a semiconductor integrated circuit in which a functional block in which logic circuit cells whose width is set to an integer multiple of a fixed minimum pitch width are arranged and a wiring block in which the functional blocks are arranged in parallel are alternately arranged Wiring is performed in all cells of the logic circuit cell at all positions that are a specific integer multiple of the minimum pitch width, orthogonal to the functional block and the wiring block, and penetrating feed-through wiring that is not connected to any of them. It is characterized by having done.

[0009]

1A and 1B are layout diagrams for explaining a first embodiment of the present invention, showing a layout example of a 3-input NAND gate, and FIGS. 2A and 2B are diagrams. 1 (a),
It is a schematic diagram of (b). Here, the feed-through wiring of the gate polysilicon (hereinafter referred to as F
1) is arranged. Further, only the FT wiring 1 or the transistor for element isolation is arranged on the left side or the right side of the cell. For example, when the cell on the left is arranged as shown in FIG.
3 selected so that feedthrough wiring comes to the pitch
Arrange the input NAND gate (in this case, FIG.
(Cells of (a) and (b)).

Here, for example, a transistor is formed in the wiring region as shown in FIG. 4, one diffusion layer is connected to the output of the logic cell, and the other diffusion layer is connected to the lateral aluminum wiring. As a result, as shown in US Pat. No. 4,749,471, a failure of an arbitrary output terminal can be detected by selecting an arbitrary probe line and observing the output of the sense line.

FIGS. 5A and 5B are layout diagrams of the second embodiment of the present invention, showing an example of a cell in which the second layer aluminum wiring is assumed as the FT wiring. As a result,
As shown in, the power line of the cell or GND
By connecting with, the power supply lines can be arranged in a mesh and a highly reliable logic circuit layout can be performed.

[0012]

As described above, according to the present invention, in a cell designed to have a constant height and a lateral width that is an integral multiple of the minimum pitch, by placing FT wiring unrelated to logic at a specific pitch, There is an effect that a design for testability and a layout design for improving reliability can be performed.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a logic circuit cell according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating FIG.

FIG. 3 is a schematic diagram showing a connection method with adjacent cells in FIG.

FIG. 4 is a partially enlarged plan view of the application example of FIG.

FIG. 5 is a plan view of a logic circuit cell according to a second embodiment of the present invention.

FIG. 6 is a partially enlarged plan view of the application example of FIG.

FIG. 7 is a partially enlarged plan view of an example of a conventional logic circuit cell.

FIG. 8 is a plan view of an example of a logic circuit cell of a conventional gate array.

[Explanation of Codes] 1 FT wiring 2 Gate input line 3 Element isolation gate 4 P-type diffusion layer 5 N-type diffusion layer 6 Power supply line 6a GND line 7 Output line 8 Sense line 9 Logic circuit cell output line 10th 2 Aluminum FT wiring 11 GND line 12 Power supply line 13 Unused gate line 20 IC 21 Transistor area 22 Wiring area

Claims (1)

[Claims] 1. A functional block in which logic circuit cells having the same height and a horizontal width that is an integral multiple of a fixed minimum pitch width are arranged, and a wiring block arranged in parallel with the functional block are alternately arranged. In the block layout method of the semiconductor integrated circuit arranged in the above, in all cells of the logic circuit cell in all positions of a specific integer multiple of the minimum pitch width, orthogonal to the functional block and the wiring block, which A block layout method for a semiconductor integrated circuit, which is characterized in that wiring is performed through a feed-through wiring that is not connected to the semiconductor integrated circuit.