JPH03274764A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a developing period by forming an interconnection layer of an uppermost layer of a multilayer interconnection layer on a logic circuit of a critical path interconnection layer. CONSTITUTION:In a gate array type semiconductor integrated circuit device 1, an interconnection layer of a fourth layer on a logic circuit B is formed of a critical path interconnection or delay path interconnection relief interconnection layer, a main power source interconnections 7 formed of the layer of the fourth layer is provided on an input/output buffer circuit 3, and power source interconnections 17 electrically connected to the interconnections 7 is provided on an interconnection layer of a third layer on the circuit B. With this configuration, the delay path interconnection or speed critical path interconnection is formed on the layer of the fourth layer on the circuit B independent from signal interconnections 13, 15 except it alternatively by an automatic layout of an automatically disposing interconnection system, a parasitic capacity to be added to this signal interconnection 19 is reduced, the interconnection 19 is freely alternatively laid, the length of the interconnection 19 is increased to reduce the parasitic capacity and the resistance value. Thus, its developing period can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device that employs a gate array method.

[Conventional technology]

A semiconductor integrated circuit device employing a gate array method can configure a desired logic circuit by connecting regularly arranged basic cells and between basic cells with multiple layers of signal wiring. Further, a semiconductor integrated circuit device employing a gate array method can configure various logic circuits other than those described above simply by changing the connection pattern of the signal wiring.

This type of semiconductor integrated circuit device is characterized by the ability to construct a wide variety of products in a short period of time.

A semiconductor integrated circuit device employing a gate array method, which is currently being developed by the present inventor, is composed of a chip (for example, a single-crystal silicon substrate) having a rectangular planar shape. This semiconductor integrated circuit device has multiple external terminals (
(ponding pad) is placed. A plurality of input/output buffer circuits are arranged inside the external terminals along the arrangement of the external terminals. A plurality of basic cells are arranged in a matrix inside the input/output buffer circuit. In the case of the fixed channel method, a plurality of basic cells arranged in the column direction form a basic cell column. A plurality of basic cell columns are arranged in the row direction at predetermined intervals. A wiring formation region (wiring channel region) is provided between these basic cell columns arranged in the row direction.

A semiconductor integrated circuit device employing this gate array method has a three-layer wiring structure. The first layer wiring is used as wiring within the basic cells and signal wiring connecting between basic cells. The signal wiring connecting between the basic cells extends in the wiring formation region in the column direction. The second layer wiring is used as a signal wiring connecting basic cells.

The signal wiring connecting between the basic cells extends in the row direction over the basic cells and in the wiring formation region.

The third layer wiring is mainly used as power wiring.

In other words, in a semiconductor integrated circuit device employing the gate array method, the uppermost wiring layer is configured as a power supply wiring layer in order to increase voltage drop and electromigration withstand voltage of the power supply.

The signal wiring is usually done using a computer-based automatic placement and routing system (DA: Design Auto).
mation).

Note that a semiconductor integrated circuit device employing the gate array method is described in, for example, Japanese Patent Laid-Open No. 61-53826.

[Problem to be solved by the invention]

In the semiconductor integrated circuit device that employs the gate array method, the signal wiring described above is performed using an automatic placement and routing system (
DA) will be automatically laid out.

This automatic layout of signal wiring is performed in an automatic placement and wiring system by arranging logic circuits in basic cells and sequentially connecting the logic circuits with the shortest distance based on an algorithm. The signal wiring is placed in an X-Y wiring channel formation region that is virtually formed in the memory space of the automatic placement and wiring system. In areas where signal wiring has already been placed in the pre-processing of the X-Y wiring channel formation area, even if it is a wiring channel that has the shortest distance for signal wiring connecting logic circuits, the rules prohibit signal wiring from being placed. make a detour. In other words, the signal wiring is automatically laid out in sequence, and the wiring length increases as the process approaches the final stage. Therefore, one or several signal wires whose wire length is increased due to the detour wire become delay path wires that exceed the allowable delay time between logic circuits. The occurrence of this delay path wiring is
Even if there are only a few wires, the logic system will no longer work, so the automatic layout must be redone using an automatic placement and routing system.In other words, the development period for semiconductor integrated circuit devices that use the gate array method will be extended. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can easily take measures for delay path wiring in a semiconductor integrated circuit device that employs a gate array method.

Another object of the present invention is to provide a technique that can shorten the development period in a semiconductor integrated circuit device that employs a gate array method.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) A gate array semiconductor integrated circuit in which a logic circuit section is placed in an area surrounded by input/output buffer circuits, and basic cells arranged regularly in this logic circuit section are connected by multilayer wiring. In the circuit device, the uppermost wiring layer of the multilayer wiring layer on the logic circuit is a critical path wiring layer (a relief layer for delay path wiring among signal wiring).

(2) Main power supply wiring is provided in the uppermost wiring layer above the input/output buffer circuit.

(3) A power supply wiring connected to the main power supply wiring is provided in a lower wiring layer one level below the uppermost wiring layer on the logic circuit section.

[For production]

According to the above-mentioned means (1), signal wiring that has become a delay path wiring (speed-critical path wiring) due to detour wiring in the automatic layout of an automatic placement and routing system is replaced with other signal wiring (other than delay path wiring). It is formed in the top wiring layer of the logic circuit section virtually independently from the signal wiring (signal wiring), which reduces the parasitic capacitance added to the signal wiring, and allows the signal wiring to be routed freely. Since it is possible to reduce the parasitic capacitance and resistance value by shortening the wiring length of the signal wiring, the delay path wiring (particularly the speed-critical path wiring) can be easily repaired. Therefore, there is no need to perform automatic layout of all signal wiring including delay path wiring again using the automatic placement and routing system, and all that is required is to rearrange the delay path wiring to the topmost wiring layer. The development period for semiconductor integrated circuit devices can be shortened.

According to the above-mentioned means (2), since the uppermost wiring layer on the logic circuit section is always provided as a wiring layer forming the main power supply wiring on the input/output buffer circuit, this uppermost wiring layer (without adding a new wiring layer), delay path wiring can be easily repaired.

According to the above-mentioned means (3), the delay path wiring (critical path wiring in terms of speed) formed in the uppermost wiring layer on the logic circuit section and the signal formed in the wiring layer further below the power supply wiring. Since crosstalk with the power supply wiring can be reduced by the power supply wiring, malfunctions of the logic system can be prevented. Therefore, the electrical reliability of the gate array type semiconductor integrated circuit device can be improved.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device that employs a gate array method.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 2 (chip layout diagram) and FIG. 3 (principal part plan view of FIG. 2) show a schematic configuration of a semiconductor integrated circuit device that employs a gate array system, which is an embodiment of the present invention.

As shown in FIG. 2, a semiconductor integrated circuit bag N1 employing a gate array method is composed of chips (for example, a single crystal silicon substrate) having a rectangular plane. Semiconductor integrated circuit device 1
has multiple external terminals (
(pounding pad) 2 is placed. A plurality of input/output buffer circuits 3 are arranged along this array of external terminals 2.

At the center of the semiconductor integrated circuit device 1 surrounded by the input/output buffer circuit 3, a logic circuit section (basic cell array) forming a logic circuit is provided. This logic circuit section includes basic cells 4 (cells that are the smallest basic unit of a collection of elements that can constitute a logic circuit, logic block, or functional block).
A plurality of are arranged regularly in each of the X direction and the X direction. A plurality of basic cells 4 arranged in the X direction (vertical direction in FIG. 2) form a basic cell column 5. A plurality of these basic cell rows 5 are arranged in the X direction (horizontal direction in FIG. 2) at predetermined intervals. Between the basic cell rows 5, signals connecting between the basic cells 4 (between logic circuits) In other words, the semiconductor integrated circuit bag W1 is used as a wiring formation region (wiring channel region) 6 in which the wiring for the wiring is formed.In other words, as shown in FIG. It is composed of a peripheral circuit section A and a logic circuit section B in which basic cells 4 constituting a logic circuit are arranged.The semiconductor integrated circuit device 1 also includes a wiring formation region 6 between the basic cell rows 5. It consists of a fixed channel system.

As shown in FIGS. 2 and 3, a main power supply wiring 7 formed in the fourth wiring layer extends over the input/output buffer circuit 3. As shown in FIGS. Semiconductor integrated circuit device 1 of this embodiment
consists of a four-layer wiring structure, and this main power supply wiring 7
is formed in the uppermost wiring layer of the four wiring layers. The main power supply wiring [7 that extends outward is, for example, a power supply voltage wiring Vcc. The main power supply wiring 7 that extends inward is, for example, a reference voltage wiring Vss. This power supply voltage wiring Vcc is, for example, a circuit operating voltage of 5 [V],
The reference voltage distribution AIVSS is, for example, the circuit ground voltage 0 [V]
are applied.

Although not shown, the basic cell 4 is constructed by arranging a plurality of bipolar transistors, resistance elements, and capacitance elements based on a basic design. Above this basic cell 4, as shown in FIG. 3, a power main line 17 formed in a third wiring layer extends in the Y direction above the basic cell 4. On this basic cell 4, a set of power supply main lines 17 including two lines, including, but not limited to, a power supply voltage line Vcc and a reference voltage line Vss, extends. This power main line 1
The power supply voltage wiring Vcc and the reference voltage wiring Vss of the main power supply wiring 7 are electrically connected to the power supply voltage wiring Vcc and the reference voltage wiring Vss of the main power supply wiring 7 through connection holes 18, respectively.

The basic cell 4 can constitute a predetermined logic circuit or a part thereof by connecting elements using signal wiring (intra-basic cell wiring) formed in the first wiring layer. As shown in FIG. 2, the signal wiring 13 formed in the first wiring layer extending in the Y direction in the wiring formation region 6 is connected between each logic circuit formed by the wiring within the basic cell. It is connected to a signal wiring 15 formed in a second wiring layer extending over the basic cell 4 and the wiring formation region 6 in the X direction. As mentioned above, the third wiring layer includes the power supply needle 817
Although it is mainly formed, a part can also be used as a signal wiring extending over the basic cell 4 and the wiring forming region 6 in the Y direction. Further, among the connections between the logic circuits constituted by the wiring within the basic cell, some of the connections between the logic circuits are made using the signal wiring 19 formed in the fourth wiring layer. There is. The signal wiring 19 is formed in the uppermost layer of the wiring layer, which is the same layer as the main power wiring @ 1 placed on the input/output buffer circuit 3, and is located in the area where the main power wiring 7 is placed (peripheral circuit section). Logic circuit section B other than area A)
placed on top. That is, the signal wiring 19 is formed in the same layer as the main power supply wiring 7, and is formed using the wiring layer (top layer) of the main power supply wiring 7. Note that the above-mentioned external terminals 2 are also arranged in this fourth wiring layer, that is, the top layer. The signal wiring 19 is formed in order to relieve a delay path wiring in which a signal transmitted between logic circuits exceeds the allowable range or a critical path wiring in the vicinity of the permissible range.

As described above, the semiconductor integrated circuit device 1 employing the gate array method of this embodiment has a four-layer wiring structure consisting of a signal wiring layer and a power supply wiring layer, as described above. The wiring in each layer of this four-layer wiring structure is formed of aluminum wiring or aluminum alloy wiring. The aluminum alloy wiring is made by adding Cu or Si to aluminum.

Cu can reduce electromigration or stress migration. Si can reduce the alloy spike phenomenon at the junction with Si (semiconductor region).

Next, a four-layer wiring structure of a semiconductor integrated circuit device l employing the gate array method will be briefly described with reference to FIG. 1 (a cross-sectional view of main parts taken along line E in FIG. 2).

As shown in FIG. 1, a semiconductor integrated circuit device 1 with a four-layer wiring structure employing a gate array method is mainly constructed of a p-type semiconductor substrate 10 made of single crystal silicon. Although not shown, the main surface of the semiconductor substrate 10 has an active region (
(element formation region) is provided in the peripheral circuit section A and the logic circuit section B. A bipolar transistor, a resistance element, and a capacitance element are each configured in this active region. The active region is electrically isolated from other surrounding active regions by an element isolation region. The element isolation region is mainly the size of the P-type semiconductor substrate 10 and the amount of elements! Insulating film (for example, silicon oxide film) 11
It consists of An insulating film 12 is formed on the insulating film 11 corresponding to the number of elements, that is, on the peripheral circuit section A and the logic circuit section B. The insulating film 12 electrically isolates the elements formed in the active region and the first wiring layer.

On the insulating film 12 on the peripheral circuit section A and the logic circuit section B, an arrangement 1A13 formed in the first wiring layer extends. Of these wirings 13, the wirings 13 extending over the logic circuit section B are used to connect wiring within the basic cells, between the basic cells 4, between the logic circuits formed by the basic cells 4, etc., although not shown in the drawings. It is used as signal wiring for connection.

On the wiring 13 of the logic circuit section B, a wiring 15 formed in a second wiring layer extends with a glabella insulating film 14 interposed therebetween. This wiring 15 is electrically connected to the wiring 13 of the logic circuit section B through a connection hole 14b formed in the glabella insulating film 14. In other words, the wiring 15 is the wiring 1
3 is used as a signal wiring for connecting between basic cells 4 or between logic circuits formed by basic cells 4.

A wiring 17 formed in a third wiring layer extends over the wiring 15 with a glabella insulating film 16 interposed therebetween. As mentioned above, this wiring 17 is the power supply trunk, i! 17 is mainly used.

A wiring 19 formed in the fourth layer wiring N (the uppermost wiring layer) extends over the wiring 17 with a glabella insulating film 18 interposed therebetween. This wiring 19 is electrically connected to a wiring 17a formed in the third wiring layer through a connection hole 18a formed in the interlayer insulating film 18. The wiring 17a is connected to the connection hole 16 formed in the interlayer insulating film 16.
It is electrically connected to the wiring 15 formed in the second Nth wiring layer through the wiring a.

This wiring 15 is electrically connected to the wiring 13 formed in the first wiring layer through the connection hole 14a formed in the interlayer insulating film 14. In other words, the arrangement 411
9 is a wiring 1 formed in each wiring layer of a four-layer wiring structure.
5.17a, it is used as a signal wiring to connect between basic cells 4 or between logic circuits formed by basic cells 4, etc., and as mentioned above, for the purpose of relieving delay path wiring or critical path wiring. It is configured.

A main power supply wiring, vi7, and external terminals 2 are formed in the fourth wiring layer on the peripheral circuit section A.

The external terminal 2 for power supply voltage among the external terminals 2 and the power supply voltage wiring Vcc of the main power supply wiring 7 are connected to the third wiring layer through the connection hole 18b formed in the interlayer insulating film 18. They are electrically connected by a wire 17b. Similarly, the external terminal 2 for reference voltage and the reference voltage wiring Vss of the main power supply wiring 7 are electrically connected by a wiring 17b.

In the peripheral circuit section A, the signal wiring 19 is formed on the external terminal 2 and the main power supply wiring 7 formed on the fourth wiring layer and on the fourth Nth wiring layer in the logic circuit section B.
A final protective film 20 is applied to the entire surface of the glabellar gauze 18 including the upper part.
is formed. Each of the interlayer insulating films 18, 16, and 14 is formed mainly of, for example, a silicon oxide film.

The final protective film 20 is formed mainly of a silicon nitride film.

The semiconductor integrated circuit device l that adopts the gate array method of this embodiment has a main power distribution #! 7 and power main line 17,
The signal wires formed in each of the first to fourth wiring layers are automatically arranged by an automatic placement and routing system (DA) using a computer. A specific method for forming a semiconductor integrated circuit device 1 employing a gate array method using this automatic placement and wiring system will be briefly described with reference to FIG. 4 (process flow diagram).

First, a logic function to be installed in the semiconductor integrated circuit device 1 is designed and a logic circuit diagram is created <10>.

Next, based on the logic circuit diagram, logic circuit information is input into the automatic placement and wiring system as information that can be handled by the automatic placement and wiring system (11).

Next, based on the information input to the automatic placement and routing system, a logic circuit is automatically placed by a computer <12>.

Next, the wiring between the logic circuits is automatically placed using an automatic placement and routing system <13>. Connection wiring is an X-Y virtual setting in the memory space of the automatic placement and routing system.
The logic circuits are arranged in the wiring channel region using an algorithm so as to connect the logic circuits with the shortest distance. This connection wiring is arranged mainly in the first wiring layer (13) and the second wiring layer (15).

Next, the connection wiring automatically placed by the automatic placement and wiring system is inspected by delay simulation to detect delay path wiring or critical path wiring. In an automatic placement and routing system, connections placed in later processing are placed by bypassing connections placed in earlier processing, resulting in longer wires and shorter connections between logic circuits. This tends to result in critical path wiring or delayed path wiring that is close to or exceeds the allowable delay time.

This critical path wiring or delay bus wiring causes malfunction or inoperability of the logic circuit. In this delay simulation, if no delay path wiring or critical path wiring is detected, the wiring information input to the automatic placement and routing system is converted into mask production data <17>.

Further, when a delay path wiring or critical path wiring is detected in the delay simulation, this delay path wiring or critical path wiring is arranged as a signal wiring 19 in the fourth wiring layer on the logic circuit section B. , is rescued so that it falls within the above-mentioned allowable delay time <15>. As shown in FIGS. 1 to 3, the signal wiring 19 is connected to each of the signal wirings 13 and 15 formed in the first wiring layer and the second wiring layer, respectively. (Because it is a dedicated wiring layer for relief)
, the X direction, and the Y direction at the shortest distance, or diagonally as shown by reference numeral 19a. This signal wiring 19 is formed automatically by the automatic placement and wiring system or manually.

Next, after testing the signal wiring 19, delay simulation is performed again <16>. At this time, if delay path wiring or critical path wiring is detected again, either the automatic placement of logic circuits (12) is performed again, or the automatic placement of connection wiring (13) is performed again.

Next, the wiring information input to the automatic placement and wiring system is converted into mask production data17>.

Mask production data is created based on design rules (device process processing rules).

Next, based on the mask production data, electron beam (EB)
A manufacturing mask is formed using a drawing device (18).

Next, using the manufacturing mask, a semiconductor wafer manufacturing process (device process) is performed (19), thereby substantially completing the semiconductor integrated circuit device 1 that employs a gate array method and is equipped with a predetermined logic function. Do〈20
〉.

In this way, the logic circuit part B is arranged in the area surrounded by the input/output buffer circuit 3, and the gates are connected between the basic cells 4 regularly arranged in this logic circuit part B with multilayer wiring. In the array type semiconductor integrated circuit device 1, a fourth wiring layer (top layer) on the logic circuit portion B is used as a relief wiring layer for critical path wiring or delay path wiring;
A main power supply wiring 7 formed in a fourth wiring layer is provided on the crowd buffer circuit 3 (peripheral circuit section A), and a main power supply wiring 7 formed in a fourth wiring layer on the logic circuit section B is provided. Wiring 7
A power supply wiring 17 is provided which is electrically connected to. With this configuration, in the automatic layout of the automatic placement and routing system, delay path wiring or speed-critical bus wiring is routed to the logic circuit section B that is substantially independent of the other signal wiring 13 and 15 by detour. It takes shape in the fourth wiring layer,
The parasitic capacitance added to the signal wiring 19 can be reduced, and the signal wiring 19 can be routed freely to shorten the wiring length of the signal wiring 19 to reduce the parasitic capacitance and resistance value. Therefore, the delay path wiring or critical path wiring can be easily relieved. Therefore, there is no need to use the automatic placement and routing system to automatically lay out signal wiring on the bottom layer, including delay path wiring and critical path wiring, and all you have to do is rearrange the delay path wiring and critical path wiring on the top layer. Therefore, the development period of the gate array type semiconductor integrated circuit device 1 can be shortened.

In addition, since the fourth wiring layer (top layer) is always provided as a wiring layer on which the main power supply wiring 7 is provided on the input/output buffer circuit 3 (peripheral circuit section A), the fourth wiring layer Delay path wiring or critical path wiring can be formed using layers (without providing a new wiring layer).

Further, by providing the power supply wiring 17 electrically connected to the main power supply wiring 7 in the third wiring layer on the logic circuit section B, the signal wiring formed in the fourth wiring layer (
Since crosstalk between the rescued signal wiring 19 and the wiring 15 formed in the second wiring layer can be reduced by the power supply wiring 17, malfunction of the logic circuit can be prevented. Therefore, the electrical reliability of the gate array semiconductor integrated circuit device 1 can be improved.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to a gate array type semiconductor integrated circuit device having five or more wiring layers.

Further, the present invention can be applied to a semiconductor integrated circuit device that employs a gate array method in which basic cells are spread over the entire surface without providing a wiring formation region between basic cell columns. In the case of this laying method, basic cells or basic cell rows between logic circuits are used as wiring formation regions.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device that employs a gate array method, delay path wiring or speed-critical path wiring can be easily repaired, so that the development period can be shortened.

Furthermore, the electrical reliability of the semiconductor integrated circuit device can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part (a cross-sectional view of a main part taken along line E in FIG. 2) showing a multilayer wiring structure of a semiconductor integrated circuit device that employs a gate array method, which is an embodiment of the present invention. 2 is a chip layout diagram of the semiconductor integrated circuit device, FIG. 3 is a plan view of the main part of FIG. 2, and FIG. 4 is a process flow diagram illustrating a method for forming the semiconductor integrated circuit device. In the figure, 1: Semiconductor integrated circuit device, 3: Output buffer circuit, 4: Basic cell, 7: Main power supply wiring,
10...Semiconductor substrate, 13...1Nth wiring (signal wiring), 15...2nd layer wiring (signal wiring, i), 17...3rd layer wiring ( power supply wiring), 19...
This is the fourth layer wiring (relief wiring). Figure 4

Claims (1)

[Claims] 1. A gate in which a logic circuit section is arranged in a region surrounded by an input/output buffer circuit, and basic cells arranged regularly in this logic circuit section are connected by multilayer wiring. 1. An array-type semiconductor integrated circuit device, characterized in that the uppermost wiring layer of the multilayer wiring layer on the logic circuit section is a critical path wiring layer. 2. The semiconductor integrated circuit device according to claim 1, wherein a main power supply wiring formed of the uppermost wiring layer is provided on the input/output buffer circuit. 3. A power supply wiring connected to the main power supply wiring is arranged in a lower wiring layer one level below the uppermost wiring layer on the logic circuit section. The semiconductor integrated circuit device described in .