JP2596406B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit designed by a standard cell system.

[0002]

2. Description of the Related Art A large-scale integrated circuit is often designed using a standard cell system. This has recently been
This is because automatic placement of standard cells and automatic wiring between standard cells have been performed by design support (hereinafter, abbreviated as CAD) by an electronic computer. With the advance of such CAD technology, a large-scale integrated circuit having tens of thousands of gates is designed in a short time. In the conventional standard cell, as shown in FIG. 3, the height of the standard cell is constant in all cells in order to easily adapt to CAD. Thus, the area where the standard cells are arranged (standard cell row 3
0) is separated from the wiring region 26 connecting the input terminal and the output terminal of the standard cell to perform CAD.

[0003]

There are several problems with such a conventional system. First, since the height of the standard cell is constant, for example, in a simple standard cell such as an inverter, most of the area of the standard cell is useless. Further, from the viewpoint of the frequency of use of standard cells, relatively simple standard cells are frequently used, and standard cells having a large number of transistors are not very frequently used.

On the other hand, the maximum height of a standard cell is determined in a standard cell having a large number of transistors and a standard cell having a large driving capability. As described above, in a conventional large-scale integrated circuit using standard cells, a relatively useless area exists in the area where the standard cells are arranged, which is an obstacle to high integration.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit utilizing a conventional wasteful area as a wiring area.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a standard cell array in which a plurality of standard cells are arranged, and a wiring region provided between the standard cell arrays. In the integrated circuit, the standard cell includes a power supply line and a ground line arranged in the horizontal direction near the center, and a P-channel MOSFET on the opposite side of the ground line with respect to the power supply line.
There is a region of an N-channel MOSFET on the opposite side of the power supply line with respect to the ground line, and the standard cell row is formed in the standard cell row by having standard cells having different heights. A semiconductor integrated circuit characterized in that the roughened region is used as a wiring region.

According to the present invention, the standard cell row has standard cells having different heights, so that the uneven area is formed in the standard cell row and the uneven area is used as the wiring area. Area can be used as a wiring area.

[0008]

FIG. 1 is a layout diagram showing a 2-input NAND gate of a CMOS standard cell according to the present invention. Through the detailed description of FIG. 1, the layout policy of the standard cell of the present invention will be clarified.

In FIG. 1, 2 is a power supply line, 4 is a ground line,
6 is a first input line, 8 is a second input line, 10 is an output line,
12 is a diffusion region forming a p-channel MOSFET;
14 is a diffusion region forming an n-channel MOSFET;
14 is a diffusion region forming an n-channel MOSFET;
Reference numerals 16 and 18 denote diffusion regions for obtaining the substrate potential of the p-channel MOSFET, and reference numeral 20 denotes an n-channel MOSFET.
The diffusion region 22 for taking the substrate potential of T is a feedthrough.

The power supply lines 2 are arranged in a horizontal direction at a constant width at the center of the cell using the first-layer metal wiring. The ground line 4 is arranged in a horizontal direction at a constant width at the center of the cell using the first-layer metal wiring. The input lines 6 and 8 are vertically arranged using polycrystalline silicon (or silicide / polycide as a low-resistance material). Thereby, the MOSF existing in the standard cell is
In all ETs, the gate electrodes are arranged in the vertical direction. The required connection between the drain portion of the p-channel MOSFET and the drain portion of the n-channel MOSFET is such that a power supply line and a ground line are provided horizontally in the center of the cell.
Since the wiring is arranged by the metal wiring of the second layer, the wiring is performed by using the metal wiring of the second layer. p-channel MOSFE
The drain portion of T is connected to the second layer via the first-layer metal wiring.
It is connected to the metal wiring of the layer. Similarly, n channel M
The drain portion of the OSFET is connected to the second-layer metal wiring via the first-layer metal wiring.

The standard cell has a vertical wiring area usually called a feedthrough. This includes an implicit feedthrough, such as an output line of a standard cell, and an explicit feedthrough, which allows wiring that is not related to the standard cell to pass through. In the standard cell of the present invention, all output lines can be implicit feedthroughs, and explicit feedthroughs such as feedthroughs 22 can also be employed. Although the feedthrough used in the implicit feedthrough is limited by the logic, the explicit feedthrough is very effective because any wiring can be used.

In the standard cell shown in FIG. 1, the second-layer metal wiring is arranged vertically and used only for connecting the drain of the p-channel MOSFET and the drain of the n-channel MOSFET. In the region (1), the explicit field through is easily arranged in the vertical direction using the second-layer metal wiring.

When the standard cell of FIG. 1 is used for a large-scale integrated circuit, the automatic arrangement of the standard cell by CAD makes the power supply line and the ground line horizontal so that the width of the power supply line and the ground line is fixed. Arrange them in a straight line. Then, the outer shape of the standard cell row 24 is uneven as shown in FIG. Thus, the uneven area 2 by the standard cell
It is an advantage of the design method using the standard cell of FIG. 1 that the active area 8 is used as a wiring area. This uneven area 2
By allocating a part of the wiring region to 8, the wiring region can be made smaller than in the conventional case, and high integration can be realized.

[0014]

As described above, according to the semiconductor integrated circuit of the present invention, since an uneven area is formed in the cell row, a part of the wiring which was conventionally wired only in the wiring area is wired in the uneven area. The conventional wiring area can be reduced, and high integration can be realized. Further, since the explicit feedthrough is configured to be easily arranged, unnecessary insertion of the feedthrough cell can be reduced, and high integration can be realized.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a 2-input NAND gate of a standard cell.

FIG. 2 is a layout diagram of a semiconductor integrated circuit when the standard cells of FIG. 1 are automatically arranged by CAD.

FIG. 3 is a layout diagram of a semiconductor integrated circuit when a conventional standard cell is automatically arranged by CAD.

[Explanation of symbols]

Reference Signs List 2 power supply line 4 ground line 6 first input line 8 second input line 10 output line 12 p-channel MOSFET region 14 n-channel MOSFET region 16, 18 diffusion region for obtaining substrate potential of p-channel MOSFET 20 n Diffusion region for taking substrate potential of channel MOSFET 22 Feedthrough 24 Standard cell row 26 Conventional wiring region 28 Wiring region generated by unevenness

Claims (3)

(57) [Claims] 1. A standard cell row in which a plurality of standard cells are arranged;
A semiconductor integrated circuit including a wiring region provided between the standard cell columns, wherein the standard cell has a power supply line and a ground line arranged horizontally in the vicinity of the center, and the ground line is provided with respect to the power supply line. There is a region of a P-channel MOSFET on the opposite side of the power supply line, and an N-channel MOSFET
A semiconductor integrated circuit having a region of T, wherein the standard cell row has standard cells having different heights, so that the uneven area formed in the standard cell row is used as a wiring area. 2. The semiconductor integrated circuit according to claim 1, wherein a source contact of said MOSFET is disposed in a direction perpendicular to said power supply line and said ground line. 3. The power supply line and the ground line each have a main line arranged in a horizontal direction and a sub line arranged in a direction perpendicular to the main line, and a source contact is formed on the sub line. 3. The semiconductor integrated circuit according to claim 2, wherein: