JPH04163963A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent degradation of characteristics by a method wherein insulated gate field effect transistors (MOSFETs) within a wafer are arranged in the same direction, thereby allowing uniform ion implantation. CONSTITUTION:I/O cells in the same bulk are of two kinds of vertical I/O cells 102 horizontals I/O cell 103. The I/O cell 110 is configured by rotating the MOSFETs 90 deg. relative to an I/O cell 100, and the MOSFETs are all positioned in the same direction when they are arranged on a circumference I/O cell section. Naturally, they will be positioned in the same direction as that of the inside base gate. Implanting ions into the MOSFET in the vertical direction will prevent the degradation of the characteristics, thereby making it possible to eliminate the increase in the process number for preventing the degradation of characteristics.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate field effect transistor (MOSF).
It is a semiconductor device in which a gate array (ET) is formed, and particularly relates to a high-speed, highly integrated circuit. [Prior Art] A conventional semiconductor device will be explained using a gate array as an example.

Insulated gate field effect transistor (hereinafter referred to as MOSFET)
FIG. 2 shows a chip layout of a conventional gate array on a semiconductor substrate on which a gate array (referred to as "gate array") is formed. Inside the gate array, 101 internal basic gates are laid out in an array, so the MOSFETs are all oriented in the same direction. However, in the peripheral input/output cell section 200, for example, the input/output cell 102 on the lower side,
The input/output cell 103 on the right side is different.

In the gate array, since the bulk transistor arrangement of the input/output cells is all the same, 102 and 103 are rotated by 90 degrees, so inevitably the MOSFETs are also rotated by 90 degrees and are no longer in the same direction.

[Problem to be solved by the invention] However, in the conventional semiconductor device, the input/output cells of the gate array are rotated by 90 degrees, so the orientation of the MOSFET is
There are different types. For example, when considering ion implantation in a process step, it is assumed that ions are implanted from the left side at an angle of 45 degrees with the facet portion of the wafer 200 facing down as shown in FIG. In this case, 201 MO
SFET is uniformly implanted with ions, but the M of 202
In OSFETs, it is not implanted uniformly.

FIG. 4 is a cross-sectional view showing how ions are implanted into the MOSFET 202 shown in FIG.

Ions are uniformly implanted into the diffusion region 301, but due to the influence of the Po1y gate 300 in the diffusion region 302, ions are not implanted into the region 303 near the gate. For example, if the height of the Pony gate (including the M film) is H and the gate width is W, the region where ions are not implanted is an area of (SQR(2) x H) x W [sq, μml]. However, although this region is diffused in the next thermal diffusion step, it becomes a thinner diffusion region than the others.

This causes characteristic deterioration of the MOSFET, and in particular,
In high-speed, highly integrated devices using microprocesses, there is a problem in that the characteristics deteriorate significantly.

In addition, in order to solve the above problem, 1
In some cases, a countermeasure is taken in terms of process, such as implanting ions twice, rotating the wafer 180 degrees, and implanting ions again, but this also increases the number of steps and has problems such as increased cost.

Therefore, the present invention aims to solve the above-mentioned problems, and aims to prevent the deterioration of MOSFET characteristics without increasing the number of process steps.

Means for Solving the Problem C] In order to solve the above problems, the present invention provides an insulating solution within the same wafer (same as within the same chip) in a semiconductor substrate on which an insulated gate field effect transistor (MOSFET) is formed. Gate field effect transistor (MOSFET)
) are all in the same direction.

[Example] An embodiment of the present invention will be described using a gate array as an example.

FIG. 1 is a chip layout diagram of a gate array to which the present invention is applied. Reference numeral 101 denotes internal basic gates, which are laid out in an array inside the gate array and are oriented in a fixed direction. Reference numerals 100 and 110 are peripheral input/output cell sections, which have four directions: top, bottom, left, and right. Normally, in the case of a gate array, the input/output cells have the same bulk, and are divided into types depending on the wiring, which are rotated 90 degrees or 180 degrees and assigned to the input/output cell portions. In FIG. 1, normal input/output cells of the same bulk are divided into two types: input/output cells 102 for upper and lower sides, and input/output cells 103 for left and right sides. 9
The structure is rotated by 0 degrees, so that the MOSFETs always face in the same direction when placed in the peripheral input/output cell section.

Also, naturally, the orientation of the MOSFET is the same as that of the internal basic gate.

As in this example, by unifying the orientation of the MOSFETs in the wafer and implanting ions vertically into the MOSFETs, the characteristics of the MOSFETs deteriorate, and the number of steps is increased as a process-side measure to prevent characteristic deterioration. This will prevent

[Effects of the Invention] As explained above, the semiconductor device of the present invention has the following effects by unifying the orientation of the M,03FETs in the wafer in the same direction.

(1) Ions can be uniformly implanted in the ion implantation step of the process, which has the effect of preventing deterioration of MOSFET characteristics.

In particular, high-speed, compact integration using microprocesses, where characteristic deterioration is noticeable, is effective for integrated circuits.

Furthermore, the improvement in characteristics has the effect of increasing yield.

(2) In conventional MOSFET layout, in order to prevent deterioration of MOSFET characteristics, the wafer is rotated 180 degrees and implanted twice from the left and right, but only once, which reduces the number of steps and reduces chip cost accordingly. be.

Further, although a gate array is taken as an example here, the same applies to any other integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a chip layout diagram taking the gate array of the present invention as an example. FIG. 2 is a chip layout diagram taking a conventional gate array as an example. FIG. 3 is an explanatory diagram of the ion implantation step of the process. FIG. 4 is a cross-sectional view of the ion implantation step of the process. 100... Input/output unit 101... Internal basic gate 102... Up/down input/output cell 103... Left/right input/output cell 110... Left/right input/output cell section 200... Wafer 201... ...MOSFET 202...MOSFET 203...Diffusion region 300...Poly gate 301...Diffusion region 302...Diffusion region 304...Photoresist 305...More than ion trajectory Applicant: Seiko Epson Co., Ltd.

Claims (1)

[Claims] In a semiconductor substrate on which an insulated gate field effect transistor (MOSFET) is formed,
A semiconductor device characterized in that all insulated gate field effect transistors (MOSFETs) in the same chip are oriented in the same direction.