JPH04152561A - Semiconductor device - Google Patents

Abstract

PURPOSE:To secure dimensions and micronization of a high resistance part by forming a boundary between a high resistance region and a low resistance region in the upper layer wiring above the connection aperture of two wiring layers. CONSTITUTION:A semiconductor device comprises at least two layers of semiconductors, and the upper wiring layer consisting of polycrystalline silicon has a low resistance region 8, to which impurities in high concentration are introduced, and a high resistance region 7, which contains a very small amount of impurities or does not contain impurities. In this structure, by providing the boundary between the high resistance part 6 of polycrystalline silicon and the low resistance part 7 above the connection aperture 9, the securing the dimension and the reduction of the high resistance part become possible. To realize this, if one changes the resist pattern 8, it is possible. At this time, it is supposed that the contact resistance between a gate electrode 4 and the polycrystalline silicon 7 becomes high, but supposing that the impurities of low resistance part are P, that the later heat treatment is performed at 900 deg.CN2 for thirty minutes, and that As is 1.8mum, it diffuses 1mum horizontally. Therefore, the contact resistance never becomes high, and even if it becomes high to some degree, it will be acceptable as long as it is smaller enough than the level of the resistance (GR-Tr) of the high resistance part.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to improvements in the structure of semiconductor devices.

[Conventional technology]

The conventional structure is shown in Fig. 2 (α) and (b) respectively.
A cross-sectional view is shown.

In the figure, 1 is a substrate, 2 is an element isolation insulating film 5 is a gate insulating film, 4 is a gate electrode, 5 is an interlayer insulating film, 6 is a polycrystalline silicon high resistance part, and 7 is a polycrystalline silicon low resistance part , 8, the resist pattern 9 is a connection opening.

Conventionally, resistors using polycrystalline silicon have been used, but
In particular, if a trace amount of impurities or no impurities are introduced, a high resistance is obtained and this is used in circuits.Static RAM is a well-known example.

[Problem to be solved by the invention]

In the prior art, as shown in FIG. 2Cb), the distance t between the boundary between the high resistance part 6 and the low resistance part 7 and the connection opening is determined by taking into account the alignment margin when forming the resist pattern 8. was set. However, with the miniaturization of elements, this alignment margin makes it difficult to reduce the memory cell size, for example in static RAM, and furthermore, if this is to be ensured, the dimension S of the high resistance itself must be reduced. This caused IDD8's no(ratsuki).

The present invention aims to solve such problems.

[Means to solve the problem]

The present invention consists of at least two layers of wiring, the upper wiring layer is made of polycrystalline silicon, and the upper wiring layer has a low resistance region doped with high concentration impurities and a high resistance region containing or not containing trace amounts of impurities. In a semiconductor device having a region, said 2
The semiconductor device is characterized in that there is a boundary between a high resistance region and a low resistance region in the upper layer wiring above the connection opening of the wiring layer of the layer.

〔Example〕

FIGS. 1A and 1B are a plan view and a sectional view showing an embodiment of the present invention, and the same reference numerals indicate the same parts.

In the structure of the present invention, by providing the boundary between the high resistance part 6 and the low resistance part 7 of polycrystalline silicon on the connection opening 9, it is possible to secure and reduce the size of the high resistance part. When trying to realize this, it is expected that the contact resistance between the gate electrode 4 and the polycrystalline silicon 7 will increase, but when the impurity in the low resistance part is P, the subsequent heat treatment 900
℃N.

When 1.8 μAs is assumed for 50 minutes, it diffuses in the lateral direction by 1 μ. Therefore, even if a structure like the present invention is used, there is no need to worry about the contact resistance becoming high (and even if it becomes a little high, it is fine as long as it is sufficiently smaller than the resistance (G r % T r ) level of the high resistance part. However, in reality, the above-mentioned No problem due to lateral diffusion.

It can also be seen that this structure can be realized by changing the resist pattern 8.

As described above, the structure of the present invention has been realized.

〔Effect of the invention〕

By adopting the structure of the present invention, it is possible to ensure the dimensions of the high resistance portion and to make it fine. This has made it possible, for example, to reduce the cell area of static SRAMs, increase their integration, and reduce costs.

[Brief explanation of drawings]

Figures 1 (α) to (b) and cross-sectional views. Figures 2 (α) to (b) and cross-sectional views. In the figures, 1... Semiconductor substrate 2... ......Element isolation insulating film 5...Gate insulating film 4...Gate electrode 5--...Interlayer insulating film 6 ......High resistance part of polycrystalline silicon 7.
・・・・・・Low resistance part of polycrystalline silicon 8...
. . . Resist pattern 9 . . . Connection opening) is a plane for explaining the prior art) is a plane for explaining the present invention

Claims (1)

[Claims] (1) In a semiconductor device consisting of at least two layers of wiring, the upper wiring layer is made of polycrystalline silicon, and the upper wiring layer has a low resistance region and a high resistance region into which high concentration impurities are introduced. A semiconductor device characterized in that there is a boundary between a high resistance region and a low resistance region in the upper layer wiring above the connection opening of the two wiring layers.